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2023-03-05mb/google/hades: Add baseboard device treeEric Lai
Add minimum device tree. Leave IOs default disable to optimize variant override complexity. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-05soc/mediatek/mt8188: Add bus protection for audio/video mtcmosgarmin chang
Bus protection is a HW mechanism to avoid bus hang and incomplete bus transactions. Bus protection HW must be enabled while the receiver of the transaction is not able to respond. BUG=b:264204465 TEST=build pass Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Signed-off-by: garmin chang <garmin.chang@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73375 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-05device/xhci: Add functions to work with resource pointersRobert Zieba
The XHCI device functions currently use functions that require a access to the device tree. Create variant of these functions that can operate with a resource* as an argument and refactor the existing device*-based functions to operate by calling the resource*-based variants. This is useful for stages like SMM that may not have access to the device tree. BRANCH=guybrush BUG=b:186792595 TEST=Ran on skyrim device, verified that XHCI ACPI tables are still generated correctly. Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05cpu/x86/smm: Add PCI resource store functionalityRobert Zieba
In certain cases data within protected memmory areas like SMRAM could be leaked or modified if an attacker remaps PCI BARs to point within that area. Add support to the existing SMM runtime to allow storing PCI resources in SMRAM and then later retrieving them. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05soc/intel/alderlake: Hook up ucode for RPL-P/H/UTim Crawford
Hook up microcode from 3rdparty repo for: - 06-ba-02 (CPUID signature: 0xb06a2) Change-Id: Icb2fc9350ebc33ef150f1ab5df1006ed956478d6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-04mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0011 for Hynix H58G56BK8BX068. Add new ram_id:0100 for Hynix H58G66BK8BX067. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) H58G66BK8BX067 4 (0100) BUG=b:270629852 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73252 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-04mb/google/skyrim/var/frostflow: Update DPTC and STT settingsFrank Wu
According to thermal_table_0215, adjust DPTC and STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04soc/amd/mendocino: Add STT support for dptc tablet modeChris Wang
Add stt settings for dptc tablet mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the clamshell/tablet mode. Run the WebGL aquarium with 5000 fish and verify that there is no power drop peak. Change-Id: Ib4aad3af8761b20084717b15a462edf4704b83cc Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73205 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-04soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang
The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-04xeon/spr: Set ACPI CPU string for 12bitNaresh Solanki
On platforms with more than 255 cores the ACPI CPU string would overflow and generate duplicates. Fix that by changing the string to hex and use 3 digits. Test: Able to boot without ACPI errors on IBM/SBP1 which has 384 actives cores. Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-04mb/system76/adl-p: Add Oryx Pro 10 as a variantTim Crawford
oryp10 is nearly identical to the oryp9, with the differences being: - Uses DDR5 RAM instead of DDR4 RAM - Uses Realtek ALC1306 instead of TI TAS5825M - Has an option for OLED display Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/adl: Add Oryx Pro 9 as a variantTim Crawford
The Oryx Pro 9 (oryp9) is an Alder Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - Both M.2 NVME SSD slots (with MZVL2500HCJQ) - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - Discrete/Hybrid graphics - HDMI output (requires NVIDIA GPU) - Mini DisplayPort output (requires NVIDIA GPU) - Detection of devices in TBT slot on boot Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04soc/intel/alderlake: Allow channel 0 for memory-downTim Crawford
Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the System76 Lemur Pro 11 (lemp11). Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/adl: Add Lemur Pro 11 as a variantTim Crawford
The Lemur Pro 11 (lemp11) is an Alder Lake-U board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - DIMM slot (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - On-board RAM: Requires CB:65567 - Detection of devices in TBT slot on boot Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dtScott Chao
BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73174 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04soc/intel/alderlake: Add UWES ASL into xhci.aslScott Chao
Align support for enable wake-on-usb attach/detach as was introduced in Cannon Lake in commit 811284125f0a ("soc/intel/cannonlake: Add UWES ASL into xhci.asl"). This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <Scott_Chao@wistron.com> Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-04security/tpm: add TPM log format as per 2.0 specSergii Dmytruk
Used by default for all boards with TPM2 which don't specify log format explicitly. Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Ticket: https://ticket.coreboot.org/issues/422 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-03-04security/tpm: add TPM log format as per 1.2 specSergii Dmytruk
Used by default for all boards with TPM1 which don't specify log format explicitly. Ticket: https://ticket.coreboot.org/issues/423 Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-03-04mb/system76: Add custom backlight levels for Intel GMATim Crawford
Add custom backlight levels for all models except: - addw1/addw2: Uses an OLED display - bonw14: Does not use the iGPU Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/tgl-u: Leave TBT LSX0 as FSP configuredTim Crawford
Do not reconfigured LSX0 so that the FSP values are used. Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04{ec,mb}/system76: Move smbios_system_wakeup_typeTim Crawford
Move the implementation of smbios_system_wakeup_type from the mainboards to the EC for all models that use System76 EC (everything except KBL). Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/google/brya: remove the skolas baseboardNick Vaccaro
The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-03soc/amd/cezanne/graphics: simplify map_oprom_vendev implementationFelix Held
Phoenix' implementation of map_oprom_vendev uses this simplified implementation, so port this back to Cezanne too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73387 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-03mb/google/skyrim: Disable USE_SELECTIVE_GOP_INITMartin Roth
This is causing some issues, so disable it until those issues can be resolved. BUG=b:271437658, b:271199389, b:270077971 TEST=Screen always lights up on boot & after S0i3 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-03acpi: Add SRAT x2APIC table supportNaresh Solanki
For platforms using X2APIC mode add SRAT x2APIC table generation. This allows to setup proper SRAT tables. Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-03soc/intel/xeon_sp: Fix CBMEM corruptionPatrick Rudolph
On the 4 socket IBM/SBP1 platform with 384 cores lots of space for ACPI tables is required. Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption. Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-03drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacksJan Samek
As discused earlier, the callback name 'mb_adjust_cfg' was considered too generic. The new naming is chosen to be consistent with other drivers' callback names designed to be used at mainboard level. Also other functions, namely 'mb_get_edid' and 'mb_select_edid_table' are renamed accordingly. BUG=none TEST=Builds for siemens/mc_apl{1,4,5,7} and siemens/mc_ehl boards complete successfully. Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-03mainboard/protectli/vault_ehl: Add initial structureKacper Stojek
This patch adds base code for the Protectli VP2420. The GPIO config has been extracted with inteltool from the stock firmware and then parsed with intelp2m. As of now, the platform runs with edk2 with no apparent issues. Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-03-03lib: set up specific purpose memory as LB_MEM_SOFT_RESERVEDJonathan Zhang
CXL (Compute Express Link) [1] is a cache-coherent interconnect standard for processors, memory expansion and accelerators. CXL memory is provided through CXL device which is connected through CXL/PCIe link, while regular system memory is provided through DIMMs plugged into DIMM slots which are connected to memory controllers of processor. With CXL memory, the server's memory capacity is increased. CXL memory is in its own NUMA domain, with longer latency and added bandwidth, comparing to regular system memory. Host firmware may present CXL memory as specific purpose memory. Linux kernel dax driver provides direct access to such differentiated memory. In particular, hmem dax driver provides direct access to specific purpose memory. Specific purpose memory needs to be represented in e820 table as soft reserved, as described in [2]. Add IORESOURCE_SOFT_RESERVE resource property to indicate (memory) resource that needs to be soft reserved. Add soft_reserved_ram_resource macro to allow soc/mb code to add memory resource as soft reserved. [1] https://www.computeexpresslink.org/ [2] https://web.archive.org/web/20230130233752/https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.32&id=262b45ae3ab4bf8e2caf1fcfd0d8307897519630 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52585 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-02mb/google/rex: Enable VPURavi Sarawadi
BUG=b:270529665 TEST=Verify the build and boot on Rex board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-02amdfwtool: Change .rom.efs to .rom and .rom to .rom.bodyZheng Bao
To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-02soc/intel/alderlake: Hook up ucode for RPL-S/HX B0Tim Crawford
Hook up microcode from 3rdparty repo for: - 06-b7-01 (CPUID signature: 0xb0671) Verified microcode blob was in CBFS on Clevo PD50SNE (system76/serw13), which has an i9-13900HX. Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-02mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie3493af340a42035ee537d83b1542be1b87d8f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-03-02acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-02mb/siemens/mc_ehl*: Correct comment in gpio.cMario Scheithauer
There were two wrong comments in all mc_ehl gpio.c files. This patch corrects the incorrect comments. Change-Id: Iea356db177227d89b91be32a4e2367c612b77350 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72458 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/siemens/mc_ehl4: Remove TPM from devicetree and KconfigMario Scheithauer
This mainboard does not use security features like TPM. Change-Id: Ieebbf12fc844573ffadb089da78062dd2033517a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/siemens/mc_ehl: Move TPM Kconfig switches to variantsMario Scheithauer
The upcoming mc_ehl4 variant is the first Siemens Elkhart Lake mainboard without a TPM. For this reason, the corresponding Kconfig switches must be moved to variant level. To prevent Jenkins build from complaining, the TPM is removed in the following patch. Change-Id: Ic73ccd1b52e57c1cf1dd7337b0e28beaadbece8e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/siemens/mc_ehl2: Set RGMII output impedance manuallyMario Scheithauer
Measurements have shown that the automatic calibrated values for RGMII output impedances are too low. For this reason, set the PMOS value to 16 and the NMOS to 13. Change-Id: Ic3382889d3281faccb03819f9680a9763703b2a1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73019 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02drivers/net/phy/m88e1512: Add a way to set output impedance manuallyMario Scheithauer
This patch provides the functionality to set the RGMII output impedance manually. To ensure that no race condition occurs, the driver strength values for PMOS and NMOS should be written to the RGMII output impedance calibration override register first and then the force bit should be enabled with a second write to this register. Link to the Marvell PHY 88E1512 datasheet: https://web.archive.org/web/20230125074158/https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-ethernet-phys-alaska-88e151x-datasheet.pdf Change-Id: I87fa03aa49514cdc33d2911d7f23386c8f69d95b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02drivers/net/phy/m88e1512: Switch the page back to 0 only onceMario Scheithauer
When the configuration of Marvell PHY 88E1512 is finished, then switch the page back to 0 only once at the end of the Init function. Change-Id: I9e516870a7c5928724df2bd3ac9c5c8f3249af2e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73017 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-02mb/siemens/mc_ehl4: Add new board variant based on mc_ehl1Mario Scheithauer
This mainboard is based on mc_ehl1. In a first step, it contains a copy of mc_ehl1 directory with minimum changes. Special adaptations for mc_ehl4 mainboard will follow in separate commits. Change-Id: I3c1f2cf4a3dcae58895f6d14a7fce46b2825e6ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72427 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02vc/siemens/hwilib: Change uint32_t return type to size_tJan Samek
The commit fcff39f0ea47 ("vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'") changed the 'dstsize' input parameter type from uint32_t to size_t. This patch changes also the return parameter, which is often directly compared with the aforementioned input parameter value. This should introduce no change on 32-bit builds and stay consistent across the project in the case of 64-bit builds and avoid comparisons of integers of different width here. BUG=none TEST=No changes to hwilib behavior on any of the siemens/mc_apl1 or siemens/mc_ehl variants. Change-Id: I0a623f55b596297cdb6e17232828b9536c9a43e6 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-03-02soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC supportChris Wang
Add a new parameter STT_ALPHA_APU' for each DPTC mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the expected setting. Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2023-03-02mb/siemens/mc_ehl2: Fix GPIO settingsMario Scheithauer
With the latest hardware revision, the two GPIOs GPP_B15 and GPP_E19 are no longer connected to a native function. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: I266612f041b749aa83b366497b4211fc075c7bd7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02device/pciexp_device.c: Do not enable common clock if already activeWerner Zeh
The Common Clock Configuration (CCC) is a PCIe feature for cases where the upstream and downstream device of a link share the same reference clock. After a change in this setting a link re-training is mandatory to make it effective. On recent Intel platforms (tested on Elkhart Lake) the FSP code which is executed before coreboot performs the PCI scan already enumerates all PCI buses for its internal uses. While this is done, all the PCI express features of a link are configured, which includes CCC. If the link supports common clock, FSP performs the link re-training already. When the execution flow is returned to coreboot, the same link treatment is applied again (coded in 'pciexp_tune_dev()') and CCC is enabled a second time, just a few milliseconds after FSP did this already. Because enabling CCC requires a link re-training, there are two link re-trainings on the PCIe link within a few milliseconds (one from the FSP code and one from coreboot) which can lead to issues with a connected PCIe device on this link. In particular, link issues were discovered with a Pericom PCIe switch (PI7C9X2G608) on mc_ehl1 where the link has stalled for a while after the second re-training. This in turn leads to non-initialized PCI devices on the bus after coreboot has finished. This patch checks if CCC is already enabled on a link and does not perform the steps to enable it again in coreboot which safes a link re-training (and thus execution time) and a potential link stability issue. Test=Check log output on mc_ehl1 which shows the following lines: [DEBUG] PCI: pci_scan_bus for bus 09 [DEBUG] PCI: 09:00.0 [8086/1533] enabled [INFO ] PCIe: Common Clock Configuration already enabled Change-Id: I747fa406a120a215de189d7252f160c8ea2e3716 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73310 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `K3KL6L60GM-MGCT`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id0925ccec014c9c535178ed3d908e60889df624d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign H58G56BK7BX068 1 (0001) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9eea7e277628992be9b7768a678a50425444002a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02soc/mediatek: Add config to control DRAM scrambleXi Chen
The DRAM scramble feature enhances DRAM data protection. When it's enabled, the written DRAM data will be scrambled and hence can prevent the data from being hacked. This feature would make debugging more difficult (for example ramoops would be lost after reset). Therefore, add a new config to allow enabling or disabling the feature from coreboot, without having to maintain two versions of the DRAM calibration blob. BUG=b:269049451 TEST=build pass and check scramble enable or disable successfully Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: Ib4279bc1cc960fae9c9f5da39f4448a5627288d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-02mb/google/brask/var/constitution: Enable Fast VMode for constitutionMorris Hsu
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I1e68f708b7740567e24f8a3ddb9832aeec7ee6b5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73247 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-01mb/google/brya/acpi: Remove extra DC boost byteTarun Tuli
The DC boost bit was intended to be in the Controller Params word rather than its own byte. Correct this error. BUG=b:214581372 TEST=build Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-01soc/intel/xeon_sp/spr: Select DISABLE_ACPI_HIBERNATE to remove S4 stateTim Chu
Server platform doesn't have S4 state so select DISABLE_ACPI_HIBERNATE to remove S4 state from available sleepstates. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ie5ddb1a98cd5bbd854b915c93694d1ebcb9bddd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-01mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 sJan Samek
The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. BUG=none TEST=Test link stability using a panel with minimum re-power delay of 1 s. Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-01soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeSean Rhodes
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this GPIO to 1 or 0 will not change the HDA GPIO configuration; it will make the sound work when set to 1, or not work when set to 0. Remove the incorrect comment and make the UPD configurable from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-03-01soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbolSean Rhodes
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-28soc/amd: introduce and use PSTATE_MSR macroFelix Held
Instead of adding the P-state number to the PSTATE_0_MSR number to get the P-state MSR number for the rdmsr call, provide a macro that directly calculates the MSR number for a given power state. Also drop the unused PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs available in the hardware. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-28soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usageFelix Held
The latency values in the _CST package override the values in the p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino, Phoenix and Glinda generate_cpu_entries generates the _CST packages for each CPU device. The coreboot code for Stoneyridge doesn't generate _CST packages for the CPU objects, but those are provided via the PSTATE SSDT binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI tables. The AGESA reference code also sets those two FADT entries to the equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED so this also matches the AGESA behavior. From the ACPI 6.4 spec: "Values provided by the _CST object override P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT." Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-28mb/amd/gardenia,pademelon/mainboard: use ACPI_SCI_IRQ definitionFelix Held
Use the ACPI_SCI_IRQ definition for both the PIC and APIC IRQ number in the fch_irq_map table. Before the PIC mapping was set to PIRQ_NC, but both mb/google/kahlee and the other amd mainboards using newer SoCs set both the PIC and APCI IRQ number to ACPI_SCI_IRQ, so change this here to match the other mainboards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I29dde7ca8d2ecf00d8174c2d793ef1ad55ae3e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73322 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28mb/google/kahlee/mainboard: use ACPI_SCI_IRQ definitionFelix Held
Use the ACPI_SCI_IRQ definition instead of a magic value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia860668b5c93b1b8882459d9f983cf3a23d16392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73321 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/stoneyridge/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
IRQ9 is used as ACPI SCI IRQ, so add a define for that and use it in the code like it is also done in the other SoCs in soc/amd. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddb51d70c15ab1d7088f62b61e22510bd1b30b1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73320 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/picasso/acpi: use ACPI_SCI_IRQ definitionFelix Held
Since there's a define for the ACPI_SCI_IRQ 9, use the define instead of a magic number in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23c8f62929f3f66192698e10826d10329ef3d8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/73319 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/picasso,stoneyridge/acpi: drop unneeded res2 FADT assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the res2 FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa69ae61bea82acf66e7210c4103ef48e36dbdd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73318 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/common/block/apob/apob_cache: use enum cb_errFelix Held
Use enum cb_err to return an error/success state instead of an int in get_nv_rdev and get_nv_rdev_rw. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I73706a93bc1dbc8556e11885faf7f486c468bea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/common/block/apob/apob_cache: include types.hFelix Held
The bool type is used although stdbool.h isn't included. Include types.h which will include both stdint.h and stdbool.h Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5213ddae3ceb36e0b2e09f8ef3f7f414ebdf187f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73316 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28mb/system76: Rename adl-p to adlTim Crawford
The directory holds boards other than ADL-P, such as ADL-U and ADL-H. Change-Id: I8e1b67f83d649cd07645a4a519ba1bf2f6f5e7c6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-02-28soc/intel/meteorlake: Hook up FSP hyper-threading setting to option APIEran Mitrani
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overridden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Port of commit a182faeb88a0 ("soc/intel/alderlake: Hook up FSP hyper-threading setting to option API") Change-Id: I0b3e1a4049312c6b1ec950382c92274e0350001f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-28include/device/pci_def.h: Fix typo in commentWerner Zeh
Fix typo in the comment for Common Clock Configuration. Change-Id: Idd01e787458a9090d53b9a57547b8158480dcc16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2023-02-27mb/google/skryim: Add RECOVERY_MRC_CACHE FMAP sectionKarthikeyan Ramasubramanian
Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP section to cache the MRC training data in recovery mode. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS directory entry is populated with the appropriate MRC_CACHE FMAP section. Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-27mb/google/skyrim/var/winterhold: Use fw_config to probe FPEricKY Cheng
Use fw_config to probe fingerprint. BUG=b:269986245 TEST=emerge-skyrim coreboot chromeos-bootimage. Test result is pass with 1000 reboot cycles. Change-Id: I4b4bca42dd78dfd5b8636ff3cb05406d2d0c94f7 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-27mb/google/brya/var/osiris: Enable Fast VMode for osirisDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I35f577e1bab0f8dda10061903df13730e2c8ee04 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-27mb/google/brya/var/osiris: use RPL FSP headersDavid Wu
To support an RPL SKU on osiris, osiris must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for osiris so that it will use the RPL FSP headers for osiris. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot osiris to kernel. Cq-Depend: chromium:4290627, chrome-internal:5516851 Change-Id: If8de42a82fd85ffa8b9836e6024f119bc798f4fc Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-27soc/amd/stoneyridge/acpi: use available number of CPUs for CPU entriesFelix Held
It's sufficient to generate CPU devices for all available CPU cores/ threads instead of for the maximum number of possible CPU cores/threads. TEST=google/careena with 2 cores still boots and Linux doesn't complain about ACPI errors due to referenced but not present CPU objects. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6850edfa305304060092cb5480f4296f4f5ddacc Reviewed-on: https://review.coreboot.org/c/coreboot/+/73070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/amd/mendocino: Populate type 0x63 entry with right MRC CacheKarthikeyan Ramasubramanian
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS directory entry is populated with the base and size of appropriate MRC cache. Change-Id: I49ec4f64e33c4d5780a7fe6a5540eab42b6cec9f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/amd/common/block/apob_cache: Add support for RECOVERY_MRC_CACHEKarthikeyan Ramasubramanian
If a mainboard has RECOVERY_MRC_CACHE and the recovery mode is enabled, then use APOB data from that section and make any updates to that section. Otherwise continue to use DEFAULT_MRC_CACHE section. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. When in normal mode, DEFAULT_MRC_CACHE is used. Normal Mode Boot1: ------------------ [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [INFO ] APOB RAM hash differs from flash [SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x0/0x1e000 [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] SF: Successfully erased 122880 bytes @ 0x0 [INFO ] Updated APOB in flash Normal Mode Boot2: ----------------- [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] APOB hash matches flash When the device is in recovery mode, RECOVERY_MRC_CACHE is used. Recovery Mode Boot1: -------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [INFO ] APOB RAM hash differs from flash [SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x650000/0x1e000 [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] SF: Successfully erased 122880 bytes @ 0x650000 [INFO ] Updated APOB in flash Recovery Mode Boot2: -------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] APOB hash matches flash Switch from Recovery Mode to Normal Mode: ----------------------------------------- [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] APOB hash matches flash Switch from Normal Mode to Recovery Mode: ----------------------------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] APOB hash matches flash Change-Id: I93f357e407c98b6e5fca495f4f779fad54a3430f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/intel/elkhartlake/romstage/fsp_params.c: separate debug paramsMichał Żygowski
This commit separates setting FSP debug params from the rest of code and configures FSP serial port parameters. Other ports (0x3E8 and 0x2E8) are omitted since Elkhart Lake FSP only supports 0x3F8 and 0x2F8. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/72404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-27mb/google/nissa/var/xivu: Disable world-facing microphoneIan Feng
Remove world-facing microphone for xivu360. Switching to world-facing camera will use the user-facing microphone to record sound. BUG=b:263927799 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ibb720974b6488ce4453081e0bc5b4e7f34a6b0f6 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-27mb/google/dedede/var/dibbi: Improve USB2 strengthAmanda Huang
BUG=b:269786649 TEST=build and test USB2 port function works fine BRANCH=dedede Change-Id: I63928a0d8ce6b2365250fd96572f4a2db948c19d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-02-27mb/google/brask/var/constitution: use RPL FSP headersMorris Hsu
To support an RPL SKU on constitution, it must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for constitution so that it will use the RPL FSP headers. BUG=b:267539938 TEST=emerge-brask intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: Ie4f5eb6ebb372ad07308ff25c9eb69a83793c656 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73246 Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-27mb/google/brask/var/constitution: Update overridetreeMorris Hsu
Update override devicetree based on schematics. BUG=None TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I883a806950821e6306242975764930035a94888e Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-02-27mb/google/rex: Remove `fixme` from gpio.hKapil Porwal
Remove `fixme` from gpio.h since it has been addressed. BUG=none TEST=Only a cosmetic change Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I79a2493dba6becd4b8c1ebf37e452a5a173eb396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-27ec/google/chromeec: Update ec_commands.hTim Van Patten
Update ec_commands.h from the EC repo at: "8441cf4 Add host event: EC_HOST_EVENT_BODY_DETECT_CHANGE" This is an exact copy of the EC repo's ec_commands.h with the exception of updating the copyright message. BUG=b:261141172 BRANCH=none TEST=built coreboot for skyrim Change-Id: I9892c0c3518f63d357459861e8fa1b7f5f494e68 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-02-27soc/amd/common/fsp/dmi.c: Fill in mem manufacturer from CBIMartin Roth
Because the ChromeOS boards don't fill a manufacturer in for the memory SPDs, that information isn't available from the FSP. We can get the Manufacturer ID based on the memory name from CBI instead. Use this information to fill in an ID so that the manufacturer name is available in the SMBIOS information. BUG=None TEST=Look at dmidecode output Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I810c3191180dd3b566d7ea64006f29b625b10526 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27device/dram/spd.c: Add Nanya's Manufacturer IDMartin Roth
There is a Nanya device used on one of the Google Guybrush devices, so add it to the list of SPD manufacturer names. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia449f4d14385cdd5a2548e2a05e3928ea3602c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-02-27soc/amd/common/fsp/dmi.c: Add dmi_type16 ECC to memory structMartin Roth
The DMI error correction type was not being filled in, so was reporting as "Error Correction Type: <OUT OF SPEC>". This patch fixes that. Since it's now filling in information for both Type 16 & 17, rename the function to reflect that. BUG=None TEST=dmidecode now reports the type correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6b51612d808c63de1acd2be952cb6c152f8a1be5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27mb/amd/birman/bootblock.c: Skip EC configuration in SimNowFred Reitberger
SimNow does not support the Birman EC, so skip the EC configuration steps when building for SimNow. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I6e879a13a119d593674d3403d4e1b32e0e244d9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-27mb/amd/birman,chausie: Enable SimNow capabilitiesFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia7e594ca2b6ea3cd9d6f60e7dcd1ba6ebabf85cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-27soc/amd/common/block/simnow: Add SimNow Kconfig optionsFred Reitberger
Add option for mainboards to target builds for SimNow. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id765437b69f1bc3a9f9d7858edcd27e687d5a7f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-27tree: Move 'asmlinkage' before type 'void'Elyes Haouas
Move 'asmlinkage' before the function type for consistency. Change-Id: I293590ef917b78c6ed3d151cd0080e42d0f10651 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73259 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-26soc/intel/xeon_sp: Drop unused cpu.h headerArthur Heymans
Change-Id: I42856424d3b55107f1758fb05f7ddbee3550d8b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-26lib/gnat: Remove Compiler_Unit_Warning pragmasElyes Haouas
'pragma Compiler_Unit_Warning' is removed upstream: https://gcc.gnu.org/git/?p=gcc.git&a=search&h=HEAD&st=commit&s=pragma+Compiler_Unit_Warning Fix: GCC libgnat-x86_32/lib/gnat/interfac.o interfac.ads:36:08: warning: unrecognized pragma "Compiler_Unit_Warning" [-gnatwg] Change-Id: I6d7efab132441dd3cc62a53b7322e9fd355e5059 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-25soc/intel/{adl, cmn, mtl}: Refactor MP Init related configsSubrata Banik
This patch optimizes CPU MP Init related configs being used within multiple SoC directory and moving essential configs into common code to let the SoC user to choose as per the requirement. TEST=Able to build and boot google/kano and google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-24mb/google/skyrim/var/winterhold: Remove gpio-keys ACPI node for PENHEricKY Cheng
Remove ACPI node for pen eject event to meet project design. BUG=b:265106657 TEST=emerge-skyrim coreboot chromeos-bootimage Change-Id: I732de49c6319397d93671c48a6518c7c7e955fdc Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73154 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-24Revert "soc/qualcomm: Increase SPI frequency to 75 MHz"Shelley Chen
This reverts commit 363202b43589ec240c4a0c8f5b449fbd5c1333f8. Reason for revert: Seeing some bit flips on the SPI bus, but cannot repro reliably on local builds. Going to downgrade back to 50 MHz to see if builder builds are more stable on each variant as a result. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I4fe76bac915e3b3c794821cd160a66824e38ea83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73214 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24mb/google/skyrim/var/crystaldrift: Generate RAM IDs for new memory partsYunlong Jia
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 3 (0011) BUG=b:265190498 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I860f10552e4e4180e09ab805ca82b108fdc8f21a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73049 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24Revert "mb/google/brya/var/gladios: Update gpio table"Robert Chen
This reverts commit 3eb17b91daac0b3acaffb01568d724d23c6f0eea. Reason for revert: PLTRST only keeps 18xms and it's too short for eMMC disk fully reset. Change-Id: If4277cb600bfe4e071959dacaf204fe7d3518f68 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73202 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-24Revert "mb/google/brya/var/lisbon: Update gpio table"Robert Chen
This reverts commit 0e0f9e51c4c4f190cbe7ef5bffa138601c644d3c. Reason for revert: PLTRST only keeps 18xms and it's too short for eMMC disk fully reset. Change-Id: I13b93747bdb4d39de1ffcfdc020648871fa6e048 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73203 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-24mb/google/brask/var/constitution: update gpio settingsMorris Hsu
Update GPP_E12,GPP_E13,GPP_H19 in ramstage. Update GPP_F11 in bootblock. TEST=emerge-brask coreboot Change-Id: Icdca7f574282da140ec64cea9cdda3ebccbe3eb8 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73194 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/ehl: Select CSE defined ME spec version for elkhartlakeDinesh Gehlot
Elkhartlake based SoCs uses Intel's Management Engine (ME), version 15. This patch selects ME 15 specification defined at common code and removes elkhartlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I3186f509c63b3a892c72cb1fa08fc094735d6eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73245 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/cnl: Select CSE defined ME spec version for cannonlakeDinesh Gehlot
Cannonlake based SoCs uses Intel's Management Engine (ME), version 12. This patch selects ME 12 specification defined at common code and removes cannonlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ifc64cf63736bb730492b1732a22669a0415816a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73140 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/jsl: Select CSE defined ME spec version for jasperlakeDinesh Gehlot
Jasperlake based SoCs uses Intel's Management Engine (ME), version 13. This patch selects ME 13 specification defined at common code and removes jasperlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Icf4bc651e94d6ec977ed8f2381d7184337dc1ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73139 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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