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2014-12-28RELOCATABLE_RAMSTAGE: Fix weak symbols in ACPIKyösti Mälkki
After relocation the weak symbols are no longer NULL. Always have empty stub function defined. Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7955 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-28RELOCATABLE_RAMSTAGE: Fix weak symbols with ramstage_cacheKyösti Mälkki
We had NULL reference with cache_loaded_ramstage() if CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM was not set so boot never proceeded to ramstage. Cache implementation outside CBMEM provides means for platform-specific location so there is no need of weak attributes here. Change-Id: I1eb1a713896395c424fde23252c374f9065fe74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7954 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-27samsung/exynos*/Makefile.inc: Simplify unnecessary ifeqEdward O'Callaghan
It's not needed, as we can use a simpler macro instead. Change-Id: Ib96f5cfa434d0383ee3bfe49995a8f8830987f20 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7925 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-26blaze: change ramcode 0001/0010 to use 792MHz bctJerry Wang
This change updates the cfg file for Micron/Samsung 2GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad Original-Signed-off-by: Jerry Wang <jerryw@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/199296 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit cb70674c6551c8c36d2fd2d220e0f677ed2c6b24) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I11222bc1453a76cc27c2be169be5d3481ed7cfe7 Reviewed-on: http://review.coreboot.org/7902 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26nyan*: Detect watchdog resets and reset the whole machine.Gabe Black
When a watchdog reset happens, the SOC will reset but other parts of the system might not. That puts the machine in a funny state and may prevent it from booting properly. BUG=chrome-os-partner:28559 TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/198582 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7900 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-26tegra124: Add a utility function to read the cause of the most recent reset.Gabe Black
When a watchdog reset happens, the SOC will reset but other parts of the system might not. In order to detect those situations we can check the rst_status register in the PMC. BUG=chrome-os-partner:28559 TEST=With this and a change which uses the new function in the nyan boards, built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset, software reset ("reboot" command from the terminal), and through watch dog reset. Verified that the new code only triggered during the watchdog reset and that the system rebooted and was able to boot without going into recovery mode unnecessarily. BRANCH=nyan Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/198581 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72 Reviewed-on: http://review.coreboot.org/7899 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-26blaze: change ramcode 0000 to use 792MHz bctKen Chang
The original sdram-hynix-2GB-792.inc was just copied from nyan bct file. This change updates the cfg file for Hynix 2GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I9534b4df6d35193179de124309df12ed830098a0 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197660 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 797dabe54f2679bb5717961dda1947df453eb0f1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie67bedb29d5d9c3a3b58d949ddf9600716c385ec Reviewed-on: http://review.coreboot.org/7898 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26nyan*: I2C: Implement bus clear when 'ARB_LOST' error occursTom Warren
This is a fix for the 'Lost arb' we're seeing on Nyan* during reboot stress testing. It occurs when we are slamming the default PMIC registers with pmic_write_reg(). Currently, I've only captured this a few times, and the bus clear seemed to work, as the PMIC writes continued (where they'd hang the system before bus clear) for a couple of regs, then it hangs hard, no messages, no 2nd lost arb, etc. So I've added code to the PMIC write function that will reset the SoC if any I2C error occurs. That seems to recover OK, i.e. on the next reboot the PMIC writes all go thru, boot is OK, kernel loads, etc. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197732 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc Reviewed-on: http://review.coreboot.org/7897 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-26soc/samsung/exynos5250/clk.h: Trivial, fix spelling in commentsEdward O'Callaghan
Change-Id: Iaacd4d7977ddeff4204acdc32d4d13fd88b6660b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7928 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-26soc/samsung/exynos5250/clock.c: Trivial whitespace fixesEdward O'Callaghan
Reduce difference with exynos5420/clock.c by fixing some whitespace and an include directive. Change-Id: Ifbdd61c8300f3988f5f729fe7d6124ac8a9b7821 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7926 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-26soc/samsung/exynos: Sync 'power.c' between chip variantsEdward O'Callaghan
Change-Id: I06d83be840b49ee7523b34e1dba5ec038256b3f4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7918 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-25soc/samsung/exynos: Make 'ps_hold_setup()' staticEdward O'Callaghan
Change-Id: I272fea9c2767c341e8a545bf7a9ac18eefa2bda5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-23TPM: Fix i2c driver dependencyKyösti Mälkki
Change-Id: I59545ef734dff41ba55dcddd541c54b17b0855bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7914 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-22hp/pavilion_m6_1035dx: Enable IOMMUAlexandru Gagniuc
Change-Id: Ia14490c9074d35b7dde99e38b4ee169d4e4589a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7678 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-22amd/agesa/f15/Proc/Common/S3SaveState.c: Sync with f15tnEdward O'Callaghan
Change-Id: If46079c1affc7d74767c4215467fd6754b24f20c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7576 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-22lib/edid.c: Fix mismatch between format string and variable typeAlexandru Gagniuc
Use 'd' instead of 'hhd' when printing absolute year of manufacture. This is the correct type in this case, as the result is autoatically promoted to int. Change-Id: Ice4155bb1a04f206ae55c45c260089d6971b77d1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7885 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Use common agesawrapperKyösti Mälkki
Callout FCH_OEM_CONFIG is made during AMD_INIT_RESET, so it was required to provide GetBiosCallOut here too. Change-Id: I0eab858677d14536293385ca37daab3e538132e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7826 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam15tn fam15rl fam16kb: Add OemInitMid()Kyösti Mälkki
Change-Id: Icbad42168ec3afb7780c0c2ddc17aa405e08d693 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7825 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add OemCustomize hooks structureKyösti Mälkki
We should potentially provide an OEM platform hook to manipulate parameters around any entry point to AGESA. Use structure for such ops to avoid weak functions and lots of empty function stubs. Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7824 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Ignore error in OemCustomizeInitEarly()Kyösti Mälkki
It does not really matter if we continue or return after a failed assertion, system configuration is invalid anyway. Change-Id: I5ba47ee3fd6c5ff97b9229f8bfc9db08873b08ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam15: Unify agesawrapperKyösti Mälkki
Disable TSC output for now. Change-Id: I078b4f0170aaf0ada58e464cf609c234204f8196 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7822 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Common laterunaptask()Kyösti Mälkki
Change-Id: I580f975aa987a333074de3d63744ad5f9008377d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7821 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Common agesawrapper_amdinitlate()Kyösti Mälkki
Change-Id: I3d532989559ffd7fd0f63e15c2c60bcfe5ec9101 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam15: Ignore AmdCreateStruct() errorsKyösti Mälkki
Change-Id: I1b7c95e08d74784e0f144cd5836d46bda64a3596 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7819 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Use memset() on agesawrappersKyösti Mälkki
Change-Id: Icc8da62c6d1644e16f7db6c634796ad597c755c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7818 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam12 fam14: Use lowercase void in agesawrappersKyösti Mälkki
Change-Id: I1755796049c2c3f2090cd6a4b4e28a71b807c7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7817 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam14: Add amd_initenv()Kyösti Mälkki
Not part of wrapper to AGESA, but workaround for enable_resources(). Also remove remains of comments in non-fam14 wrappers. Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7816 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add amd_initcpuio() and amd_initmmio()Kyösti Mälkki
These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7815 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20amd/torpedo: Drop unused code in agesawrapperKyösti Mälkki
Change-Id: I4c7fdfb64689cc8ba7e00bd7966d5c5857baf7c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7814 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam14: Increase MMCONF regionKyösti Mälkki
Increase to max 64 buses, as there are no benefits of limit 16. NOTE: It appears there is no matching (early) programming of the region to non-posted MMIO. Change-Id: I664789f7bd90992840e5817555cd3621c2d1e86c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7813 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam12: Fix MMCONF regionKyösti Mälkki
MMIO for non-posted region used hard-coded setting for 64 buses while MSR programming was for 256 buses. Change-Id: I690237dd459f7b7b4da68ae55ae9d22b79e5f255 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7812 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19qemu-armv7: Trivial style fixesDavid Hendricks
Minor style fixes to avoid future bikeshedding. - Opening brace for functions go on their own lines. - use fixed-length types where appropriate. BUG=none BRANCH=none TEST=it compiles Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: If9855d32c8ed1f5977937806c8c4cce65dd7d450 Original-Reviewed-on: https://chromium-review.googlesource.com/196955 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit e2bfeed18636af6b532e2e8f118de22a658fe41b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/mainboard/emulation/qemu-armv7/uart.c Change-Id: I8e09db53534802262168e65ec4cd47b96386490a Reviewed-on: http://review.coreboot.org/7867 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19nyan*: Clear VDDIO_SDMMC3 to reset SD card reader.Hung-Te Lin
When across warm reset, if VDD_3V3_SD_CARD gets power-cycled but VDDIO_SDMMC3 does not, we will get ~1.5V leakage on VDD. To fix that, we reset VDDIO_SDMMC3 to 0 along with VDD_3V3_SD_CARD in Coreboot. Payloads must turn on VDDIO_SDMMC3 explicitly before accessing SD card. Note the warnings of "VDD_SDMMC must set early" in comment seems only happens on U-Boot and can be removed. BUG=chrome-os-partner:27053 BRNACH=nyan TEST=Ctrl-U to boot from SD card, login and type "reboot", then Ctrl-U to boot again. Without this patch, system will fail in loading kernel. Original-Change-Id: I7f85995317d18587d514ea3afcff3bfea0a33e93 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196961 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 2cfdb78d9dc229a3c06f19bbe137d59d923908a4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie7d814e0424478c35a56fbc959437ee6a555684a Reviewed-on: http://review.coreboot.org/7866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19nyan*: Disable SD card reader power gpio.Hung-Te Lin
When warm booting, SD card reader on Tegra 124 needs to be reset by setting power GPIO to zero. Since we don't really access SD card in Coreboot, set it to zero and let payloads enable power when they need to access SD cards. CQ-DEPEND=CL:196783 BRANCH=nyan BUG=chrome-os-partner:27053 TEST=emerge-nyan coreboot depthcharge chromeos-bootimage # With related changes in depthcharge, boots SD card successfully. Original-Change-Id: I2d368eb9480c978e9e343648b58a729028c94622 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196774 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 62bb7d04dff1a87474a8557f144b24e6b7d006ae) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3429535d0d032f9db89d8e70a525a6281102537a Reviewed-on: http://review.coreboot.org/7865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19nyan*: Add fast link training functionsJimmy Zhang
Some panels (including those on Big DVT) cannot work fine without link training before sending the video signals, especially multi-lane Full HD panels. We need to use the fast link training functions from kernel to support them. BRANCH=Nyan BUG=chrome-os-partner:28128, chrome-os-partner:28129 TEST=tested on nyan, nyan_big dvt. Vince verified on Full HD panels. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ifde8daf0ebdc6fb407610d3563f3311b2a72dbc4 Original-Reviewed-on: https://chromium-review.googlesource.com/196162 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 992132ff3431fc7abba10cc8e910e36d4f3a3f7a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5ed091ae7a872fd674ab21f9f80267052fcd24b1 Reviewed-on: http://review.coreboot.org/7864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19AGESA: Remove redundant redeclarationKyösti Mälkki
Change-Id: I9172769c314850b384abbddf0200d5833e2a8b26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7811 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-19AGESA: Only fam14 sets Ontario APU IDsKyösti Mälkki
Change-Id: I3d249a1234599e3820e4ad9b852bbb03a89dd49a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-19cpu/armltd/cortex-a9: Remove stub func dead codeEdward O'Callaghan
Change-Id: Ia8246e2bdf346883072a924d8808f14f48d44bb3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-19intel/i945: Use define for `BSM`Paul Menzel
Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5929 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-19intel/truxton: Add dummy cache-as-ram regionKyösti Mälkki
Board has no chance of working without a cache_as_ram.inc, but without a specified CAR region we also break builds. Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19gigabyte/ga-b75m-d3h: Drop redundant EARLY_CBMEM_INITKyösti Mälkki
It is implied by DYNAMIC_CBMEM. Change-Id: I6859c4950ce568fb76c7604e9e994031a3d94d78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19beaglebone: use new arm bootblock infrastructureAlexander Couzens
8b685398 change config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: Ifac4a18a2e380c3472f51aaa7cc7842b01a2553e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7190 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19arm/ti/am335x: use new arm bootblock infrastructureAlexander Couzens
commit 8b685398 (ARM: Overhaul the ARM Makefile.) changes config flags for cpu and mainboard bootblock initialization. Tested on beaglebone black. Change-Id: I70cbe3abad8443c5dc71c8ba76a35973a5284477 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/7189 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19AMD amdfam10: Drop EXT_CONF_SUPPORTKyösti Mälkki
Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690. Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7809 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19AGESA fam12 fam14: Drop EXT_CONF_SUPPORTKyösti Mälkki
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped from other AGESA families. Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7808 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19AMD binaryPI: Drop EXT_CONF_SUPPORTKyösti Mälkki
Change-Id: I2ec08df2eb8e65bc759de9917894df9d0c8b1995 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19spd_cache debug: Log invalid CRC checksumTobias Diedrich
"SPD has a invalid or zero-valued CRC" is not a very useful message, so show the actual and expected values. Change-Id: I31a1cdacc82240c699627769d490b94f5d378e86 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7393 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-19mainboard: Strip out some dead includesEdward O'Callaghan
Change-Id: I0079fa089ba863c6e447bcee3440a7e0ba0f2372 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7429 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-12-19AMD 00730F01: Change Makefile to use BLOB sizes for packingBruce Griffith
The new AMD PSP and SMU BLOBs currently have fixed sizes in the southbridge Makefile. Future PSP and SMU updates may require more space and thereby cause the make to fail with cryptic error messages. Change the makefile to compute CBFS locations and the corresponding PSP pointer table entry values based on the actual file sizes. Additionally, the FWM directory has expanded to 4096 bytes. The Avalon makefile is modified to zero-pad the FWM directory using the "dd" system command. There is dead code in the makefile to allow hardware validated boot ROMs, but the option is hard-coded to be disabled. Remove the HVB dead code. Change-Id: I4705cede8ed001a71bb4f49598444255c9609d52 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/7726 Reviewed-by: Marshall Dawson <marshall.dawson@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19southbridge/amd/cimx/sbX00/early.c: Update grammar in commentsMartin Roth
Along with the spelling fixes, it was requested that I correct this comment. Updating "LocateImage() take minutes" to "LocateImage() takes minutes" everywhere that comment occurs. Change-Id: I28cd47476cb42ba3e404e064695a7fd97d581834 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7848 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Initialize LPC pads in bootblock for port 80Martin Roth
Port 80h codes were coming out of bootblock and romstage scrambled, or were not coming out at all. Initializing the LPC signal pads as LPC fixes that issue. Change-Id: I16943513f2eb6fe8fa58766aaa82dac182440c34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7802 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
The GPIO_NC1 #define was added to handle GPIOs that are not on func0. This is already handled elsewhere in the GPIO code, so is not needed. - Remove the single GPIO_NC1 from platforms using fsp_baytrail - Revert the GPIO_INPUT_PU_10k #define to remove the _func argument. Update everywhere this macro is called. - Remove GPIO_NC1 Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7849 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
The GPIO_OUT_LOW #define was missing an internal comma in both soc/intel/baytrail and soc/intel/fsp_baytrail. Thanks to Werner Zeh for pointing this out. Change-Id: I2e5507058739e5fdc2c0e43e0380058458870e46 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7801 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-18amd/olivehillplus/romstage.c: remove not useful variable 'halt'WANG Siyuan
The variable 'halt' is not useful and results in a compile error because of: 1b2f2a07 Introduce halt() build error: src/mainboard/amd/olivehillplus/romstage.c: In function 'cache_as_ram_main': src/mainboard/amd/olivehillplus/romstage.c:43:15: error: declaration of 'halt' shadows a global declaration [-Werror=shadow] In file included from src/include/cpu/x86/lapic.h:6:0, from src/mainboard/amd/olivehillplus/romstage.c:29: src/include/halt.h:31:32: error: shadowed declaration is here [-Werror=shadow] cc1: all warnings being treated as errors make: *** [build/mainboard/amd/olivehillplus/romstage.pre.inc] Error 1 Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/7847 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-18i82371eb & qemu: Move to per-device ACPI.Vladimir Serbinenko
This one is special because qemu is really far from anything real but shares some common features. Change-Id: Ia1631611724a074780e1fece50166730b2ee94ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6939 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-18Drop VIA Epia-NStefan Reinauer
ROMCC cleanup. Change-Id: Id72e6fcb89165f28cad8bf3a5b632d3fa094b7dd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7855 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia-M series of boardsStefan Reinauer
ROMCC cleanups Change-Id: Ic4c9d9eb8c7edc506c8a8e8eeeacf759cbaead74 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7854 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop VIA Epia mainboardStefan Reinauer
.. and also drop the northbridge and southbridge used by the board. This is one of the last boards to not use ROMCC for romstage. Let's get rid of it. Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7853 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18Drop Intel E7520 and E7525 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18intel/truxton: Un-romcc-ify boardStefan Reinauer
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7852 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-18AMD Trinity: Update SMU firmware from 10.9 to 10.14Zheng Bao
The first dword in FirmwareTN has been changed from 0xa0009 to 0xa000e. The FirmwareTNHeader is not called by any one in latest PI. It seems to be useless for now. Change-Id: Ic7a20e0bcca8de0b56c7bc5d01e0ce86347bde21 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-12-17chromeos: Add empty functions when CONFIG_CHROMEOS is disabledDuncan Laurie
This allows the chromeos header and functions to be included without needing to guard with #if CONFIG_CHROMEOS. BUG=chrome-os-partner:28234 BRANCH=None TEST=emerge-rambi coreboot Original-Change-Id: I523813dc9521d533242ae2d2bc822eb8b0ffa5e2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196265 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b78ccada9a01f54a60993dfc2c618201d31df9ad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic2f7127966da716e114336c30829a6403d82e180 Reviewed-on: http://review.coreboot.org/7843 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17elog: Fix chromium merge issueMarc Jones
This cleans up a mis-merge in elog.c and puts the following change back: drivers/elog: Unmangle header include out of pre-proc cond commit a3119e5835e4b8fd510d046c56a3bf2bf43a5c0d Change-Id: Iafbbd381efdb103717022d2a3c342da376a9428f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
In order to protect ourselves from the kernel driver not honoring or placing the correct frequency in the backlight register always set one. This code path picks 200Hz as the default if nothing is specified in device tree. It's somewhat arbitrary but that frequency is valid for all the eDP panel specs we've seen being used on baytrail devices. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted in normal mode. Noted register write stuck. Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196821 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Reviewed-on: http://review.coreboot.org/7845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17rambi: align gpu pipea settings with the VBIOSAaron Durbin
In the normal mode case these settings aren't overwritten by the VBIOS because the VBIOS does not run. Therefore, the settings need to align with what the VBIOS programs so that there is a consistent panel power sequencing. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted. Noted settings set by firmware for both dev and normal mode match. Original-Change-Id: Iccf65e2a6bce6859fd7cb0f466d4b44d654523ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196822 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 12999018f2b08df0c3b9cdac1f16e9c4517ea803) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idf1a701ffcb1c990cec2ca1ccca24cc0d26fabbf Reviewed-on: http://review.coreboot.org/7846 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
This ensures that SPI is ready when eventlog code is used. x86 platforms which use eventlog invoke elog_clear() in GSMI and elog_add_event_raw() when deciding the boot path based on ME status. For the SMM case spi_init() is called during the finalize stage in SMM setup. For the boot path case we can call spi_init() at the beginning of BS_DEV_INIT and it will be ready to use when the boot path is determined from the ME status. BUG=none BRANCH=none TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi (Baytrail) with follow-up patch Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1 Original-Reviewed-on: https://chromium-review.googlesource.com/194525 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 173d8f08e867bab8c97a6c733580917f5892a45d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifaed677bbb141377b36bd9910b2b1c3402654aad Reviewed-on: http://review.coreboot.org/7756 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-17chromeos: vboot_loader: Add support for SW_WP_ENABLED flagShawn Nematbakhsh
Set VB_INIT_FLAG_SW_WP_ENABLED according to the status returned by an optional platform / mainboard function vboot_get_sw_write_protect(). BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` and reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: Ifb852d75cc106d10120cfee0a396b0662282051a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c4668fc8a9ab31d9cf876b3d9ad3405756d4d683) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idace325439958f6b490d2e6705d55e95305c4b2a Reviewed-on: http://review.coreboot.org/7750 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: cbmem: Move the call to cbmemc_reinit.Gabe Black
The call was after the call to vboot_verify_firmware and so would only be called when falling back to RO, aka recovery mode. This change moves it to before vboot_verify_firmware so we'll always have the cbmem console. BUG=None TEST=Built and booted on nyan and verified that the cbmem console was the same as the serial output. Built for big and blaze. BRANCH=nyan Original-Change-Id: I02d01110659689b08d32777dae384ac3e01b3b9f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196158 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d3e4a778e4a0f5ade7d633d8ce7e72ef06c44086) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id14a19a78bcb21cb0c4030c2e41195e491f690d5 Reviewed-on: http://review.coreboot.org/7777 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17tegra124: modify panel init sequenceKen Chang
Panel datasheet defines some delay between PWM signal out and backlight enable. This change fixes the current sequence and makes the delays adjustable by dt setting. BRANCH=none BUG=chrome-os-partner:28008 TEST=Verified on Big DVT and Nyan/Norrin panels. Panel works fine with dev mode, and the measurement of power on sequence meets panel requirements. Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196183 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3 Reviewed-on: http://review.coreboot.org/7776 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: enable CLAMP_INPUTSKen Chang
Enable pinmux clamp function to avoid pinmux conflict. For pins which are configured to tristate enabled, the inputs to the controller will be clamped to zero. This can be used to avoid pinmux conflicts since the tristate bit is set to 1 in the power-on-reset pinmux setting. With pinmux clamp enabled, we need to configure all the input pins to tristate disabled. BUG=chrome-os-partner:27091 BRANCH=None TEST=built and booted successfully, display worked fine. Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194060 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0 Reviewed-on: http://review.coreboot.org/7775 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: Add eventlog supportDavid Hendricks
This enables event logging support for Nyan platforms. Right now this doesn't do a whole lot. We can add events in later CLs. BUG=none BRANCH=none TEST=built and booted for Nyan Rev. 1, eventlog gets initialized if necessary and can be printed by "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id77a78f55c8bff9ef0ffc7109c8b03c270e8b6b1 Original-Reviewed-on: https://chromium-review.googlesource.com/191200 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1bb1a00863a63e53379b02f2b466d4d8ae3cef50) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3a5d896d97dfc66ec37114bd3bac3f34e1c22bf7 Reviewed-on: http://review.coreboot.org/7774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-17Revert "elog: Use the RTC driver interface instead of reading CMOS directly."Marc Jones
This reverts commit 474313d1b6556ad8b3e6750a4096b5735cbfc846. This reverted commit was applied out of sequence and there are a number of dependencies that need to be in place prior to adding it. Remove it for now. Change-Id: If80c40867098dee2feff2b9a1d824558f4d7028d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17lib/edid.c: Use 'hh' instead of 'h' length modifier in printkAlexandru Gagniuc
The length modifiers for unsigned char were accidentally changed from 'hh' to 'h' with commit: * 1c8ee21 edid: Change static variables to auto variables. Change-Id: I4b3e63cbcde7635b842894f776373f7946bd0df8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4477 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-17intel/minnowmax: Determine board type from GPIOsMartin Roth
SSUS GPIO 5 reflects the Minnowboard Max SKU: --- GPIO 5 low is a 1GB board --- GPIO 5 high is a 2GB (or 4GB in the future) board. This allows us to determine the board type at runtime and configure the FSP appropriately. Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7797 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-17fsp_baytrail: Add code to read GPIOs in romstageMartin Roth
- Build gpio.c into romstage - Add functions to translate the GPIO # to a pad #, then return the value read from the GPIO. - Add functions to configure the GPIO - Function, Pull up/down, pull strength, Input/Output, and Output level. Change-Id: Ic37dfc9a74a598023bdf797d31087428adec176a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7796 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-17southbridge/amd rs690 & rs780 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7841 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/amd agesa & cimx spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I5d2d4ba098d2a95f7643f000f4b48b3349a8e6cf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7839 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/amd amd81XX, cs553X & sr5650 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7842 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-17southbridge/amd sb600, sb700 & sb900 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: I31333742d9c90cf6d7ae3d2f324880ed53807d7f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7840 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/nvidia: Spelling/comment fixMartin Roth
Change-Id: I4f9b2b8375abe4691f279df649eaf822b87509e5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7731 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/via: Spelling fixesMartin Roth
Change-Id: I7efc441d3da10e48c8c79e4cd51885bb14eebd55 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17southbridge/ricoh: Spelling fixesMartin Roth
Change-Id: I1d000762ed6cc1fa6a274ad6016cf7192eeffea0 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7732 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-17ARM: Use LPAE for Virtual Address TranslationDaisuke Nojiri
This change introduces LPAE for virtual address translation. To enable it, set ARM_LPAE. Boot slows down about 4ms on Tegra124 with LPAE enabled. TEST=Booted nyan with and without LPAE. Built nyan_big and daisy. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I74aa729b6fe6d243f57123dc792302359c661cad Original-Reviewed-on: https://chromium-review.googlesource.com/187862 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 6d8c8b2bbdc70555076081eb3bfaabde7b4a398f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8980375c14758af35f7d5ec5244be963e5462d8a Reviewed-on: http://review.coreboot.org/7749 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17spi_flash: Move (de-)assertion of /CS to single locationDavid Hendricks
This consolidates all calls to spi_claim_bus() and spi_release_bus() to a single location where spi_xfer() is called. This avoids confusing (and potentially redundant) calls that were being done throughout the generic spi_flash.c functions and chip-specific functions. I don't think the current approach could even work since many chip drivers assert /CS once and then issue multiple commands such as page program followed by reading the status register. I suspect the reason we didn't notice it on x86 is because the ICH/PCH handled each individual command correctly (spi_claim_bus() and spi_release_bus() are noops) in spite of the broken code. BUG=none BRANCH=none TEST=tested on nyan and link Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I3257e2f6a2820834f4c9018069f90fcf2bab05f6 Original-Reviewed-on: https://chromium-review.googlesource.com/194510 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit d3394d34fb49e9e252f67371674d5b3aa220bc9e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieb62309b18090d8f974f91a6e448af3d65dd3d1d Reviewed-on: http://review.coreboot.org/7829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17spi_flash: Differentiate between atomic/manual sequencingDavid Hendricks
This adds a wrapper function and a Kconfig variable to differentiate between SPI controllers which use atomic cycle sequencing versus those where the transaction sequence is controlled manually. Currently this boils down to x86 vs. non-x86. Yes, it's hideous. The current API only worked because, for better or worse, x86 platforms have been homogeneous in this regard since they started using SPI as an alternative to FWH for boot flash. Now that we have non-x86 platforms which use general purpose SPI controllers, we should overhaul the entire SPI infrastructure to be more adaptable. BUG=none BRANCH=none TEST=tested on nyan and link Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: If8ccc9400a9d04772a195941a42bc82d5ecc1958 Original-Reviewed-on: https://chromium-review.googlesource.com/195283 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4170c59d06206667755402712083452da9fcd941) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I54e2d3d9f9a0153a56f7a51b80f6ee6d997ad358 Reviewed-on: http://review.coreboot.org/7828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17edid: initialize has_valid_detailed_blocks as 1Vince Hsu
In last clean-up commit, the detailed_blocks parsing has been merged to one for-loop and combining return values in each iteration instead of assignment. As a result, has_valid_detailed_blocks should now be initialized as 1. BRANCH=none BUG=none TEST=Tested AUO 1080p and InnoLux 720p panels on nyan_big Original-Change-Id: Ie4b6e25de63c0e216ae5de9bde20eed1fe3e59a6 Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195803 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 21ac533d17c892c39532c263cc6ec15e4507ed3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I23111efb902c7e5994a4dbdfe77242c13ef5a70e Reviewed-on: http://review.coreboot.org/7835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17edid: Change static variables to auto variables.Hung-Te Lin
To support parsing multiple EDID blobs, the static "decode results" flags should be changed to auto variables inside decode_edid. This is done by packaging static variables into a structure inside decode_edid. We also revised some functions (manufacturer_name, do_checksum) to avoid accessing global variables directly. Extension (and detail block) parsing may need to access and return all parsed context so we pass the whole structure to it. BRANCH=none BUG=none TEST=emerge-nyan coreboot chromeos-bootimage # See EDID parsed correctly on Nyan. Original-Change-Id: Ieca93d446bacf655c145dffdfa6cc6f5dc87ac26 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195372 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ed45909df24c05a0cb8b2ff662fdd2d7a39012f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I17cdfa770181a6eaac9d1050d340c8e052572b4a Reviewed-on: http://review.coreboot.org/7834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17southbridge/sis: Spelling/comment fixesMartin Roth
Change-Id: I6a0f5406fb3bc3e8aa3a1111b1d702f530c9329b Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7733 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-17elog: Use the RTC driver interface instead of reading CMOS directly.Gabe Black
Use the RTC driver interface to find the timestamp for events instead of reading the CMOS based RTC directly on x86 or punting on ARM. This makes timestamps available on both architectures, assuming an RTC driver is available. BUG=None TEST=Built and booted on nyan_big and link and verified that the timestamps in the event log were accurate. BRANCH=nyan Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197798 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8481adde86d836b5f0b019c815bada6d232a4186 Reviewed-on: http://review.coreboot.org/7833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17elog: Isolate some x86-ismsDavid Hendricks
This attempts to isolate/fix some x86-isms: - Translate flash offset to memory-mapped address only on x86. - Guard ACPI-dependent line of code - Use a Kconfig variable for SPI bus when probing the flash rather than assuming the bus is always on bus 0. - Zero-out timestamp on non-x86 until we have a better abstraction. (note: this is based off of some of Gabe's earlier work) BUG=none BRANCH=none TEST=needs testing Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I887576d8bcabe374d8684aa5588f738b36170ef7 Original-Reviewed-on: https://chromium-review.googlesource.com/191203 Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1fc7a75f8c072098e017104788418aeed0705e93) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida4b211cf21ecdde9745d4dbef6a63ffb9fbba8d Reviewed-on: http://review.coreboot.org/7832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17elog: Do not attempt to init SPIDavid Hendricks
This severs a dependency the eventlog code has on initializing chipset/SoC SPI controller. Currently elog_init() calls spi_init() as a catch-all. This worked for x86 since the SPI controller is only used for one thing on existing platforms. As we add eventlogging support to non-x86 platforms we need to consider the more generalized case where the assumptions about how SPI works on x86 are no longer valid. BUG=none BRANCH=none Signed-off-by: David Hendricks <dhendrix@chromium.org> TEST=built and booted on Link, Beltino and Rambi. See below for "mosys eventlog list" output on Link showing boot and suspend/resume events (including lid close/open) added successfully. localhost ~ # mosys eventlog list 0 | 2014-04-14 13:52:44 | Log area cleared | 4096 1 | 2014-04-14 13:52:44 | System boot | 50 2 | 2014-04-14 13:52:44 | EC Event | Power Button 3 | 2014-04-14 13:52:44 | SUS Power Fail 4 | 2014-04-14 13:52:44 | System Reset 5 | 2014-04-14 13:52:44 | ACPI Wake | S5 6 | 2014-04-14 13:53:25 | ACPI Enter | S3 7 | 2014-04-14 13:53:35 | ACPI Wake | S3 8 | 2014-04-14 13:53:35 | Wake Source | RTC Alarm | 0 9 | 2014-04-14 13:53:49 | ACPI Enter | S3 10 | 2014-04-14 13:54:00 | EC Event | Lid Open 11 | 2014-04-14 13:54:00 | ACPI Wake | S3 12 | 2014-04-14 13:54:00 | Wake Source | GPIO | 15 Original-Change-Id: I26e25c0a856f7b8db5ab6b8e7e1acae291d2eadc Original-Reviewed-on: https://chromium-review.googlesource.com/194526 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2971d20b6ebdd9803b05ccbbaeefe1bde1a21af4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia5f2913fd8e4fee6e741e6d1e39d32bb86525cb3 Reviewed-on: http://review.coreboot.org/7831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17tegra124: change PLLD VCO calculation algorithmKen Chang
The current algo sets dc shift clock divider to 5 and PLLD DIVP to 0, this is causing VCO out of the characterized range for some panels. This CL changes the dc shift clock divider to 1 and calculates a proper DIVP to have the VCO inside the characterized range, i.e., 500MHz ~ 1000MHz. BRANCH=none BUG=none TEST=Verify on below panels the pixel clock frequencies are correct. 1. AUO B133XTN01.3 (69.5 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 69.5 695 12/695/0 with: 69.5 139 3/139/2 2. AUO B140HTT01.0 (141 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: VCO (1410000000) out of range. Cannot support. with: 141 282 2/94/1 3. LG LP140WH8 (76.32 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.32 763.2 5/381/0 with: 76.3125 152.625 8/407/2 4. N116BGE-EA2 (76.42 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.40 764 3/191/0 with: 76.375 152.75 12/611/2 Original-Change-Id: Id4b3a4865acde37a97d7346ec88406f5237304eb Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195534 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 1b56566786aa86c14f691fa3858b878f27b6b4de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9de93420e60323f143a42db842febdd3706fe44 Reviewed-on: http://review.coreboot.org/7773 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16spi: Add support for Winbond W25Q32DWDavid Hendricks
Similar to the W25Q64DW, the W25Q32DW has basically the same attributes as the earlier W25Q32 parts but with a different value in the MSB of the ID. BUG=none BRANCH=none TEST=tested on nyan, now SPI flash commands actually work. Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I697768a443c98515d893f9cf8f8b4258ae0f159d Original-Reviewed-on: https://chromium-review.googlesource.com/191205 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 35f03f4f4f21c470d172ce7cce257517b959346d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I73606737835e4f8ea00d2c331ca37957e4abd953 Reviewed-on: http://review.coreboot.org/7755 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16spi: Make idcode debug print more usefulDavid Hendricks
The old print simply said "Got idcode". This makes it actually display what it got. BUG=none BRANCH=none TEST=tested on nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I8f1c8fde6e4ac00b12e74f925b7bcff83d1f69f3 Original-Reviewed-on: https://chromium-review.googlesource.com/191204 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 5f13789be77d038d3c1602037afe29a0351f72ee) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I65d0d51c17b3bda62351532aac1756b630433ea3 Reviewed-on: http://review.coreboot.org/7754 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-16blaze: Change samsung RAMCODE to samsung-2GB-204/samsung-4GB-204Neil Chen
hynix-2GB-204MHz/hynix-4GB-204MHz are not workable with Samsung RAMCODE. To replace them by samsung-2GB-204/samsung-4GB-204 for bring up purpose. BRANCH=none BUG=chrome-os-partner:27682 TEST=emerge-nyan_blaze coreboot builds OK; flash to blaze board and boot to kernel successfully with all the RAMCODE Original-Change-Id: I7c2a96e84e6988dd739a9621ff93edc01703306a Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195396 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> (cherry picked from commit dc028c408be58f036fe125abc2e49e2c0cde0aa8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieeb0250e42fb48c6089bc8dc95550c9b1694d7f8 Reviewed-on: http://review.coreboot.org/7772 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Allow "best" PLLD parameters for unmatched pixel clock.Hung-Te Lin
The pixel clock for some panel (ex: CMN N116BGE-EA2: 76420000) cannot be matched by our PLLD params finding algorithm, after VCO/CF limitations are applied. To support these panels, we want to allow "best matched" params. BRANCH=nyan BUG=none TEST=emerge-nyan_big coreboot chromeos-bootimage; emerge-nyan coreboot chromeos-bootimage; # Successfully brings up display on Nyan_Big EVT2 and Nyan Norrin. Original-Change-Id: If8143c2062abd2f843c07698ea55cab47bf1e41a Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195327 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 8aa66e659e3c60296f05e59b4343496a850ea019) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I623db44de35fecee5539e4d72f93f28b5fa0b59c Reviewed-on: http://review.coreboot.org/7771 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Always enable DC when attaching SOR.Hung-Te Lin
We found that without enabling DC in tegra_dc_sor_enable_dc, kernel would have problem showing the text console before graphics interface is initialized, for example "chromeos factory install shim (text only)" or the "splash screen". BRANCH=none BUG=chrome-os-partner:28082 TEST=emerge-nyan coreboot chromeos-bootimage Boots factory install shim and see text console. Original-Change-Id: I6fce963ceddd125dd52789d2ec843cc2ee05f1f5 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195388 (cherry picked from commit 375a86be9b23650cd96e46b07c7a0b5c10970797) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib75e3ffac9b216c7486845cb8459dd8952d51fe6 Reviewed-on: http://review.coreboot.org/7770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: debug: Add sor registers dump functionJimmy Zhang
Dump all SOR registers for debug purpose. By default, this function is not being built in. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I7f44709b8572b9eac33c2193b92a65bf2b22aa76 Original-Reviewed-on: https://chromium-review.googlesource.com/194738 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Original-Tested-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit d08c0f7c5e8ac094987b09fae96e8133ed9c08c5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1341bbbd0ea6277e5a1b286d6f088f2961070416 Reviewed-on: http://review.coreboot.org/7769 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: clock: Enforce PLL constraints for VCO and CFJulius Werner
This patch adds some documentation to the additional PLL divisor constraints on the intermediary VCO and CF values that we just found out about. PLLC divisors for some oscillators had to be adjusted accordingly. It also adds a new clock_get_pll_input_khz() function to replace clock_get_osc_khz() in cases where you want to factor in the built-in predivider for 38.4 and 48 MHz oscillators. BUG=None TEST=Still boots. Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194474 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599 Reviewed-on: http://review.coreboot.org/7768 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 registerJimmy Zhang
This register needs to be set properly during display init. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display works as well. However, the mode setting needs to be based on either devicetree or EDID. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031 Original-Reviewed-on: https://chromium-review.googlesource.com/194739 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c Reviewed-on: http://review.coreboot.org/7767 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
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