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2015-04-28boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEXAaron Durbin
These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28chromeos: remove VBOOT2_VERIFY_FIRMWARE optionAaron Durbin
There's no need to have the VBOOT2_VERIFY_FIRMWARE distinction because it's the only game in town. Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9958 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28vboot: remove vboot1Aaron Durbin
In preparation for moving to vboot2 for all verified boot paths bring over Kconfig options to the common area from vboot1. Also remove vboot1 directory entirely. Change-Id: Iccc4b570216f834886618f0ba5f2e1dd6c01db4b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9957 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28marvell/bg4cd: merge verstage into bootblockDaisuke Nojiri
If verified boot is enabled, merge verstage into bootblock. This also requires custom bootblock code to actually call into verstage. [pg: modified to match upstream] BUG=chrome-os-partner:32631 BRANCH=ToT TEST=booted on cosmos development board. Change-Id: I53251aac966ee15da24232c23fefa636de8b253b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2b8ada263017b46afa755b5acb759574184dba06 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia0e1236357aa32bf553fb8cc98f3a8d29de17f45 Original-Reviewed-on: https://chromium-review.googlesource.com/229795 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10008 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: Allow merging verstage into bootblockPatrick Georgi
Change-Id: I31cd7f84db8b7176c8854f33421aab5c176cd5ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: Always enable timestampsPatrick Georgi
The vboot2 code requires them. Change-Id: I9afaf9b373297b0eebce9ffd7cc05766dee7d6fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: get rid of global variable that is used locally and only oncePatrick Georgi
Change-Id: Iaf6d6a8857451fb16916aaae97a6fd5c51bc8cc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28vboot2: Build verstage archive, then use that for building the stagePatrick Georgi
This slightly streamlines integrating the vboot2 library and prepares for merging verstage and bootblock on selected devices. Change-Id: I2163d1411d0c0c6bf80bce64796e1b6a5a02b802 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28lib: When used, add timestamp.c to bootblock and verstage, tooPatrick Georgi
Otherwise it won't build. Change-Id: If9e1435b0dc8bfe220b3a257976e928373fbc9a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28arch/arm: Move inclusion of timestamps.c to the right directoryPatrick Georgi
Without this, building with COLLECT_TIMESTAMPS fails. Fixes a mistake during upstreaming in commit 0de8820. Change-Id: Ie56bd38649a821f6b22a1e5dee5f50ef397035fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-28OxPCIe: Fix UART base addressesKyösti Mälkki
The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8780 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28intel SMI handlers: Refactor GPI SMI/SCI routingKyösti Mälkki
Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7967 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-04-28x60,t60,x201,macbook21 : Declare GPIs for ECKyösti Mälkki
For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb) programming to use GPI1 between SCI/SMI modes, while previous programming was for GPI12. Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8656 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-27kbuild: automatically include southbridgesStefan Reinauer
This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9796 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-27arch/arm64: update mmu translation table granule size, logic and macrosJimmy Huang
1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: I9e99a3017033f6870b1735ac8faabb267c7be0a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2f18c4d5d9902f2830db82720c5543af270a7e3c Original-Change-Id: Ia27a414ab7578d70b00c36f9c063983397ba7927 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265603 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/10009 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-27chromeec: ec_mec: Fix misaligned data accessShawn Nematbakhsh
Long auto-increment access cannot be used when our initial address is misaligned or when our terminal address is misaligned on write operations. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on cyan. BRANCH=None Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354 Original-Reviewed-on: https://chromium-review.googlesource.com/266653 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9987 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-27storm: enable CBMEM console dumpVadim Bendebury
This patch enables on storm the recently introduced 'console buffer dump on reboot' capability. BRANCH=none BUG=chromium:475347 TEST=generated storm image with serial console disabled and both rw firmware A and B sections corrupted. Programmed the new image on an SP5 device and rebooted it. Observed the device dump cbmem console buffer to the serial output, terminating with VB2:vb2_fail() Need recovery, reason: 0x3 / 0xa Reboot requested (1008000a) Saving nvdata SF: Detected S25FL128S_256K with page size 10000, total 2000000 and the LED ring started flashing indicating recovery mode. Change-Id: Idb50c86f59f393c783ccbc15de8f5564e2a1b38e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ec88001b152bb9f1d7268b83367131b004816f8 Original-Change-Id: I9345eeb4d375f42fb1e4c617495b63b308ce51d9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265295 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9986 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-27Cygnus: add TrustZone functions and set everything non-secure in bootblockCorneliu Doban
To allow an OS to run in non-secure mode: - Set all peripherals and system components non-secure except SOTP and TZPC. - Set all memory non-secure (ROM, SRAM, DDR, flash). - Enable A9 access to entire M0 address space except M0 ROM. BUG=chrome-os-partner:37533 BRANCH=broadcom-firmware TEST=boot kernel from usb stick Change-Id: I3bbd288863923011ff1413be353ac4b178ffdd07 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6de56bbe73ed8d87ad572da711a193985ee68e3a Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212735 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Ibac7de03a72a98fbd95659d0113833049b4871a5 Original-Reviewed-on: https://chromium-review.googlesource.com/266593 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-27cbmem: add and use a function to dump console bufferVadim Bendebury
The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9984 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-27lib/tlcl: Provide mock implementationYen Lin
It returns TPM_E_NO_DEVICE for all calls. BRANCH=None BUG=None TEST=manual MOCK_TPM=1 emerge-foster coreboot, and coreboot can boot to kernel Change-Id: Id7e79b58fabeac929b874385064b2417db49a708 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a9a91a65af115657e7317754eda931120750c56d Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: I8dcf0db14cf2bc76c67a3bd7f06114e70e08764d Original-Reviewed-on: https://chromium-review.googlesource.com/264946 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9983 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-27vboot: #include "fmap.h" for declarationsAaron Durbin
In the spirit of include what you use actually #include the header necessary for fmap calls. Change-Id: I7acede51d7139234c0520281799dad3a8d33454f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9968 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-27intel/fsp_baytrail: Fix default SMM_TSEG_SIZE valueDavid Imhoff
The value of SMM_TSEG_SIZE was equal to SMM_RESERVED_SIZE. This caused the install_permanent_handler() function to fail. Changed the value to 0x800000, which is already used as default in smm_region_size() in case SMM_TSEG_SIZE is 0. Change-Id: I4ff3568aefd4729a98c1777a2cae2a4715afbc2f Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/9961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-04-27arm64: save/restore cptr_el3 and cpacr_el1 registersJoseph Lo
CPTR_EL3 and CPACR_EL1 are the registers for controlling the trap level and access right of the FPU/SIMD instructions. Need to save/restore them in every power cycle to keep the settings consistent. BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I96fc0e0d2620e72b6ae2ffe4d073c9328047dc01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 73e8cc8f25922e7bc218d24fbf4f7c67e15e3057 Original-Change-Id: I51eed07b1bb8f6eb2715622ec5d5c3f80c3c8bdd Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266073 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/9981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-27arm64: implement CPU power down sequence as per A57/A53/A72 TRMJoseph Lo
Implement the individual core powerdown sequence as per Cortex-A57/A53/A72 TRM. Based-on-the-work-by: Varun Wadekar <vwadekar@nvidia.com> BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I4719fcbe86b35f9b448d274e1732da5fc75346b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b6bdcc12150820dfad28cef3af3d8220847c5d74 Original-Change-Id: I65abab8cda55cfe7a0c424f3175677ed5e3c2a1c Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265827 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9980 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-27arm64: introduce data cache ops by set/way to the level specifiedJoseph Lo
This patchs introduces level specific data cache maintenance operations to cache_helpers.S. It's derived form ARM trusted firmware repository. Please reference here. https://github.com/ARM-software/arm-trusted-firmware/blob/master/ lib/aarch64/cache_helpers.S BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82 Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9979 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-27arm64: perform early setup in secmon tooJoseph Lo
Same as commit fe0eac5f416e "arm64: Allow cpu specific early setup", we need the same in secmon too. BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: I5b1347880306a95f99233db12cb99547bad4aa8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f70fd940ff92eb5b8991cd777c2894b7a9633cf Original-Change-Id: Ifce5a6d636051e7a447d055c8e09ed4e29e091c7 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265825 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/9978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-27arm64: Allow cpu specific early setupFurquan Shaikh
Call arm64_cpu_early_setup to allow cpu-specific initialization to be performed. Also, add support for setting SMPEN bit for cortex a57 within arm64_cpu_early_setup. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully and SMP works for foster Change-Id: Ifa4e6134dbce3ad63046b3dd9b947c3d9134d5e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe0eac5f416efcf9f7b05388a17444205a8352c0 Original-Change-Id: I28a05a20e6adf084cd0bf94bdd0c3b492632107c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262993 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9977 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-24driver/intel/fsp: Correct the fastboot data (MRC data) printing lengthYork Yang
Fastboot data in Intel FSP project is printed by hexdump32() in dword length. So the data length needs to be divided by 4 when printing it. Change-Id: I959d538bd6e60282882dd138045cc730b4bd8159 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/9976 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-23ramstage: don't drop cbmem consoleAaron Durbin
In commit b0d8f5e9 I moved the call to cbmem_initialize() in the CONFIG_EARLY_CBMEM_INIT case to the very beginning of ramstage. However, that caused an issue in the ordering of the cbmem console driver in that it expects cbmemc_init() to be called prior to cbmemc_reinit(). Therefore, ensure console is called as the first thing even if some time is lost w.r.t. timestamp tracking. Change-Id: I42137d28116e0bccb9235f4e3f394d4fd8b84e37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9933 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-23cbmem_console: fix it for x86Aaron Durbin
The Kconfig options pertaining cbmem console in the preram environment no longer make sense with the linker script changes. Remove them and their usage within cbmem_console. Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9851 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-23memlayout: Make sure preram_cbmem_console symbols existPatrick Georgi
This enables its _size variable (a macro) to work even when the console has no location assigned to it in the chip/board's memlayout.ld. Since _size == 0, the code will do the right thing. Change-Id: I6b42ed0c5c3aaa613603680728b61cbdb24c4b61 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9973 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-23src/mainboard/*/*/board_info.txt: Added Release year for boardsMathias Friman
To simplify browsing the "Supported hardware" list, I added Release year for the hardware from asus, asrock, gigabyte, msi, via, tyan, intel, lenovo, apple, jetway and hp. Still several models and manufacturers to add information to. This is more of a proof-of-concept. The "Release year" will be shown in the wiki page. Change-Id: I6bc14ed06ac7c6b3c9f054b49f08cb9b3dc47947 Signed-off-by: Mathias Friman <mathias@workplays.se> Reviewed-on: http://review.coreboot.org/9963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-23AMD Lamar: Add a new AMD FP3 socket mainboardBruce Griffith
Add a new mainboard based on AMD's Family 15 Model 30 processor. TEST: Lamar will boot DOS, Ubuntu 14.10 and Windows 7. Change-Id: I2f73c396247239d54f978846e8958950697d7464 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5968 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22cbmem: switch over to imd-based cbmemAaron Durbin
By design, the imd library still provdes dynamic growth so that feature is consistent. The imd-based cbmem packs small allocations into a larger entry using a tiered imd. The following examples show the reduced fragmentation and reduced memory usage. Before with dynamic cbmem: CBMEM ROOT 0. 023ff000 00001000 aaaabbbb 1. 023fe000 00001000 aaaabbbc 2. 023fd000 00001000 aaaabbbe 3. 023fc000 00001000 aaaacccc 4. 023fa000 00002000 aaaacccd 5. 023f9000 00001000 ROMSTAGE 6. 023f8000 00001000 CONSOLE 7. 023d8000 00020000 COREBOOT 8. 023d6000 00002000 After with tiered imd: IMD ROOT 0. 023ff000 00001000 IMD SMALL 1. 023fe000 00001000 aaaacccc 2. 023fc000 00001060 aaaacccd 3. 023fb000 000007cf CONSOLE 4. 023db000 00020000 COREBOOT 5. 023d9000 00002000 IMD small region: IMD ROOT 0. 023fec00 00000400 aaaabbbb 1. 023febe0 00000020 aaaabbbc 2. 023feba0 00000040 aaaabbbe 3. 023feb20 00000080 ROMSTAGE 4. 023feb00 00000004 Side note: this CL provides a basis for what hoops one needs to jump through when there are not writeable global variables on a particular platform in the early stages. Change-Id: If770246caa64b274819e45a26e100b62b9f8d2db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9169 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22elog: enable by default for CHROMEOSPatrick Georgi
elog breaks the build if ELOG_FLASH_BASE isn't configured - and CHROMEOS isn't enabled, since with Chrome OS builds, it just uses fmap to find out the base. So it makes sense to enable it on all Chrome OS builds - if the code never uses it, the linker will drop it soon enough. Change-Id: I7ee129fadf75caf15fb9bd32b0acf6f7d9d015d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9965 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/storm: indicate start of normal boot on LED ringVadim Bendebury
Instead of switching off the LED ring for the normal boot path, turn it on with the dedicated pattern, indicating that the device firmware has started executing. BRANCH=storm BUG=chrome-os-partner:39044 TEST=program the new firmware on an SP5 device and verify that the new 'normal boot' pattern is displayed in all following scenarios: - power up the device (the pattern shows within the first second) - boot the device to bash prompt and restart. - press the recovery button and reboot the device. Once the LED ring shows the 'recovery button pressed' pattern, release the recovery button. Change-Id: Iedd66d2575ad587af77e35d23efb22a83a92858b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 092358bd17a323d0bd2fec555f43cb587486bbec Original-Change-Id: I24de45326eab83b57bcf16b5598388f81c7d0f00 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265536 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9923 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22i2c/ww_ring: add a pattern for normal bootVadim Bendebury
It became necessary to indicate the beginning of the normal boot process. This patch adds a new pattern, a slow (over 2 seconds) fade in into the 0, 87, 155 color. BRANCH=storm BUG=chrome-os-partner:39044 TEST=tested by the next patch. Change-Id: Idd977688e5aa2cc55fc295072c0766526ae95016 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 577c8bd6f8c69073cfdd7acd4a87e7ae603d48e6 Original-Change-Id: I9aff3f4558e733ff2e47206075533556e400f183 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265535 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9922 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/storm: enable zero page access protection.Deepa Dinamani
BRANCH=storm BUG=chrome-os-partner:24786 TEST=verified mmu.pagetable.list output for Storm: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--00000FFF| | | | | | | | | C:00001000--000FFFFF| A:00:00001000--000FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:00100000--29FFFFFF| A:00:00100000--29FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A000000--2A05FFFF| A:00:2A000000--2A05FFFF| ns| 00| 00001000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:2A060000--2A0FFFFF| A:00:2A060000--2A0FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A100000--3FFFFFFF| A:00:2A100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--59FFFFFF| A:00:40000000--59FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:5A000000--5A1FFFFF| A:00:5A000000--5A1FFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:5A200000--7FFFFFFF| A:00:5A200000--7FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:80000000--FFFFFFFF| | | | | | | | | Change-Id: I08a5094b2da9d67244c94984e2da14399e477b01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f137a589434b09055e6b9d32907e662e6c296502 Original-Change-Id: Ia2deab1cf8f08c4ba5a5b6dbe4c4ebf29c9df480 Original-Signed-off-by: Vikas Das <vdas@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/253801 Original-Tested-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Deepa Dinamani <deepad@codeaurora.org> Reviewed-on: http://review.coreboot.org/9920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: update color definitionsVadim Bendebury
After testing on a final assembly the PD team adjusted the wipeout request and recovery request modes' colors. BRANCH=storm BUG=none TEST=verified new colors while booting an SP5 device in recovery mode Change-Id: I9bd2dac63b99140573533c2cda8eaa9213478ab1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 41c34a619dc0317af67907f18ee844c71a73d623 Original-Change-Id: Iab84710ebdeed35ddd4a8a163bbb6b8ac9cdb799 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262602 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: change colors for different display modesVadim Bendebury
Modify colors as suggested by product review folks. This is not final, to make it easier to identify RGB locations in the hex dumps, express their values in decimal as opposed to hex. BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified new all three color schemes while pressing the recovery button at boot for 20 seconds. Change-Id: I7461acd7004e3d10cba6665a9bfe25ec8aa6f3ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a075824a1954eb5d1b65ce887304924724a6d21 Original-Change-Id: I7f5968e361333572fd1f84aa11b7150194ad902a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261690 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22storm: add config option to clear dev mode state on recoveryVadim Bendebury
Storm and whirlwind devices should leave developer mode as soon as recovery is requested. BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applies observed desired behavior on SP5 Change-Id: I3e8e481f85cd067eff4fe2049b8aa47e09f6d63e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c6dbafc16edb11ec687359b25098ce8a1b055b91 Original-Change-Id: Iac6fa62229556bc7a6960d7f1630d37570ba72c4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261621 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9879 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/storm: enable virtual development mode switchVadim Bendebury
The whirlwind device is using a button instead of the switch to enable dev mode. BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applied it is possible to enable and disable dev mode on Whirlwind and the mode persists over reboots. Change-Id: I6d31c8429ea0515bea2b7d707325d9092487048a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 495bd07e3a1d6c587a5f01efa2801d2c4e7edbe8 Original-Change-Id: I8879833ca13074e8275393c3b98df06d56a5361d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261416 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9875 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: use shorter blinking programVadim Bendebury
The originally loaded blinking program was written to allow gradual change in LED brightness, which required controlling each LED with its own engine. In fact there is no need in gradual brightness changes when the firmware is controlling the ring. This allows to control all LEDs by one engine, making the code simpler and more robust (no need to synchronize the three engines any more). BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified that recovery boot WW ring patterns work as expected. Change-Id: I89d231fb61693f4e834d8d9323ae5a7ddd149525 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19809cf8120df8865da9b5b9e7b8e932334bf4b5 Original-Change-Id: I41038fd976dc9600f223dc0e9c9602331baf68f9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9873 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: stop running programs before loading the new onesVadim Bendebury
The two controllers on the ring are programmed independently, and if the second controller is running the old pattern while the first one was loaded with a new pattern, there is a window of when the two unrelated patterns might interact. To avoid this shut down execution on both controllers before starting downloading the new pattern code. BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified recovery/wipeout LED ring behavior did not change. Change-Id: I163f2983d414fe839208054ae3e9025663a46aeb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3502ca6b119c033855b45388e7b782d35cfdd82b Original-Change-Id: I0f71f94a7e82f6c0e7f98d3aad1f93ece207248f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261200 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9872 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: define display pattern programsVadim Bendebury
Add compiled lp55231 code snippets to allow display certain patterns when booting the device with the recovery button pressed. As soon as the press is detected, the low intensify solid white pattern is enabled. Holding recovery button long enough causes the device transition between the wipeout requested and recovery requested states, with the appropriate changes in the displayed pattern. The patch also includes the source code for the LED controller as well as instructions on how to compile and modify the code to result in different colors, intensities, blink periods and duty cycles. BRANCH=storm BUG=chrome-os-partner:36059 TEST=reboot an SP5 device with the LED ring attached, keep the recovery button pressed, observe the changes in the LED display pattern while the device progresses through the boot sequence. Change-Id: Ic7d45fc7c313b6d21119d4ae6adaeb4f46f7d181 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0fd6a5c0067d705197816629f41640a931d2f7cd Original-Change-Id: Ib5cc5188c2eeedbba128101bf4092a0b9a74e155 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260670 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9870 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: decouple LED display from vbootVadim Bendebury
The patterns displayed on the LED ring while under the coreboot control are not driven by the vboot, but by the board code instead, The four distinct states of the LED display are: - all off - recovery button push detected, waiting for it to be released - wipeout request pending - recovery button was pushed long enough to trigger this request - recovery request pending - recovery button was pushed long enough to trigger this request. BRANCH=storm BUG=chrome-os-partner:36059 TEST=no functional changes Change-Id: I38d9a3028013b902a7a67ccd4eb1c5d533bf071c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bdfff0e646283da6a2faaacf33e0179d2fea221c Original-Change-Id: Ie279151b6060a2888268a2e9a0d4dc22ecaba460 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260649 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9868 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: various driver fixes and improvementsVadim Bendebury
When in development environment, some SP5 devices might not have the LED ring attached. They are still fully functional, but when booting up are generating massive amount of i2c error messages. This patch prevents accesses to non-existing lp55321 devices. When loading the program into the device the vendor recommends 1 ms delay when accessing the program control register. This patch separates these accesses into a function and add a delay after every access. Another fix - advance the program address when loading multipage programs. Set the global variable register 3c, not used by coreboot programs, to a fixed value. This will allow depthcharge to avoid re-initializing the controller when not necessary. BRANCH=storm BUG=chrome-os-partner:36059 TEST=booted firmware on an SP5 with no LED ring attached, no excessive error messages are generated, saw the default pattern displayed when the recovery button is pressed during reset. Change-Id: I6a2a27968684c40dae15317540a16405b1419e30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e0b4c84aca27460db594da1faf627ddee56f399 Original-Change-Id: I10f1f53cefb866d11ecf76ea48f74131d8b0ce77 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260648 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/storm: support factory reset (wipeout) requestVadim Bendebury
The recovery switch on storm is overloaded: it needs to be pressed for a certain duration at startup to signal different requests: - keeping it pressed for 8 to 16 seconds after startup signals the need for factory reset (wipeout); - keeping it pressed for longer than 16 seconds signals the need for Chrome OS recovery. This patch adds a function to report the wipeout request status and enables the new feature on Storm. BRANCH=storm BUG=chrome-os-partner:37219 TEST=verified that keeping the recovery button pressed between 8 and 16 seconds at startup results in the wipeout request generated (crossystem 'wipeout_request' returns 1). Keeping the button pressed for more than 16 seconds triggers recovery mode. Change-Id: I17131593e12833866a22837271feb0e6989e6750 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c503ec13c2b096d4a21fb299c0dd0396f1d01e9 Original-Change-Id: Ic3678217906e56307d47378fa8a6defeb314084e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259844 Reviewed-on: http://review.coreboot.org/9863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22google/storm: use whirlwind LED ring on SP5 boardsVadim Bendebury
The latest whirlwind requirements call for the need to indicate different device states while it is still in coreboot (it could be waiting for recovery or for factory reset trigger). Initialize the LED ring when running on the SP5 hardware (which is the first proper Whirlwind device). BRANCH=storm BUG=chrome-os-partner:36059 TEST=when the device starts the LED ring gets shut down Change-Id: I9dd0bca4849a2a8500322c84c7351aeef00d862e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24e4da56d4c43d03f235d0cfd5995ef235e6a2c5 Original-Change-Id: Ica37301aa27f35897d2bf467ae319fb5e68adc1d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258271 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9859 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c: add support for ww_ringVadim Bendebury
This is a copy of the depthcharge ww ring driver implementation ported into coreboot. The main differences are: - direct use of the i2c driver instead of using the callback driver description - no dynamic memory allocation for the controller structures BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applied the LED ring gets initialized to the default pattern at coreboot start. Change-Id: I6902c8b76fc173ad2ec28b8cc94695e892df338a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eda24b78f8aff311dd6296d458bdfecf26c3d65a Original-Change-Id: I5660dc3f255aab8fbe3a87041c72916a645c193b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/257730 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22mainboards: Add CHROMEOS_VBNV_* where appropriatePatrick Georgi
For boards with MAINBOARD_HAS_CHROMEOS, we should also state what kind of storage is available for vboot's non-volatile data. The flags are taken from the chromium repository and have no effect with CHROMEOS disabled. Change-Id: I1747ad26c8c7f6d4076740ec2800dbd52c5d6b3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22intel/broadwell: guard CHROMEOS support betterPatrick Georgi
Since CHROMEOS_VBNV_* are selected by mainboards, they may be active without CHROMEOS being selected. In this case, they should be a no-op. Change-Id: I3b84e2a919ffaa809d713e72e5e4df7a7575e6b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22coreboot: common stage cacheAaron Durbin
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22coreboot: tiered imdAaron Durbin
A tiered imd allows for both small and large allocations. The small allocations are packed into a large region. Utilizing a tiered imd reduces internal fragmentation within the imd. Change-Id: I0bcd6473aacbc714844815b24d77cb5c542abdd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8623 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22coreboot: add imd libraryAaron Durbin
The imd (internal memory database) library provides a way to track memory regions by assigning ids to each region. The implementation is a direct descendant of dynamic cbmem. The intent is to replace the existing mechanisms which do similar things: dynamic cbmem, stage cache, etc. Differences between dynamic cbmem and imd: - All structures/objects are relative to one another. There are no absolute pointers serialized to memory. - Allow limiting the size of the idm. i.e. provide a maximum memory usage. - Allow setting the size of the root structure which allows control of the number of allocations to track. Change-Id: Id7438cff80d396a594d6a7330d09b45bb4fedf2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8621 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22chromeos: fix some compilation issuesAaron Durbin
This fixes some compilation issues observed with CONFIG_CHROMEOS. Nothing within the vbootX subdirectories is functional yet, but a partial compilation within the chromeos direction works now. Notable fixes: duplicate definitions and missing prototypes. Change-Id: I53c7b6dcf06b8bcf41a8555094b48968c0740026 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9936 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22chromeos: make functions visible with CONFIG_CHROMEOSPatrick Georgi
They were keyed to VBOOT_VERIFY_FIRMWARE which made them invisible under some circumstances. Change-Id: I61c56b4d245351fae0ec14f80bcd17ba93184651 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9956 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22elog: use CONFIG_RTCPatrick Georgi
When RTC is not selected, return all 0. Change-Id: I892a9489fc1d82fb8e61cf02666f797dc6412e05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22rtc: add config flag to denote rtc API availabilityPatrick Georgi
RTC drivers now select RTC, so that code which depends on them can implement fallback behavior for systems that lack the hardware or driver. Change-Id: I0f5a15d643b0c45c511f1151a98e071b4155fb5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22chromeos: Drop {developer,recovery}_mode_enabledPatrick Georgi
They were already moved to src/lib/bootmode.c in commit 5687fc9 Declare recovery and developer modes outside ChromeOS Change-Id: Ia27a0c79baa364ce3779a8a699e9246d26d02ecb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22nvidia/tegra132: Add spi_crop_chunk()Patrick Georgi
Missed during upstreaming Change-Id: Ifef4bb8a097a71244bdb648840cd64a812673107 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9950 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22google/*: Add MAINBOARD_HAS_CHROMEOS where appropriatePatrick Georgi
Some recently upstreamed boards are missing this flag Change-Id: I89d73970f23eed6ea127e620c38f9687b2f5b048 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9949 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22vboot2: CFLAGS_* doesn't contain preprocessor flags anymorePatrick Georgi
The preprocessor flags that are manipulated in that line are managed exclusively in CPPFLAGS since commit 58f73a69. Change-Id: I2263401a292b4f7435659b24cf4f695a927015ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9948 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22qemu-armv7: fix cbfs media implementationAaron Durbin
When using qemu-armv7 to load coreboot.rom with the -kernel flag the rom is offset by 0x10000. Therefore only allow mappings within 0x10000 and 0x10000 + CONFIG_ROM_SIZE. TEST= QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 \ -m 1024M -nographic \ -kernel coreboot-builds/emulation_qemu-armv7/coreboot.rom Change-Id: Ifec5761a7d54685f664c54efaa31949b8cc94bad Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9935 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22coreboot: add a place to choose romstage loaderAaron Durbin
Instead of always loading romstage from cbfs provide a way, similar to ramstage and payload, for other program loaders to intervene. For now, only the cbfs loader is consulted. TEST=Booted to end of ramstage on qemu-armv7 Change-Id: I87c3e2e566d7a0723e775aa427de58af745ecdd5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9934 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22kontron/986lcd-m: update vendor URLPatrick Georgi
Change-Id: Ia43291d0d41e565f2442b625387f3ffde9a98d32 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9947 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22kontron/986lcd-m: Add release yearPatrick Georgi
Change-Id: Ie49e235b81ca0cd7aff05ceed522d9df1d5403b0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9946 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22vboot: route all resets through a single functionVadim Bendebury
It is necessary to trigger console buffer contents dump on reset. Let's make sure all vboot resets are routed through the same function. BRANCH=none BUG=chromium:475347 TEST=built and booted storm Change-Id: I0d8580fb65417ba4b06dfae763dd6455afc8fc26 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9788e2043cb1bd5df7e30574f7df4de4f25caa0d Original-Change-Id: Iafca416700c51a0546249438ca583a415a1ca944 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265292 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9931 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Enable DDR auto self-refreshIcarus Chau
Enable auto entry and auto exit self-refresh. Configure entry idle time to 16x long count sequences. Where a long count sequence is 1024 cycles. The idle entry configuration is based on 32x of the DLL lock time (512 cycles). A conservative setting to help minimize self-refresh enter/exit thrashing. BUG=chrome-os-partner:36456 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR, print on console: sdram initialization is completed. test ddr start from 0x60000000 to 0x80000000 ... test ddr end: fail=0 Translation table is @ 02004000 Mapping address range [0x00000000:0x00000000) as uncached Change-Id: Ibad220429fd52ead2933db03bec1a555f9385e53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3768f82ca268fb854f8c4753916518a1efdf887d Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212125 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Change-Id: Icac1e12745d048b32e1804a546f6b49c8b5953c0 Original-Reviewed-on: https://chromium-review.googlesource.com/265862 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add specific controller initialization to corebootCorneliu Doban
BUG=chrome-os-partner:37533,chrome-os-partner:35814 BRANCH=broadcom-firmware TEST=bootblock initialize Cygnus HW successfully Change-Id: I93b97d7b26f6bacd8fab3d6bc52ec52e92e91a43 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8679570c6607ed6964f46df618fe8d0d22fcb2c0 Original-Reviewed-on: https://chrome-internal-review.googlesource.com/211695 Original-Tested-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Commit-Queue: Corneliu Doban <cdoban@broadcom.com> Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com> Original-Change-Id: I62d354bce71aba8d5074f5385616a1265bd604df Original-Reviewed-on: https://chromium-review.googlesource.com/265861 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9929 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_rialto: support the developer key GPIOJonathan Dixon
Currently (EVT) this is a pullup resistor on the board (i.e. always in dev mode). Future builds it will be pull down and require servo or HW modification to control. Either way, this change means the FW should acknowledge it. BUG=chrome-os-partner:38663 TEST=Manually verified that servo devmode switch toggles this GPIO. requires FW signing to verify GPIO is observed and dev mode active. BRANCH=none Change-Id: Ib05216992abc5f6175fe7395471bd379f185b61f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 702c8d222a3d19d6b8db89d122dcdf594c85da99 Original-Change-Id: I1d0f31819b9f7a1ab63deac52bcaf0b996499b0c Original-Reviewed-on: https://chromium-review.googlesource.com/263529 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Jonathan Dixon <joth@chromium.org> Original-Commit-Queue: Jonathan Dixon <joth@chromium.org> Reviewed-on: http://review.coreboot.org/9928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22armv8/secmon: Disable and Enable GIC in PSCI pathFurquan Shaikh
Disable and enable GIC before switching off a CPU and after bringing it up back respectively. BUG=None BRANCH=None TEST=Compiles successfully and psci commands work for ryu. Change-Id: Ib43af60e994e3d072e897a59595775d0b2dcef83 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5271d731f0a569583c2b32ef6726dadbfa846d3 Original-Change-Id: I672945fcb0ff416008a1aad5ed625cfa91bb9cbd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265623 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9926 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-22t132: Add gic.c to secmonFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully for ryu. Change-Id: Iaff771cdd1c8b6a7447e1e86aa35ea3ed40b17ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2856d3d4f4ab4e56259d36769d9cbb0ec9642951 Original-Change-Id: I702d7c6fa70b1af02c16b874f9de22c6b04a9100 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265624 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9927 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22armv8/secmon: Correct PSCI function idsFurquan Shaikh
PSCI_CPU_OFF is SMC32 call, there is not SMC64 version. Register SMC32 and SMC64 types of PSCI calls. BUG=None BRANCH=None TEST=Compiles successfully and CPU off works fine with PSCI command. Change-Id: I8df2eabfff52924625426b3607720c5219d38b58 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9228c07f9d9a4dd6325afb1f64b41b9b8711b146 Original-Change-Id: I2f387291893c1acf40bb6aa26f3d2ee8d5d843ea Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265622 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9925 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22armv8/secmon: Correct names for SMC macrosFurquan Shaikh
We support SMC32 calls from AARCH64, however we do not support SMC32 calls from AARCH32. Reflect this policy in the code by using appropriate names for exception type check in SMC handler. BUG=None BRANCH=None TEST=Compiles successfully and able to turn CPU1 on and off using psci commands. Change-Id: Ifc3c9e2fe0c4e6e395f2647769a2d07f5f41f57f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbaf712c2c45273a9eb0b0808a0d4d0630023fdd Original-Change-Id: I133b2c0bbc4968401a028382532bd051d6298802 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265621 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: save and restore cntfrq for secondary cpusJimmy Huang
CNTFRQ_EL0 can only be set in highest implemented exception level. Save and restore CNTFRQ_EL0 for secondary cpus in coreboot. This patch fix the error below: SANITY CHECK: Unexpected variation in cntfrq. Boot CPU: 0x00000000c65d40, CPU1: 0x00000000000000 BRANCH=none BUG=none TEST=boot to kernel on oak board and check secondary cpu's cntfrq. confirmed cpu1's cntfrq is same as boot cpu's. Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c Original-Reviewed-on: https://chromium-review.googlesource.com/264914 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot: add mocked secdataDaisuke Nojiri
This patch allows a board without a secdata storage (typically TPM) to pass the verification stage if recovery path is taken. It's useful for bringup when the actual board is not ready. BUG=none BRANCH=none TEST=booted the kernel from a usb stick on a cygnus reference board Change-Id: I5ab97d1198057d102a1708338d71c606fe106c75 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5d45acee31fd5b7bfe7444f12e3622bae49fc329 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212418 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Iddd9af19a2b6428704254af0c17b642e7a976fb8 Original-Reviewed-on: https://chromium-review.googlesource.com/265046 Reviewed-on: http://review.coreboot.org/9919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add usb phy driverDaisuke Nojiri
The code originates from https://github.com/Broadcom/cygnus-linux/commit/d0752a61273decb16db0fe8d09291f9cc326ed24. BUG=chrome-os-partner:37439 BRANCH=purin TEST=booted kernel from a usb stick on the ref board Change-Id: I51ecf4e1d6890e4286402c26721f4d063ab04711 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fac506e758cb63a947bbdcfbddf9b8edecf7cd2f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/202386 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I027affea293af8744c997a2ed3dec741977bd328 Original-Reviewed-on: https://chromium-review.googlesource.com/264560 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: DDR reads return to controller with no bubblesIonela Voinescu
When the PHY is compiled to run in HDR(half data rate), then either NOBUB or FXDAT must be set to 1 in the DDR system general configuration register. NOBUB specifies that reads should be returned to the controller with no bubbles and this is felt preferable to the fixed latency option (FXDAT). Both of them inrease read latency. BRANCH=none BUG=chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly Change-Id: Iee530ba5bb0acc889fba447dc2ee5cb965ba6926 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7944b4af45d9504098f8b4af44d0f5abafea42c Original-Change-Id: I9ced76bd670fc4efa7441d57e15f97871b046ae9 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264341 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9917 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: DDR row/bank/column mappingIonela Voinescu
The DRAM configuration register, apart from holding the device density and width also has a rudimentary address mapping scheme. Currently this is set to the default Bank/Row/Column. This means that the memory is segmented into 8 chunks, each with a page detector. If all the activity is in one section of memory then the other 7 page detectors could be idle. Changing this to Row/Bank/Column would concatenate the page detectors meaning that all 8 could be used by a single initiator. This may not gain anything in a synthetic bandwidth test but could yield extra performance in a real world application or benchmark. BRANCH=none BUG=chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly; all access to DDR works properly in Coreboot ramstage, Depthcharge and Linux; no performance tests were ran so far. Change-Id: I22d86bf3b679ed63884d7436d9d7bbaf1726f640 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e852ed42afcdc2062a0037144bab723227cb1f1f Original-Change-Id: If90b0cf5ce86db5e3d6d362873d22d4269e3a49f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264340 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9916 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: add arm64_arch_timer_init functionJoseph Lo
Add arm64_arch_timer_init function which should be called per CPU for setting up the cntfrq register of arch timer. During the Linux kernel bring up time, it will check the cntfrq register per CPU and should be the same with the boot CPU. BRANCH=none BUG=none TEST=bring up 4 cores in Linux kernel without warning message of cntfrq register value Change-Id: I9cb33a54c2c8f9115bbe545a2338ca8e249b8db6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 253cd3c68bb4513ae2033c12c2f070ee391e5a13 Original-Change-Id: I71068dbdd00a719145410ef6ec466f001ae837ad Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264244 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9915 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add secimage and sign bootblockDaisuke Nojiri
secimage is a tool which adds a header and signature to the binary first loaded by the soc. ARM core frequency is set to 1 Ghz. BUG=chrome-os-partner:36421 BRANCH=broadcom-firmware TEST=booted b0 board Change-Id: Ia08600d45c47ee4f08d253980036916e44b0044a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36284d1b242c26b0b5aac2894f7ed1790da1ef15 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/197155 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Iaddd24006b368c8f37e075cb51e151e985029f3b Original-Reviewed-on: https://chromium-review.googlesource.com/264417 Reviewed-on: http://review.coreboot.org/9914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22nvidia/tegra*: check bus number for i2c driver APIsYen Lin
BRANCH=None BUG=None TEST=emerge-foster coreboot Change-Id: I383d2b5f269ed348065a9f270f80514a2ff45742 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fba6973c304e1612a9869c2e78a08650b6e5fe66 Original-Change-Id: I6d5d0098db8dbfb21529bf112a04b97779a0f381 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264027 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arch/armv7: Add API to disable MMU pages.Deepa Dinamani
Disables 4K regions in the MMU table. Assumes that the region is already accounted for by the first level page table entry. BRANCH=storm BUG=chrome-os-partner:24786 TEST=verified mmu.pagetable.list output for Storm: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--00000FFF| | | | | | | | | C:00001000--000FFFFF| A:00:00001000--000FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:00100000--29FFFFFF| A:00:00100000--29FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A000000--2A05FFFF| A:00:2A000000--2A05FFFF| ns| 00| 00001000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:2A060000--2A0FFFFF| A:00:2A060000--2A0FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A100000--3FFFFFFF| A:00:2A100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--59FFFFFF| A:00:40000000--59FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:5A000000--5A1FFFFF| A:00:5A000000--5A1FFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:5A200000--7FFFFFFF| A:00:5A200000--7FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:80000000--FFFFFFFF| | | | | | | | | Change-Id: Ib603da91966cc4c70ea9d5fee04f1e9890d0bb93 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67db80e6476d8ed35f0a9d1e0d3ca03612b9d9be Original-Change-Id: I6b149c7edbd975231b783cc53ddb63cf2e94052c Original-Signed-off-by: Vikas Das <vdas@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/253800 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Deepa Dinamani <deepad@codeaurora.org> Original-Commit-Queue: Deepa Dinamani <deepad@codeaurora.org> Reviewed-on: http://review.coreboot.org/9912 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: Fix operator precedence error in LPDDR initJulius Werner
Upstream coreboot regularly runs Coverity over the code base. Turns out that's a good idea since it's really easy to screw yourself over with a missing parenthesis and some unfortunately deceptive line breaking. This patch fixes a bug in LPDDR3 initialization due to an incorrect operator precedence assumption ( ?: does not bind stronger than | ). In effect, instead of setting MR11[1:0] to 0b11 or 0b00 based on ODT, we're unconditionally setting MR0[1:0] to 0b11. Thankfully, MR0[1:0] seems to contain read-only bits so this might have not been a problem when ODT is off (which is currently true for all LPDDR boards). Also adding a redundant LPDDR_OP() around the 0 to make the intent clearer and changing 3 and 0 to 0x3 and 0x0 to make it more obvious that these are bit masks (right?). BRANCH=veyron BUG=None TEST=Running reboot loop on a Minnie, looks good so far... Change-Id: I06464aaa57e693b1973846a5771162244f7a1c57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan Original-Commit-Id: 5bd9eba39fb7b0f940fead963bbc1878b031b2cb Original-Change-Id: I701ce059472078b5de09a45dd31f54b65a51e641 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/264135 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jinkun Hong <jinkun.hong@rock-chips.com> Original-Tested-by: Jinkun Hong <jinkun.hong@rock-chips.com> Reviewed-on: http://review.coreboot.org/9911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Add variant MEC IOShawn Nematbakhsh
MEC cannot access memmap-range data directly though LPC and instead must access through its EMI unit. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on glower. BRANCH=None Change-Id: If98d425014a894ddeafad4268f92af5860878522 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ed3c50ab97ca1e172d5cdc00f4cd8e069e565c Original-Change-Id: I32b897836d28ef4f3b3aa5f81b9023f2ceb629c8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263611 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Read / write IO ports through common functionsShawn Nematbakhsh
Rather than calling inb + outb directly, access the ports through common functions. This is in preparation for alternative access modes required by certain new embedded controllers. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Verify system boots cleanly in normal mode. BRANCH=None Change-Id: I98783ff67a37d970019683bb589825bc5d68c033 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25afa3f95183d8cf2e9a35272c77e92fbc6ee030 Original-Change-Id: Ic9d8f7f5c5d392212e39db28ebceea461d46f796 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263571 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Implement I2C driverAnatol Pomazau
BUG=chrome-os-partner:35810 BRANCH=purin TEST=Enable I2C1, reset devboard codec, read a register. Here is the code that demonstrates how I2C works: i2c_init(1, 100*KHz); mdelay(50); int rc = i2c_writeb(1, 0x18, 1, 0x80); // reset codec printk(BIOS_INFO, "I2C reset rc=%d\n", rc); mdelay(50); uint8_t data = 0; rc = i2c_readb(1, 0x18, 43, &data); printk(BIOS_INFO, "I2C read rc=%d data=%x\n", rc, data); // data == 0x80 Change-Id: I0d202f8b0375b5ccd9f71b23fb0cadd5a70ae779 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6bbe9afe3dccd104f39c2c286d3765a28ea20141 Original-Signed-off-by: Anatol Pomazau <anatol@google.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/195706 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Commit-Queue: Anatol Pomazau <anatol@google.com> Original-Tested-by: Anatol Pomazau <anatol@google.com> Original-Change-Id: I178acef9de18fa854983294edcd2c05886795e2a Original-Reviewed-on: https://chromium-review.googlesource.com/263496 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9908 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Enable gpio on romstageIcarus Chau
BUG=chrome-os-partner:35936 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_GPIO_TEST, print on console: Start gpio test... [gpio_crmu] gpio:0 set input [gpio_crmu] gpio:0 set pullup:0 GPIO get 170=0 gpio request enable pin=64 offset=0x1c .... GPIO set 69=1 [gpio_asiu] gpio:45 set, value:0 GPIO set 69=0 Gpio test completed... Additional test: Measure on GPIO 69 to confirm the voltage change. Apply voltage on AON_GPIO0 to check reading. Change-Id: I634cffccc7f0fa198317a92e3f1670ae6828892e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4784e5d88b9f7acb70bd6f6b12b1096f092f34b8 Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/204537 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Ia4f833be80d7844c2d014c9ffcf587d385e7766c Original-Reviewed-on: https://chromium-review.googlesource.com/263495 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22switch mainboards over to use BOARD_ID_AUTOStefan Reinauer
This patch switches the mainboards with board id straps to use BOARD_ID_AUTO instead of BOARD_ID_SUPPORT. On urara, which does not have those straps, the option is removed. (And re-added for urara derivatives through setting the config option BOARD_ID_MANUAL BRANCH=none BUG=chrome-os-partner:37593 TEST=emerg-nyan_big coreboot, emerge-urara coreboot, emerge-buranku coreboot Change-Id: I5ac4024c6f1f9b9d7a5179d88722c69b23b82bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 22a470698f9c9ed275aa8150a5bb8d8cf368b050 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Change-Id: I48c291ad6f255a28c833bebc2638bfafa2782e74 Original-Reviewed-on: https://chromium-review.googlesource.com/262935 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9906 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22build system: add manual board id supportStefan Reinauer
This patch adds manual board id support to coreboot and selects manual board ids vs automatic (ie strap based) where appropriate in the mainboards. CQ-DEPEND=CL:262935 BRANCH=none BUG=chrome-os-partner:37593 TEST=emerge-urara coreboot, see no board_id file emerge-buranku coreboot, see board_id file Change-Id: Ia04e5498a01f35c5418698ecaf3197f56415e789 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3bdb1fa092005be24de9fc68998053982648da85 Original-Change-Id: I4f0820233a485bf92598a739b81be2076d4e6ae7 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262745 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22device: Add class and subclass name supportLee Leahy
Add support to display class and subclass names for PCI devices. BRANCH=none BUG=None TEST=Build and run on strago/cyan. Change-Id: I5136fae45b8a1cd02541f233d29a246cdfcd8331 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7c9b0d7201b09a06ea32f0db84187d15f767c80 Original-Change-Id: Ibf2ee89dd84040ca6ab0e52857a69f7ed0c28f37 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263342 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9901 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22Kconfig: Don't select GENERIC_GPIO_LIB in BOARD_ID_SUPPORTStefan Reinauer
The code guarded by BOARD_ID_SUPPORT does not use this library. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BRANCH=none BUG=none TEST=emerge-storm coreboot succeeds in building an image. Change-Id: If8c5c326265441f0c10999e3882706432139fd89 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f49b89e0b03f482a30dc652e5956494fb994cc70 Original-Change-Id: Ie2cd2cd049fdb20fa5cc368bee08babd3f7a551c Original-Reviewed-on: https://chromium-review.googlesource.com/262744 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22soc: select generic gpio lib on (almost) all non-x86 SOCsStefan Reinauer
BOARD_ID functionality is not what requires the GPIO lib, but it is the mainboard specific implementations that do. The option essentially says whether the SoC provides <soc/gpio.h> (with the interface required by the common GPIO code). Right now, x86 and Samsung's Exynos SOCs don't have support for this interface. So this should be selected by the SOC, not by BOARD_ID_SUPPORT. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none BRANCH=none TEST=emerge-storm coreboot still successfully compiled an image Change-Id: I0ce2bd7ce023f22791d31a6245833b61135504b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0dd4dea521372194eedf11b077d95fd3b15ad9f7 Original-Change-Id: I3dea6c2fb42a23fcb9d384c3bbfa7fc8e217be2d Original-Reviewed-on: https://chromium-review.googlesource.com/262743 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: Correct shareability option for normal memoryFurquan Shaikh
In order to allow proper working of caches, set the correct shareability option for normal memory. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully for foster and SMP works. Change-Id: I5462cb0a2ff94a854f71f58709d7b2e8297ccc44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e092916780716ac80c3608c1bd8ca2901fbb3bd1 Original-Change-Id: Idd3c096a004d76a8fd75df2a884fcb97130d0006 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/urara: retrieve network device information from VPDVadim Bendebury
Invoke the function which copies MAC addresses from VPD into the coreboot table and calibration data into CBMEM. BRANCH=none BUG=chrome-os-partner:36584 TEST=with the rest of the patches applied observed that the MAC addresses from VPD get copied into the appropriate kernel device tree nodes. Change-Id: I68e2b73520853ef2d3249ca12ee87669fd01f442 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f935098c50e2df345748d3b71cee2152acd422 Original-Change-Id: I6e1483d33480d13380ade2dddae6c92fd3f1f881 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262844 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: process WiFi MACs along with ethernet MACsVadim Bendebury
coreboot is expected to read all MAC addresses from the VPD and put them in the coreboot table entry, depthcharge is expected to associate different MAC addresses with different kernel device tree nodes. This patch adds processing of wifi_macX keys. The order of MAC addresses in the coreboot table is such that the wifi_macX entries follow ethrnet_macX entries, ordered by X. BRANCH=none BUG=chrome-os-partner:36584 TEST=with the rest patches applied verified the contents of the kernel device tree on an urara board. Change-Id: I6523e168d2fea201a4956bc2a2d605b07ddac452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36c12ee1d3ce9d2797902f0e098651067c2283ed Original-Change-Id: Ib87e4815243f34ab258325839cbc12d16120bf89 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262843 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: decode calibration data into binaryVadim Bendebury
The preferred way of communicating WiFi calibration data to the kernel is binary blob. But this data is stored in the VPD, and must be in ASCII, so it is encoded using base64. With the recent addition of the bas64 decoder it is possible to convert the VPD representation to the form preferred by the kernel. BRANCH=none BUG=chromium:450169 TEST=with the rest of the patches applied verified that on both storm and urara the device tree contains the required binary data. Change-Id: I89da94bb425767eedc5e2d576e507663afad65ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c2ae38ded24394e0640b5d077e2231cf956397c5 Original-Change-Id: If8a7d0883ea8bb21a13bf203b25ee9f8a08903a9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262842 Reviewed-on: http://review.coreboot.org/9895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: increase RAM CBFS cache sizeVadim Bendebury
CBFS cache use is very close to the limit, does not allow to read much more from CBFS. BRANCH=none BUG=chrome-os-partner:36586 TEST=the upcoming patches do not fail due to the lack of room in CBFS cache any more Change-Id: I8e784891e59ca284b3bd82557c2114a2f450d8a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c94d55c8042db81c1eb0c10d5f24883e00cdc19a Original-Change-Id: Ic09dbd5b4a0e165ccef396ff8a9e21b12c49b705 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263268 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>