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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237421399
TEST=Verify the build for gimble board
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie66c9679c985215ad7f1a5ae76560b839ea95702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65474
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For ipq806x this fixes two resources getting declared
with same index. The latter previously overwrote former.
Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ifb47e0d1d1b9c01c1332af4135f5578160c491a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in
ramstage to fix build error.
BRANCH=firmware-brya-14505.B
Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I86423c45ca33a79d3d8cf8e4ca4737da94a4aa4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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In the CSE FW update flow, update is triggered when there is a mismatch
in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed,
compared and then the CSE RW region is updated. However, in the case of
compressed blobs, we cannot directly map the blobs from SPI. It needs to
be decompressed before the hash is calculated and compared. Add a check
for compressed blobs and figure out whether it needs to be directly
mapped from SPI or loaded into memory allocated for file in CBMEM, with
the provided CBMEM ID.
BRANCH=firmware-brya-14505.B
Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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CSE FW sync is currently performed in romstage, when uncompressed ME_RW
blobs are used. When compressed blobs are used, this has to be done in
post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be
performed, in romstage or in ramstage.
BRANCH=firmware-brya-14505.B
Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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cbfs_unverified_area_cbmem_alloc() expects a tag id to allocate space
to decompress ME_RW blobs within the CBMEM area, add a tag id for it.
BRANCH=firmware-brya-14505.B
Change-Id: I32f44496d389e3a7e4f2573ee4e46a145f7cd927
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kingler and Krabby's rev 0 boards both have Cr50 instead of Ti50. In
order to support them with the new firmware where TPM_GOOGLE_TI50 is
selected, use the board rev to determine the EC-is-trusted logic.
BUG=b:237355198
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I7797eafaa7a35355d241c4ea425a4716a35a7817
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This change copies ec_commands.h directly from the ChromiumOS EC repo,
with the exception of changing the copyright header to SDPX format.
Update to commit SHA1 2cbf6fbf (ec_commands: Drop VBNV read/write
support).
BUG=b:178689388
TEST=none
BRANCH=none
Change-Id: I74fa8b1171ca109dee163a7657659cdac1687450
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65469
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:63368 added a workaround of driving EN_PP3300_WLAN_X low in bootblock
to prevent a kernel crash on warm reboot. The crash has been fixed in
the kernel, so remove the workaround.
Kernel fix:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3463465/
BUG=b:225261075
TEST=Wifi works on nereid, warm reboot doesn't crash the kernel
Change-Id: Idb5547e65ea934954326fcc740b14a83c939432e
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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It seems fixup or adjustment addition for relocation type
EFI_IMAGE_REL_BASED_DIR64 is missing in the fsp rebasing code. The
patch address the miss. Without extending the fixup for the relocation
type, build system throws warnings during the rebasing of FSP-M and
FSP-S blobs which are built with 64bit.
Portion of build output containing warning with debug enabled cbfs lib:
...................................................
E: file offset: 9218
E: file type = 4
E: file attribs = 0
E: section offset: 9230
E: section type: 12
E: TE image at offset 9234
E: TE Image 0xffed80d4 -> 0xff256234 adjust value: ff37e000
E: Relocs for RVA offset 12000
E: Num relocs in block: 18
E: reloc type a offset f40
E: Unknown reloc type: a
Portion of build output after fix:
..................................
E: file offset: 9218
E: file type = 4
E: file attribs = 0
E: section offset: 9230
E: section type: 12
E: TE image at offset 9234
E: TE Image 0xffed80d4 -> 0xff256234 adjust value: ff37e000
E: Relocs for RVA offset 12000^M
E: Num relocs in block: 18
E: reloc type a offset f40
E: Adjusting 0x7f2e7f377024 ffee9192 -> ff267192
E: reloc type a offset f48
TEST: Integrate FSP blobs built with 64 bit and do boot test.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I894007ec50378357c00d635ec86d044710892aab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65383
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Fixes a bug in Makefile.inc.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2664df961a1fc0cd904a5e742face20c3fc8c3c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65450
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Debug FSP is ~850KiB larger than release FSP and we don't have
sufficient space for nissa flash layout.
Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.
Note: This fmd will only used for internal testing/debugging and not for
the firmware in released devices.
BUG=b:231395098
TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Intel FSP has "debug" build which is not public, used for debugging by
approved developers. Add a Kconfig to indicate that coreboot is building
with debug version of FSP so we can adjust few things (i.e. flash
layout) in the case.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ibc561498d7edcb9d7ec155f090822f1eb25d10cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65466
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Add chipset devicetree and power limits for AlderLake-S platform.
Based on Intel docs #619501, #619362 and #626343.
Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Change-Id: I422ece7b64bf81bcc75a414fd27f15ec330d40be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Reverting commit 1e25fd426ad8 ("soc/amd/common/block/psp: introduce
AMD_SOC_SEPARATE_EFS_SECTION").
A better solution was used in commit c17330c1dddb ("mb/amd/chausie: Add
EC blob into CBFS"), and this is no longer necessary.
TEST: Boot chausie
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I27a8622a1f0d871690b181a79adca225a20996ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add ADL-S specific table with IRQ constraints to avoid accessing
non-existent devices.
Also when using debug FSP, silicon init would assert on assigning IRQs
for non-existent devices. This patch fixes the problem.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib4464a85bc11a8603bf471ea348bbfc9481db4aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Due to incorrectly interpreted DOC #630603, the reserved range
remains the same for all ADL platforms and is sync with
src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the
range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was
only mean for static allocations, but the rest is also reserved. The
only difference between ADL-S and other ADL platforms is Trace Hub
base.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Disabling the ASPM for I225V will cause I225V suspend fail, so remove ASPM_DISABLE for I225v.
BUG=b:235565637
TEST=emerge-brask coreboot and check LAN_I225V sku can boot into OS.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Id4505a713a3d92cb66c189cc2963111b6e90f092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add fingerprint device and select UART_ACPI driver.
Disable FPMCU until the proper boot segment initializes it.
BUG=b:228271993
BRANCH=NONE
TEST=Can add fingerprints and unlock the device using them.
Signed-off-by: Moises Garcia <moisesgarcia@google.com>
Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The `limit` field for the PMC fixed BAR was incorrectly set to the `base
+ size + 1`, where it should be `base + size - 1`, to correctly tell the
allocator the limit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icf51333f438ce2597c008b48305cf5816dacd3f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `limit` field for the PMC fixed BAR was incorrectly set to the `base
+ size + 1`, where it should be `base + size - 1`, to correctly tell the
allocator the limit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib2d8c7ffe87fdd970f3172bb4e6b2c9386859ab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65460
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Nivviks variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:237238786
BRANCH=None
TEST=Build and boot Nivviks.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Iea5c6e0c404efb8231321701ea9282347e01f75d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Based on latest schematic:
1. Update devicetree for USB port description
2. Add touchscreen ILITEK, amplifier ALC1019, codec ALC5682
3. Configure GPIO table to reflect that
4. Remove APW8738BQBI IC so set "disable_external_bypass_vr to "1"
BUG=b:235303242, b:236791101
BRANCH=dedede
TEST=build
Change-Id: I38c8c5b913013d818ac6a26284184c9decdd9f4e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65079
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kernel driver will en/disable the IRQ when suspend/resume. If lock
the pin, driver can't change the status which causes the unexpected
behavior. Device will wake when insert the pen. This is workaround
until we figure out the correct setting for driver.
BUG=b:233159811
TEST=Pen garage wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifc7b1e52a24c0e7bd54664d59870cb09536ef868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65380
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:231690996
TEST=gpios are the same in kernel pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I67a466fac478b2a3a682451174fbdcdd67816769
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Based on schematic and gpio table of pujjo, generate overridetree.cb
settings for pujjo.
BUG=b:235182560
TEST=FW_NAME=pujjo emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I47b10d03798004d1f3e398070acb2cbad46900b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Change-Id: I0b9bd00a5de4c2c8d91fa9d595d3ee313356048a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB
helps in improving overall boot time since it reduces hashing and
body loading time (~30ms).
Backport changes from commit hash 84532dae1 (soc/intel/alderlake:
Change VBOOT_HASH_BLOCK_SIZE to 4 KiB).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3784b99bf06e0c03d123f290a98a0b1e4528b8d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64792
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
BUG=b:224325352
TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
skolas4es variant.
BUG=b:230773725
TEST=None
Change-Id: I12b05cdacdd26bfffff47b7a3fb127aa7778f15d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65493
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`chipset_lockdown` is no longer configured in this devicetree.
Change-Id: Iaaacd471ab873f150d7a74bba612130c33641c64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
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Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs.
References:
RaptorLake External Design Specification Volume 1 (640555)
600/700 Series PCH External Design Specification Volume 1 (626817)
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic2b9a22bc6c32030f960d59b2874be5459c3ba28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Code taken from TGL base.
TEST=Boot MSI PRO Z690-A WIFI DDR4 and see all devices have SSID
applied
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3a6d299ec40bac8e29d06926572e375d7d835e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The temperature values were taken from guybrush as a starting point for
skyrim.
BUG=b:230428864
TEST=Boot skyrim to OS and verify thermal zones are populated and
working in /sys/class/thermal/
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6669b32f5e3dd63c6523f74166089eb4eb2d7848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed. After confirmed with the owner, the expect behavior is
only wake when eject the pen.
BUG=b:233159811
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7a82e5e8935c9ea27e923661f66809e9169bc86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65379
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add MIPI WFC based on schematics
BUG=b:236576117, b:235446911
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bd2ba187729a55c00369b218ca0414e0162b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Follow latest schematic to modify SPI flash to 16M.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I56be68b962c38d3f885dcf25a0251b8d9ab6ff3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65446
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE.
Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Extend the code to support ADL-S PCIe Root Ports.
Based on DOC #619362 and #619501.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset.
Add IRQ routing tables for PCIe Root ports up to 28th.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As we walk the results of largest_resource(), we actually know that the
condition can only be true for the first return value. So there's no
need to keep track of the first loop iteration.
Change-Id: I6d6b99e38706c0c70f3570222d97a1d71ba79744
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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While what this round() function does is documented, it still seems
hard to follow what happens when reading a call. I tried to come up
with a better name, but eventually reading an explicit ALIGN_UP()
worked best.
Change-Id: Ifd49270bbae0ee463a996643fc76bce1f97ec9b7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65400
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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These comments are a very nice example of documented code. The
comment blocks use the full, allowed line length, though. That
is nice for code, but can make text blocks harder to read. So
reflow the comments to a 72-char width (like we use in emails
and commit messages).
Also add some articles where they seemed missing and fix some
smaller nits.
Change-Id: If4cdbb383cf67f01200c8e4163fc3c576a5c3a87
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The comment said special care needs to be taken if a resource cannot
be allocated. However, the opposite seems true: There is nothing to
be done, we simply leave the resource w/o the IORESOURCE_ASSIGNED
flag. There's also no code to be found that would currently do some-
thing special. allocate_child_resources() directly continues with
the next resource after printing an error.
Change-Id: I21acbc891ea4dfb62decf9abe0ace91016486116
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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clcok ---> clock
Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Modify ddi_ports_config based on schematic Kinox_SCH_20220602.pdf.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_2 = DP or HDMI
BUG=b:233338341
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib2dbb34af1f85585b77638710d3799520c3f016f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The details about how the CPU multiprocessor init (MP) has migrated
from coreboot to FSP can be found in
https://doc.coreboot.org/soc/intel/mp_init/mp_init.html.
The major reason behind this migration is to support the Intel
proprietary and restricted CPU feature programming which can't be
performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part
of coreboot MP Init flow (prior to calling FSP-S). Hence, the new
flow introduced with Tiger Lake platform forced having monolithic
MP Init peformed by FSP (using coreboot MP PPI wrapper code).
The last 3-4 years of FSP doing MP Init has demonstrated ample
issues during platform bringup which is specific to UEFI MP Service
implementation and not relevant to open source coreboot. This new
flow makes the debug and validation aspect complicated where
any FSP MP Init code changes should have been validated with coreboot
MP PPI wrapper else might cause some failure, unfortunately,
the validation commitment has never been met, hence, issue debugging
is the only solution that remains in practice.
Most importantly, the restricted feature programming which demanded
closed source MP Init (for features like SGX and C6DRAM) has never
been enabled in coreboot (starting with Alder Lake, the SGX feature
has been dropped).
This patch attempts to decouple FSP-S doing MP Init from the rest
of the FSP-S silicon init and introduces 2nd MultiPhase SI init
which allows bootloader to perform the mandatory SoC programming
before FSP-S has done with PM programming (a.k.a set the reset CPL).
The core/uncore BWG suggests the minimum SoC programming before
BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2
to perform the required CPU programming before enabling the BIOS
Reset CPL.
This implementation would allow us to get rid of FSP running CPU
feature programming and additionally make several EDK2 MP service
modules optional (those are packed to create FSP-S blob).
In summary, this change would allow coreboot to utilize open source
MP init without running into FSP-S related code blocks.
Note: At present, Intel Alder Lake FSP doesn't have support for
MultiPhase SI Init, Index 2 (submitted a FSP code changes over
chrome-internal to enable this feature to decouple MP Init from
FSP-S init).
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Perform several thousands cycles of suspend test and power cycle
without running into any issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I314c63c917ef6fdd32f364b2c60bae22486b8b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64979
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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mc_apl7 does not use security features like VBOOT and TPM.
Test: flash mc_apl4 mainboard and ensure the disabled features via log.
Change-Id: I16683b92deb047208848b69c5aa79dc4212ce930
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65284
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add a new board 'Tentacruel', and enable SDCARD_INIT for it.
BUG=b:234409654
BRANCH=corsola
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ia10efeead575b4e193a73562275a78839415a706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65192
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change makes mdss configuration common for both sc7180 & sc7280
to avoid code duplicacy.
Changes in v2:
- Move soc related mdss changes to soc specific disp.c
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Change-Id: Ibc43ab6ee5ced08e34625e1485febd2f4717d6a0
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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In order to improve gpio merge mechanism. Change iteration override
to padbased table override. And the following patch will change fw
config override with ramstage gpio table override.
BUG=b:231690996
TEST=check gpios in pinctrl are the same.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3d0beabc2c185405cb0af31e5506b6df94e9522c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Introduce three functions:
- new_padbased_table:
Returns the gpio pad number based table
- gpio_padbased_override:
Must pass the table with padbased table
- gpio_configure_pads_with_padbased:
Must pass the table with padbased table, will skip configures the
unmapped pins by check pad and DW0 are 0.
Some boards may have complex, SKU-based GPIO programming. This
patch provides for a simpler pattern of controlling overrides of
GPIO programming by providing a table of pad configuration indexed
by pad number. Thus, pad state can be overwritten over multiple
overrides until the final takes place, and then all GPIO
programming is performed at once.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8b99127b73701b50a7f2e051dee9d12c9da9b741
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64712
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia44be7d63b0e6e16a49695d430715a7e5785d530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic31eb81bc98fd94877a51ebf44cfb2c69e4db0ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55923
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9c680d12f023d8682288e9d3619f549484f3b975
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I80ee3a8bb28d5f7b2a47b0a98abbc53a95ad25bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55917
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0e68912bf7f1ccb130b8bc6213308ec2e846efc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55920
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I668a39c603870329fd1528ddc5f3a42a379e1e76
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65267
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The only callsites in intel/xeon_sp were replaced with calls to
log_resource() and functionality is provided with LOG_RESOURCE()
now.
Change-Id: Ie44694f7a0b119d10f1bef9158fa30e71c312a55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55478
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace xx_resource() calls with calls that take the base
and size arguments as-is, without dividing by KiB (or >> 10).
With replacement of the allocator/constructor function
caller can use log_resource() instead.
Change-Id: I7e4e1e5a779c418f369dd2dab8c811f67ad1399f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55477
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These should help to make the reviews as platforms
remove KiB scaling.
Change-Id: I40644f873c0ea993353753c0ef40df4c83233355
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Function fixed_io_resource() and alias io_resource() were
previously unused. Unlike previously, IORESOURCE_STORED flag
needs to be set by the caller, when necessary.
For fixed resources, fields alignment, granularity and
limit need not be initialised, as the resource cannot
be moved. It is assumed the caller provides valid base
and size parameters.
Change-Id: I8fb4cf2dee4f5193e5652648b63c0ecba7b8bab2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Unlike fixed_mem_resource_kb() the arguments are not in KiB.
This allows coccinelle script to assign the base and size
without applying the KiB division or 10 bit right-shift.
Unlike with fixed_mem_resource_kb() the IORESOURCE_STORED flag is
passed in the flags parameter until some inconsistencies in the tree
get resolved.
Change-Id: I2cc9ef94b60d62aaf4374f400b7e05b86e4664d2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch changes the serial message type to BIOS_WARNING as sometimes
it may raise a wrong signal when microcode resides inside other part
of the IFWI instead /CBFS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I714bf74a91c2d783982c5e5ca76a70deed872473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65316
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch drops FSP Debug interface selection as coreboot now decides
the UART inerface to redirect the debug msg.
BUG=none
TEST=Able to see all coreboot and FSP debug log with and without this
patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If8c07d7e63c5d445fdb77ac38b99217bf015e15f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Enable caching of memory training data for recovery as well as normal
mode. We had HAS_RECOVERY_MRC_CACHE selected in the sc7280 Kconfig,
but never allocated a RECOVERY_MRC_CACHE in the herobrine fmap so it
never worked. Adding RECOVERY_MRC_CACHE and also removing
RO_DDR_TRAINING, RO_LIMITS_CFG, RW_LIMITS_CFG entries which have been
deprecated.
BUG=b:236995289
BRANCH=None
TEST=run dut-control power_state:rec twice and make sure that
DDR training doesn't run on the second boot.
Change-Id: I39ac7eca4ae94075874324b13c69eef59522e3c5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Having PTT means mocking secdata, so saving/reading the hash always
succeeds, but there is no data stored/read from/to TPM. The code
comparing MRC hashes did not care if secdata mocking was enabled
and failed during hash comparison with invalid data. This broke the
fastboot even if the MRC cache data was filled and correctly
checksummed. If mocking is enabled simply fallback to checksum
computing to proceed with fastboot.
TEST=Boot MSI PRO Z690-A WIFI DDR4 in fastboot mode with PTT and vboot
enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic0cf04b129fe1c5e94cd8a803bb21aa350c3f8da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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With CB:65012, google_chromeec_vbnv_context() is no longer used. Remove
it from the codebase.
BUG=b:178689388
TEST=./util/abuild/abuild -t GOOGLE_STOUT -a -x
Change-Id: I717f600f0f73c3ca932b6a442a9d5b90c35c8f3b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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We have clarified the powerdown sequence with Nvidia, and the EEs have
come up with this modified sequence which still meets the requirements
from the hardware design guide.
BUG=b:233959099
TEST=Verified by ODM and EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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These changes made my crude pattern matching work with
coccinelle simpler.
Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Commit 0cc56a2848 (nb/intel/gm45/dsdt: Fix number of PCI busses) derives
the maximum PCI bus number at runtime. However, IASL complains about the
initial 0 in the resource template, which rendered the PB00 definition
self-contradictory at build time (maximum was lower than minimum +
length - 1).
Let's return to the old default values (min: 0, max: 255, length: 256)
and adapt max and length at runtime. Also fix some surrounding whites-
pace.
NB. The issue wasn't detected before merging commit 0cc56a2848 because
of broken IASL versions that can't count errors.
Change-Id: I359d357f276feda8fe04383080d51dc492c3f2e8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64347
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Return the correct processor family code for smbios per System
Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0.
BUG=b:234409052
TEST=Boot chausie to chromeos and verify "dmidecode -t processor"
outputs the correct processor family.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for osiris board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for osiris board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia30a7b915df14c91a2526dca3e374436da286b7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2986ae6fd1f51efc6b9bb18ff2b7186357e55fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Configure GPIOs according to schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8c4347fcc975ed994261c7738e5ef811a12e4b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Base on bernadino 14 adl-p 20220531.pdf, configure GPIOs
according to schematics.
GPP_B2 => BYPASS_DET
GPP_F19 => FP_USER_PRES_FP_L
BUG=b:234384954
TEST= USE="project_crota" emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ic2e7ecc34912f07463e0025787fdf59c7602e40b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Added missing set_resources function to avoid error messages in boot up
logs.
BUG=b:230576402
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com>
Change-Id: Ie0a5bd345486293ce07e586a423d53740ad377f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This patch ensures google/volmar eMMC SKU has advanced PM support
enabled.
BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e2883d894d2ca7f810f4b72af1c12037c8fdabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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The previous two patches removed all of the soc/Kconfig files, so there
is nothing to include anymore. Get rid of the 'source' command that
includes them.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I95067c4702ef25a8a6db4d480c089f06986ce9b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65329
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the Intel top_swap feature into the intel/common Kconfig file.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3ed649aaeb51c2250be9473114c17d3f191d2c38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Most of the src/soc/Kconfig files are only there for AMD and Intel to
load the main SoC Kconfig files before any common files. That can be
done in src/Kconfig instead. Moving the loads to the lower level allows
the removal of all but the Intel soc/Kconfig file, which can be removed
in a follow-on patch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Clean up Makefile.inc by sorting entries and moving common entries to
all-y. In this way it is more clear to know what drivers have been
involved in each stage and the hardware differences between each SoC.
BUG=none
TEST=emerge-corsola coreboot
TEST=emerge-asurada coreboot
TEST=emerge-cherry coreboot
Change-Id: Idfc7de36ebf36650f7c6bd1584ef77e2a540cde9
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65315
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `send` and `recv` API functions currently print error messages
if a timeout occurs while polling the EC, but they perform the I/O
transaction regardless. This can put the EC in a bad state or
otherwise invoke undefined hardware behavior.
Most callers ignore the return value currently, but for callers
which do not, we should make sure our behavior is correct.
Signed-off-by: Abel Briggs <abelbriggs1@hotmail.com>
Change-Id: Ifb87dd1ac869807fd08463bd8fef36d0389b325e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033682
TEST=Built and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I8135684d471fdcfdbbe2f1bc5455902d56bb71de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for volmar board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I4d12f7214a306ded54b4536a27fe0fb7f3c33b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This CL fixes my previous CL (commit ca741055e)
which introduced a couple of issues found by Coverity (see below).
The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)."
*** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size()
*** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size()
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the desktop board types as per DOC #573387.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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This patch fixes an issue introduced with commit ca741055e
(soc/intel/adl: Add missing claimed memory regions) where PRMRR base
should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead
System Agent PCI configuration space.
With this change, coreboot is able to read PRMRR base when the
PRMRR size > 0.
TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
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This patch adds a new mainboard variant called mc_apl7 which is based
on mc_apl4. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.
Test: build mc_apl7, flash to mc_apl4 and compare log level 8 output
Change-Id: Ie9f2f5c29d071de442f8f3e3eaf4b3c2a6b8920f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65283
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The common AMD ACPI GPIO access code is verified to be correct for
Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I834076c0a1d1784a272896f2d8f082ebfb86a383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The MCA banks were updated in commit 736d68c0b36e ("soc/amd/sabrina/mca:
update MCA bank names to match the hardware"), but seems that I forgot
to remove the TODO about checking if this is still correct for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd86113ccb9eeab704679afab0b985f9febed13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The common microcode update mechanism is verified to be correct and work
on Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5c41674299a829507438beb3ea597a71a0c5a972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The bits are documented in NDA document #55758.
BUG=b:228458221
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibc27f617ca9c9620b3b2cb0837b661fa0cd36c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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There is an existing issue for nissa boards where wake up from
RTC wake is not working during suspend_stress_test.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Reference: https://review.coreboot.org/c/coreboot/+/64089
Later issue was found to be with GPP_F14 configuration for nissa
boards. When coreboot skips setting GPE_EN bit for GPP_F14, RTC
wake works properly. Another way to make it work is to skip locking
GPP_F14 GPIO to allow kernel to configure it properly.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later. This fixes the issue of RTC wake not working.
Note: This patch provides workaround for the existing issue and
BUG will be closed once actual reason is identified and proper
fix is available.
BUG=b:234097956
BRANCH=None
TEST=RTC wake works on Nivviks board with the patch.
Change-Id: Ie8091ab8acf2b3f064cb79bdf4700f6b4c1674a5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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