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The South Station recieved updates that fix a number of fadt problems.
South Station now uses the southbridge fadt.
Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
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Requirements:
- must be in ramstage (locking flash while executing code from there
might not work)
- must be after cbmem is reinitialized (so the mrc cache copy of the
current run can be found)
Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- Separate Sandybridge from ChromeOS a bit
The Sandybridge code depends on chromeos features a whole lot.
As a first step, provide a code path to look up the MRC cache
without depending on u-boot.
- Move mrc cache handling to separate file
This enables us to handle the MRC cache from ramstage,
where we can write the flash safely (eg. to update the
cache).
Also teach it to lookup the current MRC cache from CBMEM,
as the original data block isn't available anymore.
After all the preparations, finally write to the SPI
as necessary. It's a simple round robin wear levelling
that erases the entire MRC cache region when it's full
and starts from the beginning.
Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This driver is taken from u-boot and adapted to match
coreboot. It still contains some hacks and is ICH specific
at places.
Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/997
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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For legacy free AMD systems, the #define LEGACY_FREE cannot
currently be overridden. This patch allows the platform_cfg.h
to override that. (I know we want to get away from that, but
for now...)
Also allow BIOS_SIZE to be overridden on SB700 cimx based
platforms.
Change-Id: I570115248bcbc686062bfb66acb56208240b847a
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1018
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Change source file modes from 755 to 644
The following files have been grepped for changes:
*.c
*.h
*Kconfig*
*Makefile*
Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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MA785GM-US2H was left out of Kconfig. This
allows the option to select the board.
Change-Id: I9efea96c21dcd0754ab51824b410435b0b5300c2
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1022
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The fadt.c is the same across all the platforms using the sb800
cimx southbridge wrapper.
Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1019
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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These are the PMIO & PMIO2 read & write routines from
src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx
tree. Currently most platforms using CIMX are calling WritePMIO()
directly from the src/vendorcode/amd/cimx/sbX00 directories
instead of using a wrapper function.
These functions only do byte reads & writes.
Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/981
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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If serial uart (8250/16x50) takes abnormally long to respond, give
up on logging to serial console and instead let the system boot.
Also reference bit in LSR register with correct name.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to
uart8250mem.c:
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Iaca4f57389c887110e6406d45053935891c96838
Reviewed-on: http://review.coreboot.org/826
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
(manual tweak since it hit a false positive)
Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +
Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1006
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change is taken from Linux. It allows to check for Kconfig
definitions in the preprocessor and source code using the same
idiom.
Long term plan is to remove our Kconfig hack to #define values to 0,
and this helps.
This includes a tiny modification to the macros to fix romcc support.
Change-Id: I0fddbea8c8ca215cf226acf39cb329b0ba0445a5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1005
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
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- Prefix all CBFS output messages with CBFS:
- Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS
enabled, the code will no longer print all the files it walks for
every file lookup.
- Add DEBUG() macro next to LOG() and ERROR() to specify which messages
should only be visible with DEBUG_CBFS printed.
- Actually print a message when the file we're looking for was found. :)
old:
Searching for fallback/coreboot_ram
Check cmos_layout.bin
Check pci8086,0106.rom
Check fallback/romstage
Check fallback/coreboot_ram
Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24
Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000
Stage: done loading.
new:
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000
CBFS: stage loaded.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/993
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I40a4201b468131ba67e48ab68d62ca5413f2e2e8
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Otherwise set_subsystem isn't called for these (as they're not
marked on_mainboard)
Change-Id: I08e781735c59e4aa61009d2afa165d782f5a849e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/998
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In a recent commit the SATA code of Panther Point / Cougar Point was
changed to enable AHCI mode depending on the device tree settings rather
than a hard code hidden in romstage.c. However, Emerald Lake 2 was not
fixed up accordingly.
Change-Id: I6c93f386509361e1ab5565b0e4d0e84f0ba282a2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/995
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I1ec7a7e54513671331ac12f08d5f59161b72b0fd
Example:
PSS: 1900MHz power 35000 control 0x1300 status 0x1300
PSS: 1600MHz power 28468 control 0x1000 status 0x1000
PSS: 1400MHz power 24291 control 0xe00 status 0xe00
PSS: 1200MHz power 20340 control 0xc00 status 0xc00
PSS: 1000MHz power 16569 control 0xa00 status 0xa00
PSS: 800MHz power 12937 control 0x800 status 0x800
PSS: 1900MHz power 35000 control 0x1300 status 0x1300
PSS: 1600MHz power 28468 control 0x1000 status 0x1000
PSS: 1400MHz power 24291 control 0xe00 status 0xe00
PSS: 1200MHz power 20340 control 0xc00 status 0xc00
PSS: 1000MHz power 16569 control 0xa00 status 0xa00
PSS: 800MHz power 12937 control 0x800 status 0x800
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/994
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The CBMEM_ID_RESUME_SCRATCH area is only used by Agesa code, on one
particular board (AMD Persimmon). Make the creation of that section
depending on Agesa so it does consume space on non-Agesa systems.
Change-Id: I2a1a4f76991ef936ea68cf75928b20b7ed132b84
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/992
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/991
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Sandybridge memory initialization produces some amount of training data
that has to be kept around in CBMEM. Add a descriptive name to the CBMEM
pretty printer to prevent it from just printing the hex value.
Change-Id: I587c0bc3dfcf389ba298d445d2594eef73bc69a8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/990
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Another bug in the Intel microcode update code that existed since we switched
to LinuxBIOSv2 in 2004:
The inline assembly code that reads the CPU revision from an MSR after running
cpuid(1) trashes registers EBX and ECX. Only ECX was mentioned in the clobber
list. C code running after this function could silently access completely wrong
data, which resulted in the wrong date being printed on microcode updates (and
potentially other issues happening until the C code writes to EBX again)
Change-Id: Ida733fa1747565ec9824d3a37d08b1a73cd8355f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/996
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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No part of ChromeOS seems to use the debug header description, so drop
it to make sure it does not get copied around wrongly.
Change-Id: Icb0baedbf6112f11289b2ddd9618a955a424ddf7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/989
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: If183611b0b62d9321a5a12311c4cb3b344b04b36
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/986
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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If microcode.c is built by romcc, this indicates that we are running
microcode updates in the bootblock (e.g. before enabling cache as ram).
In this case we did not enable any consoles yet, so we don't output
anything.
This patch removes inclusion of the unnecessary console/console.h for
that case, which was breaking with certain configurations.
Change-Id: Iebb57794d7b1e84cac253d249d47b88de4dd28a3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/988
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This fixes my build when specifying an absolute path to the binary.
Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/987
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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It is important to have the system configuration reported as early as
possible to have a better idea what exact chipset the platform is
running with.
This change adds code to have an early coreboot module report the CPU
and PCH information. CPU info includes the 32 bit feature information
word, the symbolic processor brand string, and information about some
features support, as obtained through CPUID instructions.
The PCH information includes the symbolic device name and PCI device
version.
Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The current early PM setup that attempts to configure dynamic clock
gating relies on PCIe functions to be enabled that may not be.
Instead of reading port 0 or 4 directly to determine the link width
use the register that refelects the soft strapping options as this
will always be available.
Also add a clear register assignment and break for port 0 in the
switch statement instead of falling through to port 4 as that could
end up setting the slot power limit based on port 4 values instead
of based on port 0.
register 0xE1=0x3f and all other root ports should have 0xE1=0x03.
When port 0 and 4 are disabled they will have 0xE1=0x3C before
being disabled by the pch enable handler.
LUMPY default:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 3 0xe1
0x03
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 1 0xe1
0x03
Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/980
Tested-by: build bot (Jenkins)
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Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices
implement function 0. The Linux Kernel therefore will not enumerate
a PCI device if it does not present a valid config space at function 0.
If a board does not have anything connected to root port 0 and it is
desired to disable the unused ports in order to save power then this
will cause the other downstream PCIe devices to go missing as they
will not be enumerated.
Intel chipsets provide a way to map root port numbers to different PCI
function numbers, thereby avoiding this issue and allowing root port 0
to be turned off.
This change adds a new chip config option 'pcie_port_coalesce' that
will collapse the enabled root ports into a linear map starting at
zero. This option defaults to disabled as it can have a confusing
effect on the system as the declared static devicetree may not match
what is seen at runtime. This option is also forced on if the static
devicetree disables port 0.
When each root port is processed in the early enable stage it looks
for a lower numbered root port that has been disabled and then swaps
the two assigned function numbers.
However the mapping register is write-once so it has to keep track of
the proposed mapping changes until all ports have been processed
before writing out the final map value. At this point it also updates
the function numbers in the static device tree so they are consistent
with the new layout.
There are a few other closely related fixes in this change:
1) There is a power savings opportunity if an entire bank of ports
(0-3 or 4-7) are disabled. This was checking the chipset revision to
look for CougarPoint B1+ stepping and that was not passing on
PantherPoint where this should always be applied. To fix this I added
a function to determine the chipset type based on comparing the upper
byte of the device ID.
2) Apply the same chipset type check fix to the IOBP programming.
3) There is another power savings opportunity to enable dynamic clock
gating on shared PCIe resources which only applies to ports 0 and 4.
However if 0 or 4 is disabled then the later check to enable this
would fail as that device is already hidden.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/979
Tested-by: build bot (Jenkins)
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The chipset enforces static-defined interrupt swizzling on PCIe root
ports so if a port is remapped to a different function it needs to
still report the proper interrupt map to the OS instead of assuming
that function number is equivalent to root port number.
This change also includes an update to the PCH function disable
register which was incorrect for CPT/PPT and would cause unpredictable
behavior if used.
The kernel command line was changed to add 'nomsi' in order to force
PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
that the mapping is correct.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/978
Tested-by: build bot (Jenkins)
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CONFIG_MAX_PHYSICAL_CPUS is defined by quite a number of
mainboards whithout any code actually using the variable.
Hence, drop MAX_PHYSICAL_CPUS from Kconfig for those boards.
In the long run we should drop CONFIG_MAX_PHYSICAL_CPUS use
completely and make the code dynamic or depend on CONFIG_MAX_CPUS
instead.
Change-Id: I37dcc74d245ddba5186b96bd82220dacb6f4d323
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/984
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The sata controller comes up in legacy/normal mode and
is currently put into AHCI mode in romstage.
If that is removed and the controller is left alone until the
ramstage driver (like we do on Stumpy/Lumpy) then the resource
allocator will have configured the device for IDE mode with an
IO address in BAR5. Then when the ramstage driver puts the
controller into AHCI mode it will not have the correct resources
to do the rest of the AHCI setup.
So the controller mode needs to be changed in the enable stage
rather than in the init phase. This same register contains
the port map and it is a R/WO (write once) field so the configured
port map must be written at the same time. For non-AHCI mode
the devicetree map was ignored before but it is used now.
Since the port map register is now written at enable step it
does not need to be written again during init.
With this change the sata port map can be reduced to just port 0
and then U-boot does not have to probe all available ports.
Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/977
Tested-by: build bot (Jenkins)
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- New table for GT1
- Updates to GT2 17W table
- New table for GT2 35W SKU
- New table for GT2 Other
This also includes a workaround to poll on a different register
when deasserting force wake. On some SKUs the kernel is hanging
when bringing up graphics unless this register is also polled.
Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/974
Tested-by: build bot (Jenkins)
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- Add config options to set backlight registers
- Update powermeter weight tables for IvyBridge GT1 and
add a new table for GT2 SKU
- Fix a few registers used during GPU PM init sequence
Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/973
Tested-by: build bot (Jenkins)
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Port u-boot patch for low-level driver:
- Fix bug in traversal of vendor name list.
- Sending "command ready" needs additional logic to handle
TPMs that need that bit set twice: once to empty the read
FIFOs and once to actualy set command ready.
Change-Id: I57c280266b2e966c5b90e4f9e968426a33b93cf1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/972
Tested-by: build bot (Jenkins)
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The OS does not re-execute the APMC 'enable ACPI' SMI
on resume so this has the potential to leave things
in an unknown state.
Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/971
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is done inside the SystemAgent binary on Ivybridge.
Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/970
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The ASPM setting for the Direct Media Interface should no longer be done on
Ivybridge/PantherPoint based systems.
Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://review.coreboot.org/969
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This adds the PCI device id of the LPC controller identifying the
QPRJ/QS stepping of the Panther Point southbridge.
Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Many PCI devices share the very same driver despite having different
PCI device IDs, which causes a lot of copy and paste of driver
definitions.
This change introduces a way to specify the array of acceptable
device IDs in a single driver entry. As an example the Intel
{Sandy|Ivy} Bridge SATA driver is being modified to use a single
driver structure for all different SATA controller flavors, a few
more Ivy Bridge IDs are being added as well.
BUG=none
TEST=manual
. modified coreboot brought up an Ivy Bridge platform all the
way to Linux login screen.
Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I4a64a56dda22050a31232807096e15565a665377
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/967
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The Emerald Lake 2 CRB can potentially have more
than 8 CPU cores, so update the number of max cores
accordingly.
Change-Id: Ia42ed8a84916f66dfbfdf2a72cbbed5cea61899b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/966
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The Emerald Lake 2 CRB wasn't designed with ChromeOS in mind, so there aren't
any actual developer mode, recovery mode, or write protect switches, let alone
GPIOs to read them from. Instead, I've commandeered signals connected to GPIOs
which are for other things but which aren't used by hardware or, for instance,
the EC to do something Coreboot doesn't control.
The recovery mode switch is connected to GPIO 22 and is called BIOS_REC on the
schematic. The name is at least very reminiscent of the right thing even if
it's supposed to be used for something else. There's a jumper on the board
labelled J8G1 which can force the line to ground, and if not, there's a switch
on the front of the case which toggles its value. "RECOVER" is for recovery
mode and "KEEP" is for normal mode.
The developer mode switch is connected to GPIO 57 and is called SV_DET on the
schematic. It's connected to a jumper labelled J8E2 on the board and, as far as
I can tell, can't be controlled in any other way. When the jumper is in place
and the pins are shorted, developer mode is selected. When the jumper is
removed, normal mode is selected.
The write protect is connected to GPIO 48 which is called BIOS_RESP on the
schematic. It's connected to a jumper labelled J8E3 which, like j8E2, seems to
be the only way to control the line it's on. When the jumper is in place,
write protect is "disabled", and when it's in place it's "enabled" even though
there's no functional difference.
The input for the recovery mode switch was chosen because of the name it
already had on the CRB, BIOS recovery, and because there's a switch to control
it on the front of the case which makes it easy to get at. The jumpers for
developer mode and recovery mode were chosen because there weren't very many
options available, and of those these were next to each other which should
make them easier to find and work with. It might be a good idea to wire toggle
switches up to the pins of those jumpers so they'll be easy to identify, can
be labelled, and would be easier to work with than little jumpers in the
middle of the motherboard.
Change-Id: Ib2c3dc05077dacfbede596dae143ed81a99dbebd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/965
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This fixes a few cosmetics with the following three boards:
- Intel Emerald Lake 2
- Samsung ChromeBook
- Samsung ChromeBox
The following issues were fixed:
- rely on include path in ASL code instead of specifying relative
paths
- use updated ALIGN_CURRENT in acpi_tables.c
- use preprocessor defines instead of hard coded values where possible
Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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Instead of the special case in the generic Makefile.inc,
use cbfs-files in the CPU directories.
Change-Id: I71d9c8dff906c9a516ac0dd09a315f8956075592
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/962
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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stages have special cbfstool syntax, which we need to support.
Change-Id: I119255246af818f010acfc7ec2091a6184e74eb3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/961
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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... or fail if repository is not enabled.
Change-Id: I0a1e6d6fed852ec7edf96ace8346ae6b23838a56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/959
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my
best interpretation of the schematic. It may not be correct, but it doesn't
seem to cause any problems either.
Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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One option to allow using the repo (defaults to no),
one to let boards state that they require it in the
current configuration.
The build system checks out the repo if allowed, and
fails if the repo is requested by the configuration
but not desired by the user.
Change-Id: If71d80b329cf528aa467fcb0b4d9d7c7434aab27
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/957
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Change-Id: Ic93ad2749834c8f7a2ca1651d343561f2a496312
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/953
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/952
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This adds support for Intel's Emerald Lake 2 board.
Change-Id: Ifaeeac9d52fe655324ee29df5f7187b89b35f73a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/951
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This code fixes the sandybridge C state generation code to work with
the current version of the ACPI code generator.
Change-Id: I56ae1185dc0694c06976236523fdcbe5c1795b01
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/950
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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It's used by Sandybridge specific C state generation code.
Change-Id: Ia6f1e14e748841a9646fd93d0a18f9e8f2a55e29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/949
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This code is still using libfdt which was denied for inclusion
in coreboot, so it won't compile as is.
Without MRC cache, waking from suspend won't work, and cold boots are
significantly slower (adds around 300-400ms per channel IIRC).
A rework of this code is currently in the works, but will take a little bit
more time (and should not hold back the mainboards being merged)
Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/948
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I9c5148eb315e2f478cb753d9918144a19e417379
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/945
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Change-Id: I58050591198bb06de5f0ca58ca3a02f1cfa95069
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/944
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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... in order to unify the Sandybridge and Lenovo implementations
currently used in the tree.
- use acpi_addr_t in acpigen_write_register()
- use acpi_cstate_t for cstate tables (and fix up
the x60 and t60)
- drop cst_entry from acpigen.h
Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/943
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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AMD supplies their video bios for the Family 14h processor line
with Vendor ID: 1002, Device ID: 9802. This rom should work for
Device IDs 9802-9809. This patch maps all those device IDs to
0x9802 so coreboot will be able to load the vbios. If a vbios
rom using the ACTUAL Device ID is loaded, this function will not
be called.
This file should contain of all Family 14h Graphics PCI IDs so
that they don't need to be overridden on a per mainboard basis.
Change-Id: If3d4a744b3c400dea9444a61f05382af2b2d0237
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/955
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
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This is a model fadt.c that I would like to use for updating
several other AMD platforms with after acceptance.
- Updated to match ACPI 3.0b specification and added comments
to reflect that.
- Since smi_cmd is 0, remove commands that rely on it:
acpi_enable, acpi_disable, & pstate_cnt
Add comments to that effect.
- Changed preferred_pm_profile to SOHO Server (platform
specific)
- The southstation platform is legacy free - Updated
iapc_boot_arch and flags to reflect that.
- Added reset_register flag so that operating systems
will actually use the reset_reg. This is important
on legacy free systems.
- Updated Generic Address Structures to use access_size
name in the updated acpi.h. Added access sizes to
the structures where reasonable.
- Removed 64-bit x_firmware_ctl pointer to facs. This was
causing a fwts failure and windows-64 BSOD.
- Added bit width for pm2_cnt_blk and modified gpe0_blk bit
to match the hardware.
Change-Id: Icf1a982aa122636d1088c8b80f53d04732b54c49
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/942
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Change-Id: I4bd9b52cfc24a8ff73be05ee535b9e16c0d9bd79
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/946
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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since it is used in CPU specific ACPI generation code
Change-Id: I2559658f43c89dc5b4dc8230dea8847d2802990c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/947
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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- When calling map_oprom_vendev() the vendor ID and device ID
are joined into a 32 bit value. They were reversed from the
order that I would have expected - Device ID as the high 16 bits
and the Vendor ID as the low 16. This patch reverses them so
so that the the dword comparison in map_oprom_vendev() matches
what's entered into Kconfig for vendor,device.
- Change files calling map_oprom_vendev()
Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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If compiling coreboot with ChromeOS support, two
more include files are required.
Change-Id: I7e042e250e4a89e7dd4bab58443824d503c3f709
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/931
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge
systems.
Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/937
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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post_code() was added in our internal tree by duplicating code. It's not of
much use at this point, since the code is quite well tested, so avoid bloating
the bootblock (since compiled with ROMCC).
Also add some missing include files that didn't seem to be needed with an
older version of coreboot.
Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/936
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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string.h is required to build with the reference toolchain.
Change-Id: I9fd8d2ea8fc676d3502989cbcc7aefe3b2d738b6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/935
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Newer versions of IASL didn't like our IO constructs. Use
FixedIO instead, it's also shorter.
Change-Id: I9364d993ecb71ffd84c0313ca1e2f870af59eb24
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/934
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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rename from mainboard_apm_cnt to mainboard_smi_apmc to match the function
naming scheme of the other handlers. Add prototype for mainboard_smi_sleep
(mainboard specific S3 sleep handlers in SMM) that is required by Sandybridge.
Change-Id: Ib479397e460e33772d90d9d41dba267e4e7e3008
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/933
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In order to use the generic microcode update code in the bootblock, cpu/cpu.h
needs ROMCC guards. Also, delete the unused struct device declaration and move
the struct bus declaration to where it's used.
Change-Id: I0cc731c555593946e931a680ec93994932530599
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/932
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There is no reason for this to be a top level directory.
Some stuff from lib/ should also be moved to drivers/
Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/939
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- Added a union to identify the byte that was reserved in the
Generic Address Structure from ACPI 2.0 to ACPI 2.0b as the
Access Size byte for ACPI 2.0c to ACPI 5.0
- Added various #defines for use in the FADT
- Added a couple of comments for the #endifs
Change-Id: I294ddfd89fcb0ad88bb6e52d911f807d84671e82
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/930
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Most subsystems print their name with a colon, and then the
message. Do the same thing for the microcode update code.
Also, each microcode update has a date header. Print the
date from that header to make it easier to determine whether
you're running the latest microcode.
Change-Id: Ic22947c4b9f0502d4091d975e1f1ab42f70aa1aa
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/929
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
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- add GPLv2 + copyright header after talking to Ron
- "bits" in struct microcode served no real purpose but
getting its address taken. Hence drop it
- use asm volatile instead of __asm__ volatile
- drop superfluous wrmsr (that seems to be harmless but
is still wrong) in read_microcode_rev
- use u32 instead of unsigned int where appropriate
- make code usable both in bootblock and in ramstage
- drop ROMCC style print_debug statements
- drop microcode update copy in Sandybridge bootblock
Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/928
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Instead of opaque numbers like (1<<29), use
symbols like CR0_NoWriteThrough.
Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Without that fix the screen flickered with resolutions superior
to 832x624 because the cpu_ht_freq was 0 (so it ran at 200Mhz).
Change-Id: I1056d76b1d77f6177594ed9d03ecc5ae7b3c2c13
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/900
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Move final build results under $(objcbfs).
Move intermediate files under $(objgenerated).
Remove use of sed -i.
Change-Id: Ie035a1544848b26514a197c340f470201065b8d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/859
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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$(obj)/coreboot_ap -> $(objcbfs)/coreboot_ap.elf
It is really a ramstage for AP CPU and not a romstage, it is not
enabled for any mainboard by default, and it doesn't compile
even if enabled.
Change-Id: Ifb9c5cb6df65309660b000876cf6a9a3da9b6839
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/840
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move final build results under $(objcbfs).
Move intermediate files under $(objgenerated).
Change-Id: I0046f68938be81b8efa525aa50b39328ca02ecb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move final build results under $(objcbfs).
Move intermediate files under $(objgenerated).
Change-Id: I0365304e1b0ed02a5a3ec720b0cf3e303eaefa7c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/838
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib5a34491531228db9a9232322bd573fded27ee67
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/924
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Otherwise it breaks 486 boards without RDTSC, ending with
exception 6.
It ends like this on bifferboard:
Jumping to image.
Unexpected Exception: 6 @ 10:001007e3 - Halting
Code: 0 eflags: 00000016
eax: 001001fe ebx: 00100118 ecx: 00000000 edx: 00108e00
edi: 0010aaf8 esi: 00000000 ebp: 00117ff4 esp: 00117fd8
Please keep in mind 486, dont use rdtsc/cpuid in generic code, or if you do make sure make it non-default option.
Change that broke it: http://review.coreboot.org/#/c/749/7/src/boot/hardwaremain.c
Change-Id: I974b25377c20a11430b35b24dcc275d8cbfd2b9a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/925
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Fix tabs and whitespace for
ma785gm mainboard.c file.
Change-Id: I8c94bf428bc4e78871da8c64f89221af4151e16d
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/923
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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This commit adds the following to MA785GM:
Refactor some alignment handling
Unify Local APIC address definitions
ACPI: More ../../.. removal
Remove old AMD fam10 fixme comment
amd/sb700: Move HAVE_HARD_RESET to southbridge
Change-Id: I85a95bb641375dd61d1f58a2f2f972771d1d9ad9
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/922
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Add early_smbus.c for romstage-y list and remove respective
include on mainboard romstage.c files.
Tested on AOpen board.
Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch adds coreboot support for the
GIGABYTE MA785GM-US2H board.
This port now removes all dead code in
the previous patch set, and also boots Fedora 16
on x86_64 (Phenom II X4 955 BE)
On-board audio causes spurious interrupts and
the kernel gets stuck in an infinite loop.
AtomBIOS on RadeonHD video cards does not function
and causes another infinite loop. radeon.modeset=0
must be set. acpi=off must also be set.
With those kernel command line options set,
Fedora 16 makes it to the login screen. USB
mouse and keyboard don't work though. several
USB error codes on boot-up. PS/2 should.
Change-Id: I58a7083a023ebf7373b6ded2e9f0adda7ab76dea
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/476
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe
slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2
SIM sockets.
Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/521
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit d4d5e4d3e10da06a83d57a147bd58a733381de18 contains #ifdef instead
of #if, making the FSB/serial bus selection for APIC always select serial
bus. The bug is harmless on most chipsets because the bit is often RO,
but it breaks at least on VIA K8T890.
Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/921
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Comment out the id variable which is used in a commented code
block.
Change-Id: Ib002d57e5314971f0589d04b7e451ab7d7079f53
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/913
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Final build results (.elf, .debug, .map) are to be placed under
directory $(objcbfs), the default is:
$(obj)/cbfs/$(CONFIG_CBFS_PREFIX)/
Intermediate build results (.o, .s, .S, .inc, .ld) that do not have
a clear one-to-one relation to a file under src/ are to be placed
under directory $(objgenerated), the default is:
$(obj)/generated
Also defines implicit rules for final build results:
.debug -> .elf and .map
.elf -> .bin
Change-Id: I448c6b7c9a952e54170df42091d7db438025a795
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/858
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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No longer include northbridge files directly in the source for
mainboard romstage.c and fix includes.
Also make required adjustments to function declarations.
Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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It takes about 3 seconds to scrub 8GiB DDR266 RAM.
After ECC scrub XIP cache is disabled for system stability. There is
very little to do in romstage after ECC scrub, especially when RAM
debug messages are turned off. So the delay caused by this is hardly
noticeable.
Cache for complete ROM is re-enabled before ramstage is decompressed,
and it has no unstability issues. So the code required to re-enable
cache for ROM currently already exists in cache-as-ram_ht.inc.
A Kconfig option HW_SCRUBBER enables the scrub to be run on hard
reboots and power-ons.
Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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As cmos.layout parsing capabilities are already there in nvramtool,
use those than using build_opt_tbl.c. Add binary and header file
generation in nvramtool. Make appropriate changes to Makefile.inc.
Change-Id: Iaf3f5d4f51451aeb33c92800a0c895045f2388cf
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/898
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Made using coccinelle:
@@
expression E;
@@
-(E + 7) & -8
+ALIGN(E, 8)
@@
expression E;
@@
-(E + 15) & -16
+ALIGN(E, 16)
Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/910
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change reverts :
Change Id I4fdb281b2b684ab5fea999aae28ca08dce24da4d
The wbinvd (or invd) should not be needed at the reset vector. It
causes problems with some CPUs AP init. If there is a problem with
a specific CPU and it must be done at this location, it should be
added conditionally.
Change-Id: I85b71b0a07f039359a4fb889aaa05c75fff619be
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/908
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Drop comments (from e7501 era) which no longer seem to apply with
e7505. Write the semi-constant D0:F0 table as code. Some register
settings seem to be in different order compared with vendor BIOS,
and will be handled by follow-up patches.
Split RCOMP register copy function in two parts.
Drop some uses of inline and local_mdelay().
Change-Id: I8739d3b2bbad5861118e8b16ccea1dd86991204f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/896
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Hope no more blank issue is got from future copy-paste.
Change-Id: I5eb50e8232e339e7039a15054606aaff6b7ebc52
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/907
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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S3.rom is useless for all the other boards which don't use flash to
save sleep/wakeup settings. AGESA-based boards other than persimmon
haven't been validated the S3 resume. They don't need S3.rom yet.
Change-Id: I12693e9556ca6f8e0d80b2ab2dca5c85bdb97685
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/902
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Fix the copy-paste typo in ALIB table creation. ssdt is useless here.
Change-Id: I250066eb5f755275f75c37789ce8760de35b046b
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/885
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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The name of processor created by AGESA is P00n, whose P is
BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
from 0. The dsdt should be aligned with that.
This feature has only been tested on persimmon. The changes on all the
other boards were propagated.
Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/884
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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