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2021-01-28ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Declare GNVS variables globallyKyösti Mälkki
There is a common place where acpigen generates these, so the declarations for the OperationRegions should be centralized too. Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki
With top-aligned bootblock this is no longer globally needed. The default maximum is now a generous 256 KiB with couple platforms having lower limits of 32 KiB and 64 KiB. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28arch/x86: Top-align .text in bootblockKyösti Mälkki
Move .text section closer to .init. This reduces the size of the flat bootblock binary and footprint in CBFS. Change-Id: I64325bd633e1104853cfb928c7f801d94ff3045a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28arch/x86: Top-align .init in bootblockKyösti Mälkki
Link .init section near the end of bootblock program. It contains _start16bit, gdtptr and gdt that must be addressable from realmode, thus within top 64 KiB. Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/x86: Rename __protected_start symbolKyösti Mälkki
It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Link entry32.incKyösti Mälkki
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/x86: Link reset16.incKyösti Mälkki
Change-Id: If2caab67286cf77e37928e03be4f581070e771d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47968 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Link entry16.incKyösti Mälkki
Change-Id: I78ecd15716169b58cf6696ff8c5069ac2d5038ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47967 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Refactor acpi_wake_source()Kyösti Mälkki
Change-Id: I44cb499260fdd0ea37308909a24cdf5ca1afa025 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Refactor fill_acpi_wake()Kyösti Mälkki
Change-Id: I7fcc2b36cfe57adf8ae3a6acf8b54e19504202a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49878 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/intel/adlrvp: Remove ClkReq assignment for RP8Subrata Banik
CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required. TEST=Able to detect PCIe SD card over x1 slot. Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28mb/intel/shadowmountain: Add flash layoutV Sowmya
This patch adds the flash layout for shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I7073d9c783684051e33e7a33eca50007d286bb00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-28soc/amd/picasso/acpi: Fix PCI0 MMIO windowRaul E Rangel
The PCI0 MMIO window was defined between TOM and 4 GiB. This was overlapping with the FCH MMIO devices. The first MMIO device after TOM is the FCH IOAPIC. This wasn't causing a problem for linux other than the fact that /proc/iomem showed all the MMIO devices under the PCI root bridge. On Windows this was causing all the MMIO devices to have conflicting resource errors. BUG=b:175146875 BRANCH=zork TEST=Boot linux and verify peripherals all work. Boot windows and verify the i2c controllers show up. The GPIO controller still has a problem related to power. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc409f1318e6da5a693ccbb3da74aafd13f1e058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49853 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso: fix CBFS MCACHE on ZorkKangheui Won
Zork platform was not booting with MCACHE enabled since psp_verstage had following issues with MCACHE. Fix all the issues and re-enable MCACHE for Zork. * psp_verstage should call vboot_run_logic, not verstage_main. vboot_run_logic calls after_verstage which handles RW MCACHE build. * It should avoid low-level apis for cbfs access. cbfs_map will build RO MCACHE if it's the first stage, while other low-level apis won't. * It should call update_boot_region before save_buffers MCACHE should be transferred to x86 so we should build it before calling save_buffers BUG=b:177323348 BRANCH=none TEST=boot Ezkinil Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso/acpi: Remove DMA addresses for UARTsRaul E Rangel
This is not the correct way to specify the FixedDMA devices. I'm removing for now since it adds confusion. BUG=none BRANCH=zork TEST=Boot zork to linux and make sure UART still works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-28soc/amd/cezanne/chip: add empty SoC device operationsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6321223b3b4b8d27ac696fdeeec75fd4bd1e6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49952 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/cezanne: compress FSP binaries in CBFSFelix Held
Compressing the FSP binaries in CBFS reduces the load time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0faf9a3937e4a5027eba6327a51060025971450f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49951 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28Revert "mb/amd/mandolin: Clean up IRQ numbers"Felix Held
This reverts commit 2a1638a9cead257115ff82b18862d506015378b2. The original commit broke Mandolin and with the revert applied, I can boot into Linux via SeaBIOS again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7024b6ff1e772bbc89f810c766655a5887ed8b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49950 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27nb/intel/haswell/haswell.h: Do not include `pch.h`Angel Pons
Avoid indirect header inclusion, include `pch.h` where necessary. Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-27soc/amd/picasso/chip: use switch/case statement in enable_dev()Felix Held
The default case is only needed to make the compiler happy. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27soc/amd/stoneyridge: Change set_sb_nvs_final()Kyösti Mälkki
Change-Id: I0de8033bae8c1dcfbc6fd7655ba748a3514e74e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/cezanne: Add UCODE firmware to CBFSZheng Bao
Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/picasso: Remove the useless definition of UCODE_FILEsZheng Bao
UCODE files are integrated in CBFS now, instead of AMD firmware group. Change-Id: I88fdd08ab400fad8e323251bb7dab4e4e01b0b88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27soc/amd: Throw an error if FWM_POSITION_INDEX is emptyZheng Bao
The empty string causes an undetectable build error. Filter out the board which doesn't define this variable. A great odds that the reason is the board doesn't set a valid ROM size. Change-Id: Iade1961460285acdec245c553c7b84014c30c267 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27mb/google/brya/var/brya0: Use auto-generated Makefile.incAmanda Huang
This change adds mem_list_variant.txt that contains the only memory parts used by brya0 for Proto-0 build and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. BUG=b:176491791 Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-27soc/intel/alderlake: Generate LP4x SPD files using gen_spd.goAmanda Huang
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with ADL-based mainboards. BUG=b:176491791 Change-Id: Ie75e43833bf9ba6557fc59cf8b4a0358d495e56a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49919 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27soc/amd/common: Only set write_acpi_tables if ACPI table is enabledZheng Bao
In ./include/device/device.h, the struct device_operations is defined as below. ------------------------------------ #if CONFIG(HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(const struct device *dev); void (*acpi_inject_dsdt)(const struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); #endif ------------------------------------ So we also need to add the same #if in the C source. Change-Id: I488eceacb260ebe091495cdc3448c931cc4a1ae3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki
Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27mb/google/dedede/var/sasukette: Generate SPD ID for supported memory partschenzanxi
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: K4U6E3S4AA-MGCR BUG=None TEST=Build the sasukette board. Change-Id: I57c9d22ae655032120f19add98ef454853428af5 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-01-27ACPI: Separate device_nvs_tKyösti Mälkki
Remove typedef device_nvs_t and move struct device_nvs outside of global_nvs. Also remove padding and the reserve for chromeos_acpi_t. Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-27src/device: Don't die() on vBIOS errorsMartin Roth
Systems can boot to the OS without a display. Don't kill the boot process based on a vBIOS error, instead just display a warning. If the issue is actually fatal for some reason, it's going to die at some point anyway. BUG=b:175843172 TEST=Boot morphius to OS without a display BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7d261321cdbe423dd754f6a354e5f50b53563fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-27soc/amd/common: Notify SMU of AC/DC state upon resumeMarshall Dawson
As a result of S3 resume, call ALIB function 1 to report the current AC/DC state. BUG=177377069 TEST=Verify printf is called during resume on Morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I3e52b0625c1222f10ea27568d5431328131a26a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27mb/clevo: Drop redundant `select HAVE_SMI_HANDLER`Angel Pons
Already selected from SoC Kconfig. Change-Id: I131f435ab0a30e33a70773a99c60284f8b9c82c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-27soc/amd/common/block/smbus: remove stale commentFelix Held
The comment doesn't apply to Stoneyridge, Picasso and Cezanne which are the only SoCs selecting SOC_AMD_COMMON_BLOCK_SMBUS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9024de9d3731a0bc64365f959142bf657a53e193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-26mb/kontron/ktqm77: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I7ba4625075fd3c27092d854903baf140521c8f7b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/asus/a88xm-e: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I8887b869e9ed809f7861b810c2fb994fa2ee062e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/asus/f2a85-m: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I3a5ef0987f2e03e07f1de2b3b10d65dde3827c70 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/asus/am1i-a: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I856494c634c8c932faa7840b0fd0a35663f4de57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46157 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26mb/bap/ode_e20XX: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I07705aed2f41cd0d2a7f4b980046995f44395f07 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/asus/p2b: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: Ib07e4147f7f1b90f721be147d48ed12ae793c4fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46159 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26mb/lenovo/t60: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: Iea2c0600d696f9da6774affdc33d9c50d5cf2c95 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/kontron/986lcd-m: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I2ef51c0348e76cb34e118ed207de88cc753f8fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/gigabyte/ga-945gcm-s2l: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Generated 'Build/dsdt.dsl' are identical. Change-Id: Ic01ca9b58fe948fe5ffbc9e80ea4bae91fb6d581 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/msi/ms7721: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are same. Change-Id: Iaf26af76935dc8cd9642f047e833f0e8b14e6931 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46209 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26mb/roda/rk9: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl are identical. Change-Id: I3cfa9d3a199a33ac8faddf4dbc1eed0df8703835 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/roda/rv11: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are identical. Change-Id: Id12c20dbe949c4badfe07578c6d202cd4cfb8191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46211 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26mb/google/stout: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I1ceb2abdd2562c145b01db7307d817c858d6b978 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26soc/intel/braswell/romstage/romstage.c: Use __func__Elyes HAOUAS
Change-Id: I07d36fb9b499e64eaba8829073c040792a2fee6e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26device/pci_device.c: Use __func__Elyes HAOUAS
Change-Id: Ia6c7de99164682dcbcc375969403d2bfb9675f3c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26arch/x86/car.ld: Fix up blob reserved regionsAngel Pons
Drop duplicated assignment that rewound `.` back, and broke platforms using MRC.bin and DCACHE_RAM_MRC_VAR_SIZE. Tested on out-of-tree Acer E5-573 (Broadwell), fixes booting. Also tested on Asrock B85M Pro4 (Haswell), also fixes booting. Change-Id: I3f0153f776c07acf7cf92808b677b118c60507c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49909 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26cpu/intel/common/fsb.c: Add Broadwell CPUID modelsAngel Pons
Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for both the traditional and ULT variants of Broadwell, because the CPU driver for Haswell already contains CPUIDs for both Broadwell types. Without this patch, Broadwell CPUs would hang when trying to print the first console log message, but only if flashconsole was not enabled. This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell CPUIDs and microcode) and went unnoticed until now because the tests were done with flashconsole enabled, which somehow boots properly even though the console time tracking would not work (depends on TSC). Tested on out-of-tree Acer E5-573, fixes booting without flashconsole. Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26soc/amd: Add an option to select if SOC supports ESPI sub decodeZheng Bao
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only Picasso need this option. Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-26mb/google/brya: Add memory DQ mapEric Lai
Add memory DQ map based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26mb/google/zork/Kconfig.name: remove double space in board variant namesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-26mb/ocp/deltalake: Replace space with underscore in Locator stringJohnny Lin
Per Facebook BIOS requirements 'Locator' field should not have any space between words. Tested=On OCP Delta Lake, dmidecode -t 17 to verify. Change-Id: I2f6f1b2590c55d6da4ca32aef2f50eb332f441dc Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-26mb/google/volteer/var/voema: Add camera ACPI configurationDavid Wu
Add camera ACPI configuration for Voema BUG=b:169551066 TEST=Build and boot Voema. Start camera app and able to capture images. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jim Lai <jim.lai@intel.com>
2021-01-26ocp/deltalake: Set C-State configMarc Jones
Set the supported C-State to C1 and C6. This matches the states in CPUID(5). Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26soc/intel/xeon_sp/acpi.c: Add ACPI C-State tableMarc Jones
Add the soc ACPI _CST table. The table may be customized to support the different state combinations and set by the mainboard config. Tested on deltalake with acpi_idle driver. Note, intel_idle may not use ACPI _CST table. Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2021-01-26soc/intel: Move c-state resource defineMarc Jones
De-duplicate the MWAIT_RES define. Move it to intel/common/block. Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26sb,soc/intel: Refactor power_on_after_fail optionKyösti Mälkki
It's only necessary to call get_option() with SLP_TYP S5. Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26cpu/x86/smm: Remove unused APMC for C-state and P-stateKyösti Mälkki
Change-Id: I7a3a1b63c0ef14b1e24ecce2df66f7970e5eb669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-26soc/amd: Refactor some ACPI S3 callsKyösti Mälkki
Do not pass ACPI S3 state as a parameter, by locally calling acpi_is_wakeup_s3() compiler has better chance for optimizing HAVE_ACPI_RESUME=n case. Test for acpi_s3_allowed() is already included in the implementation of acpi_is_wakeup_s3() and is removed as redunandant. For ramstage, acpi_is_wakeup_s3() evaluates to romstage_handoff_if_resume(). Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25mb/google/auron: Use `get_gpios` functionAngel Pons
Change-Id: I91424a45ae67186987630b7686102f467f57e7ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-25soc/amd/picasso: Change GPIO _HID to AMDI0030Raul E Rangel
This matches the _HID used in the picasso UEFI bios. BUG=none BRANCH=zork TEST=boot linux and verify peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd/picasso/acpi: Change I2C _HID to AMDI0010Raul E Rangel
This is the new _HID that was used for Raven. It matches the _HID used by the picasso UEFI bios. This does change the fixed clock used by linux from 133 MHz to 150 MHz. BUG=none BRANCH=zork TEST=boot linux and verify touch screen and touchpad still function Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd/picasso/acpi: Change UART _HID to AMDI0020Raul E Rangel
This is the new _HID that was used for Raven. It matches the _HID used by the picasso UEFI bios. BUG=none BRANCH=zork TEST=boot linux and verify UART still works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/intel/denverton_ns: Drop unused `pattrs.h`Angel Pons
Change-Id: I78ff11a56b38c4bc4f4f00115de1af4b73d4448c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-25soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh
This change uses the newly added meminit block driver and updates ADL SoC and mainboard code accordingly. BUG=b:172978729 Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-25soc/amd/picasso: Use makefile variable to locate UCODEZheng Bao
Change the hardcoded location of microcode patches to using FIRMWARE_LOCATION. Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/common: Refactor ACPI wake sourceKyösti Mälkki
Change-Id: I5cb65e131bf2a35c4305ea971812d9799b964c4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49837 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd: Refactor ACPI power state and ELOGKyösti Mälkki
Change-Id: Ib7423c8d80355871393c377ebaffdfe2846d8852 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25sb,soc/intel: Remove no-op APMC for C-state and P-stateKyösti Mälkki
Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25sb/intel/common: Change some SMI loggingKyösti Mälkki
Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25cpu/x86/smm: Use common APMC loggingKyösti Mälkki
Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25mb/google/dedede/var/drawcia: Add support to handle pen detectionWisley Chen
For board version 6 afterward, it will have external pull-up for GPP_C12, and remove internal pull-up. BUG=b:177618684 TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I503873afb48384168dcd8a822c7246655898356e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-01-25mb/google/kukui: Add panel for Katsuchenzanxi
Declare the following panel for Katsu: - BOE_TV105WUM_NW0 - STA_2081101QFH032011_53G BUG=b:176523929 TEST=build Katsu image passed BRANCH=kukui Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-25mb/google/zork: adjust the eDP panel power sequenceChris Wang
set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight. BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-25soc/amd/picasso: Add UPDs for support eDP power sequence adjustChris Wang
Add UPDs for eDP power sequence adjust all pwr sequence numbers below are in uint of 4ms. BUG=b:171269338 TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on dalboz Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/picasso: Add UPDs for support eDP power sequence adjustChris Wang
Add UPDs for eDP power sequence adjust. BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-25mb/google/zork: add eDP tuning parameter to fix the eDP noiseChris Wang
needs to adjust the eDP phy setting to fix the eDP noise for WWAN. DP_VS_LEVEL0_PREEMPH_LEVEL0, = 0x00 (0.4v 0db) swing 0, pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004B COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ibe720e26d2257e05a989eaa1fd85d542005cf6a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48734 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/picasso: Set UPDs for tuning eDP phyChris Wang
Add UPDs for edp phy tuning adjust. BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I389bc4b5726f70bb1edfd858dba1c575cf68050b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-25nb/intel/ironlake: Drop constant parameterAngel Pons
All callsites of `rmw_1d0` use the same `flag` value. Change-Id: I84fab5d3fd270ce684cd6ca892c213b0d8610283 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-25mb/google/auron: Convert to ASL 2.0 syntaxElyes HAOUAS
Built google/auron (Lulu) provides identical 'dsdt.dsl' files. Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-25nb/intel/sandybridge: Only run DMI recipe on Ivy BridgeAngel Pons
Reference code does not run any DMI recipe for Sandy Bridge. Create a helper function and exit early for Sandy Bridge. The CPUID value will be used in a follow-up, since DMI setup has stepping-specific steps. Change-Id: I5d7afb1ef516f447b4988dd5c2f0295771d5888e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48413 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25nb/intel/sandybridge: Correct late DMI init sequenceAngel Pons
Based on reference code, update the DMI ASPM setup steps. Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48536 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25mb/libretrend/Kconfig: Remove duplicated stringElyes HAOUAS
Change-Id: Iab19538e1f5a74b714cb2a34855d9717315b9018 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-25mb/51nb/Kconfig: Remove duplicated stringElyes HAOUAS
Change-Id: Ib184dbfef05608bbf18d49fee5cbc9dd12ed6751 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49883 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25src/lib/: Remove "this file is part of" lineElyes HAOUAS
Change-Id: I9031dad52581e77aa56014b1fede884f2cdeb6de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49882 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroringMichael Niewöhner
Drop the old, redundant code for mirroring LPC registers to DMI and make use of the new common code. Select the new Kconfig option for LPC DMI mirroring by the option SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig directly. APL, even though it's younger than SPT, does not need mirroring. Test: Set LGMR address by calling `lpc_open_mmio_window` and check that both the PCI cfg and DMI LGMR register get written correctly. Tested successfully on clevo/cml-u. Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-25soc/intel/lpc_lib: mirror LPC registers to DMI when requiredMichael Niewöhner
Starting with SPT, LPC registers IOD, IOE, LGIR* and LGMR need to be mirrored to their corresponding DMI registers. Add the required writes to DMI registers, where the PCI config registers get written. This is already done in soc code for IOD, IOE and LGIR* by mirroring the registers later, during PCH init. Also the code mostly matches accross the platforms. This common implementation will avoid delayed mirroring of the registers and also deduplicate the code. This change also adds a new Kconfig that will be selected by platforms requiring mirroring of LPC IO/MMIO registers to their corresponding DMI registers. For making use of this common code, the redundant soc code needs to be dropped and the newly introduced Kconfig option has to be selected. This is done in the follow-up change. Change-Id: I39f3bf4c486a1bbc112b2b453381de6da4bbac4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-25mb/google/dedede/var/boten: Add custom SAR values for BotenKevin Chang
Add Boten customized SAR table. BUG=b:175931508 BRANCH=dedede TEST=build and test no Boten Change-Id: I3b00f56c8b890979cbf2155c97a3a064d8b0ba1a Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-25mb/google/dedede/var/magolor: Enable EC keyboard backlightTim Chen
BUG=b:177288782 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I98f741da4a22494883939c4efe7960c66e71c6a7 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-25drivers/intel/fsp2_0/header_display.c: Correct component_attribute checkBenjamin Doron
According to FSP_INFO_HEADER structure in FSP EAS v2.0-v2.2, BIT1 indicates an "official" build. Change-Id: I94df6050a1ad756bbeff60cda0ebac76ae5f8249 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25mb/google/dedede/var/sasuke: Enable bluetooth deviceSeunghwan Kim
"usb2_ports[7]" for internal bluetooth device was configured as 'USB2_PORT_EMPTY' mistakenly in previous patch, so we need to enable it again. BUG=None BRANCH=firmware-dedede-13606.B TEST=Built and verified BT device existence with lsusb Change-Id: Id2900152e23bbc2f454d064dc86a9e45e934ea0f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25trogdor: Explicitly initialize display pins in bootblockJulius Werner
This patch adds explicit initializations for the remaining named display (power) control GPIOs to the bootblock GPIO init code. These pins are usually mapped to pins that are already configured to pull-downs on power-on reset so this wasn't really required, but we have already moved them around so often that you never know when EEs might one day move them to a pin with a different power-on reset configuration, so it's better to be explicit. In one particular case, GPIO(67) (used by CoachZ rev1+ but not by anything else for the EN_PP3300_DX_EDP pin) is not actually a pull-down on boot, even though that is claimed by the datasheet. This is likely due to the fact that it can serve as the SPI_HOLD pin for the boot flash QSPI bus, so even though our board's boot flash doesn't really use that pin, it seems that the boot ROM still configures it as such. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I533baa962d2dfc87cfa510f442ed2e8912e0e5b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: mturney mturney <mturney@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-01-25arm64/armv8: Set ARCH_ARMV8_EXTENSION depend on ARCH_ARM64Elyes HAOUAS
This will remove "ARCH_ARMV8_EXTENSION=0" from ".config" when unneeded. Change-Id: Idd4ad67fb4a3efdb0864803f87c6b5f508fb4364 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-25soc/intel/xeon_sp/cpx: Fix loading MCU on APsArthur Heymans
Commit 393992f (cpu/mp_init: Fix microcode lock) fixed the semantics of parallel loading microcode updates. So now '*parallel = 1' really means loading MCU in parallel, which seems to fail inconsistently on around 10% of the APs. Change-Id: I755dd302abbb58537d840852e8e290bea282a674 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49671 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/common/acpi: Add _UID for PNP0C02 devicesRaul E Rangel
When MAINBOARD_HAS_SPEAKER is false, the SPKR gets _HID PNP0C02. This conflicts with the LDRC device. PNP0C02 is also used other places in the picasso code base, so I chose a random _UID for each device. The _UIDs are unique in the code base so it's easy to search for duplicates. BUG=b:175146875 TEST=Boot trembyle to linux Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01be41515e011293e90a6b42b8e34de8ec3ffc18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 21:23:18 +0000