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2011-01-27Add a new CMOS variable which triggers activation of thePatrick Georgi
LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the variable reset, it's not. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27Trivial. Re-indent the code.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27Set the phy via weak function.Zheng Bao
As Rudolf called. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27oops. this is weird. CAR addresses should be specified in the socket and not inStefan Reinauer
the board. I thought we did this ages ago. Also push CAR BASE further down so it won't conflict with a 32mbit flash part. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-25Set the SB800 SATA PHY correctly.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-24This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue.Josef Kellermann
Signed-off-by: Josef Kellermann <Joseph.Kellermann@heitec.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-24Change fadt revision back to 3.Zheng Bao
The AcpiPmaCntBlk have to be set. Further research is needed to find out why. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21... And fix the other compile time issues in cmos_layout.bin supportPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21Make YABEL warnings-are-errors safePatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21Typo. s,CMOS_COMPONENT,CBFS_COMPONENT,.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21Now bimini can boot linux to login.Zheng Bao
Note: 1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the smp_write_config_table will run. Then intr_data will be written into 0xC00/0xC01. 2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0). The pci_locate_device will cause the system crash. 3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why? 4. early_setup.c: pmio 0x65 has change its meaning. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21push ts5300 rom size to 1MB. In fact the flash part on thatStefan Reinauer
board is 2MB and the entry point is somewhere in the middle. quite weird setup http://www.embeddedarm.com/products/board-detail.php?product=TS-5300 We should probably wipe the board from the tree. It will not work anyways with current coreboot and the architecture is kind of obscure. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20Remove the code for debugging.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20S3 feanture of SB800. Compiliant with SB700.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20Move some board specific functions to sb800.h.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20Features of Bimini board:Zheng Bao
RS785 SB800 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20This sb800 code is derived from sb700.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20For Cx, each ChipSel need to be sent MR command.Zheng Bao
After this patch, tilapia can run in higher memory frequency. To test the high frequency, dont forget to change the freq limit in mcti_d.c: static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { pDCTstat->PresetmaxFreq = 800; } Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19Add a GX2 Kconfig option to choose the framebuffer size.Nils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19Revert r5902 to make code more readable again. At least three people like toStefan Reinauer
have this go away again. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Kevin O'Connor <kevin@koconnor.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor
cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn. This patch also adds a MTRRphysMaskValid bit definition. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19The cn700.c code references mainboard_interrupt_handlers() which isn'tKevin O'Connor
defined if VGA_ROM_RUN is off. Define a dummy implementation of that function for this case. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18Report if cmos_layout.bin can't be found when it should.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18Move option table (cmos.layout's binary representation)Patrick Georgi
to CBFS and adapt coreboot to use it. Comments by Stefan and Mathias taken into account (except for the build time failure if the table is missing when it should exist and the "memory leak" in build_opt_tbl) Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18remove the code which is not ready to release.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18remove the code which is not ready to release.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18remove the code which is not ready to release.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18remove the code which is not ready to release.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-17The code is tested on my board with register DIMMs. More tests need to beZheng Bao
done. Please send the testing report. Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set to a higher limit, otherwise the frequnce will be set as 400MHz. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16Ooops lets see if this extra comment removal fixes this.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16Trivial, cleanup of GPIO comments.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14Disable CMOS recovery code for ROMCC boards as the CBFS code used forPatrick Georgi
that feature is not ROMCC compatible. Fixes build errors introduced in r6253. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14Improved GPIO setup for roda/rk886ex, and some documentationPatrick Georgi
on what the GPIOs are used for. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14Allow coreboot to initialize CMOS if checksum is invalid.Patrick Georgi
If a file "cmos.default", type "cmos default"(0xaa) is in CBFS, a wrong checksum leads to coreboot rewriting the first 128 bytes (except for clock data) with the data in cmos.default, then reboots the system so every component of coreboot works with the same set of values. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13Default to CRT on Kontron/986lcd-m. "default display" doesn't alwaysPatrick Georgi
select the right output device. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13Improve compatibility of YABEL with real-world VGABIOSesPatrick Georgi
Some of them do weird things to the option rom region (mapping registers there or so) which failed as we handled these memory region in emulation. As they were copied back to real memory after the emulation was done, we can just as well use real memory directly for these regions. This affects IVT, BDA, and option ROM space. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-12drop unused filesStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-11change a readable way to fix SB800 CIMX "multi-character constant warning".Kerry She
by using 'Int32FromChar' macro, instead of the ASCII code. Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06Various Nokia IP530 fixes.Marc Bertens
- Correct default ROM image size for this board (512KB is correct). - devicetree.cb: Add AUX I/O config (mainly GPIO settings). This allows you to control the LEDs in the front panel and JP900/JP901 can be read. - irq_tables.c: Rework PIRQ table to make more onboard devices work. Also, avoid IRQ9. - mainboard.c: Drop unneeded functions, everything is done in devicetree.cb. Signed-off-by: Marc Bertens <mbertens@xs4all.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06Fix some settings fo AMD MCT. It is based on BIOS test suite.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05uart_init is only used in romstage.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05move single options out of main menu and remove stray "options"Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04MCP55: Cosmetic fixes, switch to u8 et al.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04CK804: Cosmetic fixes, switch to u8 et al.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04Trivial:Kerry She
add missed CIMx file to romstage. in order to link them into romstage, move all CIMx table to .rodata section. Run dos2unix on Makefile.inc, which is not upstream CIMx code Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell checkKerry She
Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD SB800: Drop component prefix from filenames.Uwe Hermann
We did the same with other chipsets in r6150. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD Bimini: Use mptable_init() in mptable.c.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD Bimini: Small fixes, and updates to recent trunk conventions.Uwe Hermann
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed to HAVE_DEBUG_CAR in r5898. - Move QRANK_DIMM_SUPPORT to Kconfig, see r6028. - Drop obsolete/unused COMPRESS, see r6145. - Drop obsolete SET_NB_CFG_54, see r6086. - Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077. Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it. - Rename some GENERATE_* options to HAVE_*, see r6027. - Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151. - Drop ACPI_SSDTX_NUM, the global default is 0 already. - Random whitespace and coding style fixes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD Bimini: Drop duplicate ASL files as we did for other boards.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01Add support for the AMD Bimini eval mainboard.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01Add AMD SB800 southbridge support via cimx_wrapper.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01Add AMD SB800 southbridge CIMx code.Kerry She
The main CIMx code is in a src/vendorcode directory and should not be changed with regard to coding style etc. in order to remain easily syncable with the "upstream" AMD code. Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-31Add RS785(RS880) support. Just few pci_ids.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge codeNils Jacobs
and fix CIS mode comments. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30Use die() to assure the processor can't wake up from an interrupt.Nils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30Per default, use SeaBIOS payload instead of no payload.Stefan Reinauer
Add choice to use stable or master version of seabios repository Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)Nils Jacobs
to FG (FooGlue). As the GX2 has no VIP port. -Change the Memmory setup MSR register names so they correspond better to the databook. (Part1) This is less confusing for beginners. -Add a MSR printing function to northbridge.c like in the Geode LX code. -Remove the AES register names.(GX2 has no AES registers) -Delete some unused code. -Clean up GX2 northbridge code to match Geode LX code. -Add missing copyright header to northbridge.c. -Move hardcoded IRQ defining from northbridge.c to irq_tables.c . Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29fix i810 boards with ram init debugging disabled.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29-Clean up some comments.Nils Jacobs
-Remove some white spaces. -Remove some leading zeros. -Fix a typo in LX code. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27proper printk handling in src/northbridge/intel/i82810/raminit.cStefan Reinauer
and drop some romcc relics in 440bx code too Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27__PRE_RAM__ is defined by the makefileStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27dump_spd_registers() is only defined when ram init debugging is on.Stefan Reinauer
Most boards unconditionally call this. Fix it in header file instead of each single romstage.c Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27Fix most CONFIG_DEBUG_RAM_SETUP issues. Stefan Reinauer
The intel/xe7501devkit is still broken, I think the (romcc) image is too big to fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27Intel SCH: make state machine binary selection available in Kconfig for now.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26All the values should stay untouched or be set automatically by the resourceStefan Reinauer
allocator. If that does not work out, they should be set in the code. Setting them in Kconfig is the worst possible thing to do. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Random fixes for TI pci1x2x / Nokia IP530 / others.Uwe Hermann
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c: - Fix SMSC FDC37B787 name (was a typo). - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either. - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/. - All of these are confirmed by Marc Bertens on IRC. - Fix a few CHIP_NAME HP board names. - Random whitespace and coding-style fixes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Move Geode GX2 UMA video memory size to KconfigNils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Remove dead and unused Geode GX2 codeNils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Replace Geode GX2 MSR addresses for GLCP on GLIU1 with namesNils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Clean up Geode GX2 comments, whitespace and coding style. Trivial.Nils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-25Nokia IP530: Add missing "select SDRAMPWR_4DIMM".Uwe Hermann
This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one). Thanks Marc Bertens <mbertens@xs4all.nl> for bringing up the issue and for the success report for this fix on IRC. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-23Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk().Keith Hui
It's a good thing to use printk() instead of print_*() anyway on 440BX (and other chipsets which have been converted to CAR). Build tested and boot-tested on ASUS P2B-LS. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19The same mechanisms are used for normal and fallback images. Stefan Reinauer
Hence drop the FALLBACK_ prefix Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19ASUS M2N-E: Enable PCI-E x16 slot.Uwe Hermann
Simple devicetree.cb fix, tested on hardware using a PCI-E x16 graphics card. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18SMM on AMD K8 Part 2/2Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18Fix a few whitespace and coding style issues.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18A couple of Poulsbo fixes:Patrick Georgi
- Don't include cmc.bin to the build. It's required, but we don't ship it - mptable's API changes a bit. Adapt. - Fix ACPI for new iasl versions with improved code validation Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 boardPatrick Georgi
which uses it. Compiles, but not boot tested lately. Many things missing (eg. SMM support, proper ACPI, ...) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17Remove some more unused/incorrect hda_verb.h files.Uwe Hermann
As discussed on the mailing list at http://www.coreboot.org/pipermail/coreboot/2010-December/062393.html http://www.coreboot.org/pipermail/coreboot/2010-December/062510.html Someone who owns these boards should create correct files at some point. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17fix the tree again. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17add license headers to some trivial files and pc87427.hStefan Reinauer
Mostly done according to initial file creator. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17drop one more version of doing serial uart output differently.Stefan Reinauer
coreboot made it kind of complicated to print a character on serial. Not quite as complicated as UEFI, but too much for a good design. Fix it. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17guard against the case that CONFIG_WAIT_BEFORE_CPUS_INIT is not defined at all.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16drop unused code in div64.hStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16print what make is doing (CBFS call)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16don't hardcode CONFIG_PC80_SYSTEMStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16- Fix shortcoming in Kconfig when handling multiple "choice"sStefan Reinauer
- move some variables where they belong Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16fix according to coding guidelinesStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Add TINY_BOOTBLOCK support for the SiS966 southbridge.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Get mptable OEM/product ID from kconfig variables.Uwe Hermann
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Add support for cbfs-files-y to the build system.Patrick Georgi
That variable allows chipset components to add files to the CBFS image, for details see http://www.coreboot.org/pipermail/coreboot/2010-December/062483.html Compared to the patch in that mail this commit improves dependency tracking a bit. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-15Build fix.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-15Cleanup up HD audio codec / hda_verb.h files.Uwe Hermann
Most of the current hda_verb.h files are identical (same MD5 sum) and are intended for a specific MCP55 board with the Realtek ALC880 audio codec, which has the vendor/device ID of 0x10ec0880. They were splitted out from the MCP55 southbridge code and put into board dirs a long time ago (which is correct, as those settings are indeed board-specific), but they were never adapted to those boards. Here's the table of which codec is soldered onto which board, based on checking the vendor website board spec pages, and the board manuals: - GIGABYTE GA-M57SLI-S4: Realtek ALC883 - MSI MS-7260: Realtek ALC883 - MSI MS-9652: Realtek ALC888 - MSI MS-9282: Server board, doesn't have audio at all - Tyan S2912: Server board, doesn't have audio at all - All Supermicro boards: Server boards, don't have audio at all - NVIDIA l1_2pvv: No public info to be found, but I assume this was the original MCP55 eval board for the port and it's probably has the Realtek ALC880 codec used in the original hda_verb.h. These are the codec vendor device/IDs involved: Realtek ALC880: 0x10ec0880 Realtek ALC883: 0x10ec0883 Realtek ALC888: 0x10ec0888 The following files are marked as incorrect / TODO, as the ID of the codec doesn't match and thus will never get actually used (you'll see "HDA: no verb!" or similar in the coreboot logs). Even if the ID matched, the rest of the table would be incorrect anyway because the values are highly board-specific. ./src/mainboard/gigabyte/m57sli/hda_verb.h ./src/mainboard/msi/ms9652_fam10/hda_verb.h ./src/mainboard/msi/ms9282/hda_verb.h The following files can be safely dropped as these are server boards and don't have HD audio (or other audio) at all: ./src/mainboard/supermicro/h8dmr/hda_verb.h ./src/mainboard/supermicro/h8qme_fam10/hda_verb.h ./src/mainboard/supermicro/h8dme/hda_verb.h ./src/mainboard/supermicro/h8dmr_fam10/hda_verb.h ./src/mainboard/tyan/s2912/hda_verb.h ./src/mainboard/tyan/s2912_fam10/hda_verb.h The following two are correct and can stay: ./src/mainboard/nvidia/l1_2pvv/hda_verb.h ./src/mainboard/getac/p470/hda_verb.h Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-14Set the ROMSIZE as 4MB.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13no leading zeroes.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13Attached patch implements the memory speed reductions (and 2T/1T clock ↵Rudolf Marek
logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs. The patch does not implement support for three dimm configurations supported from revE. On the other hand it should improve greatly memory stability across the 939 platform. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13This patch just turns on the ACPI resume.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 22:34:51 +0000