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2022-02-28device/pci_device: Fix PCIe bridge detectionNico Huber
PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(), it's our virtual `domain` device. Expecting a PCI device above bus 0 resulted in undefined behavior for all boards with PCI. Only boards with a PCI device 00:00.0 that looked like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake). Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171 Signed-off-by: Nico Huber <nico.h@gmx.de> Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe) Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28mb/google/brya/var/kano: Add wifi sar tableDavid Wu
1. Add wifi sar table for kano 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:214393458 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-02-28sb/intel/lynxpoint: Fix up commentAngel Pons
Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-28mb/google/dedede/var/pirika: Add Wifi SAR for pasaraFrank Chu
Add wifi sar for pasara BUG=b:216411442 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: Enable USB controllers in devicetreeJon Murphy
BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable internal graphicsJon Murphy
BUG=b:214416935 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-26mb/google/skyrim: Enable console UARTJon Murphy
BUG=b:214414501 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: Set up FW_CONFIGJon Murphy
BUG=b:214415048 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable eSPI SCI eventsJon Murphy
Enable ESPI SCI events BUG=b:214416630 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Add smihandlerJon Murphy
BUG=b:214415408 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable Chrome ECJon Murphy
BUG=b:214413613 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable variants for SkyrimJon Murphy
BUG=b:214414033 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: CONFIG_CHROMEOSJon Murphy
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable ACPI tablesJon Murphy
Add GPIO initialization and ACPI generation for tables BUG=b:214415303 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW SeqSubrata Banik
This fixes no practical problem, especially for coreboot where only one process should access the SPI controller. It makes the code look more spec compliant. As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. Software must initiate the next SPI transaction when this bit is 0. Add non-blocking mechanism with `5sec` timeout to report back error if current SPI transaction is failing due to on-going SPI access. BUG=b:215255210 TEST=Able to boot brya and verified SPI read/write is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-26soc/amd/common/psp_verstage: Add missing post codes on S0i3 resumeRaul E Rangel
We print these out in the normal flow, so lets add them for S0i3 resume as well. BUG=b:221231786 TEST=Perform suspend/resume cycle on guybrush and verify we get the new POST codes. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinkingRaul E Rangel
This feature was never used. Let's remove it to keep things simple. BUG=221231786 TEST=Boot test guybrush and morphius and verify transfer buffer is correctly passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-25mb/google/brask: Update PCH power cycle related durationsZhuohao Lee
The power rails discharge time of brask has been measured, the longest discharge time of the power rails are smaller than 150ms so it is safe to set the pwr_cyc_dur to 1 second. Since the brask is derived from the brya, we could apply the same setting from the brya. The setting is copied from commit dee834aa. BUG=b:214454454 BRANCH=firmware-brya-14505.B TEST=`test_that firmware_ECPowerButton` passed. Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25mb/intel/adlrvp: Add support for MAX98373 codecUsha P
- Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-25sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macroElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25nb/intel/ironlake: Fix sending HECI messagesArthur Heymans
This code only worked when the payload (a packed struct) was 4 byte aligned. With gcc11 this happens to not be the case. Change-Id: I5bb4ca4b27f8554208b12da177c51091ea6a108f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA
coreboot uses port index which is 0 based for all PCIe root ports. In case of PCIe remapping logic, coreboot reads LCAP register from PCIe configuration space which contains port number (mostly 1 based). This assumption might not be true for all the ports in coreboot. TBT's LCAP registers are returning port index which are based on 2. coreboot's PCIe remapping logic returns port index based on index 1. This patch adds variable to pcie_rp_config to pass lcap_port_base to the pcie remapping function, so coreboot can map any n-based LCAP encoding to 0-based indexing scheme. This patch updates correct lcap_port_base variable for all PCIe root ports for all SOCs, so that function returns correct 0-based index from LCAP port number. BUG=b:210933428 BRANCH=None TEST=Check if code compiles for all ADL boards Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic numberFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25soc/intel/denverton/include/iomap: drop unused DEFAULT_HPET_ADDR defineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie92bd54b072d545944b3d0251e9727ce493bb864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25sb/intel/common/hpet: use HPET_BASE_ADDRESS definitionFelix Held
Use the definition from arch/x86 instead of a local redefinition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If172cde267062a8e759a9670ac93f4e74e8c94d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-25soc/intel/baytrail,braswell/include/iomap: drop unused HPET_BASE_SIZEFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I875916488a99af768d087691549a93f6fd5169ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25arch/x86/Kconfig: add HPET_MIN_TICKSFelix Held
Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in acpi/acpi.c, so define this option in arch/x86/Kconfig to have it defined in all cases where the function that ends up using this information gets called. Since we now have the type information for this Kconfig option in a central place, it can be dropped from the Kconfig file of the Intel southbridges that change the default value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25acpi/acpi: use read32p instead of pointer dereferencingFelix Held
Using read32p to get the contents of the first 4 bytes of the HPET MMIO region instead of a pointer dereference should clarify what's done in that piece of code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iecf5452c63635666d7d6b17e07a1bc6aa52e72fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62297 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/google/guybrush: enable coreboot to request spl fuseJason Glenesk
Enable guybrush based platforms to send fuse spl command to PSP when required. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Confirm that PSP indicates fusing is required, and confirm coreboot sends command. Fusing is required when the image is built with an SPL table requiring newer minimum versions. A message indicating fusing was requested will appear in the serial log. "PSP: Fuse SPL requested" Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-25mb/google/volteer/var/collis: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:192535692 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I30fa886a39bd7082442a3a2b95fdf2d2b84ddd1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-25herobrine: Add Villager variantShelley Chen
BUG=b:218415722 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-25mb/google/skyrim: First pass GPIO configuriation for SkyrimJon Murphy
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/amd/chausie/devicetree: add i2c_scl_resetFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/amd/chausie/devicetree: enable I2C controllersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24mb/google/brya/var/taeko: Add GL9750 SD card reader supportKevin Chang
Add GL9750 SD card reader support. BUG=b:220987566 TEST=Build FW and check device function normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I8f6ca45a320d34dfd820ef0b6e0d3163fab26027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24mb/google/skyrim: Add stubs to configure GPIOsJon Murphy
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24soc/apollolake: Allow configuring individual USB ports on GLKSean Rhodes
Allow configuring the limited fields that FSP-S provides. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-24treewide: Write minor version at acpi_create_fadt() functionElyes Haouas
When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0". So set it correctly for treewide. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Lance Zhao
2022-02-24mb/google/brya: Add SPD configs for CrotaTerry Chen
Add a mem_parts_used.txt for Crota, containing the memory parts used in proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) BUG=b:215443524 TEST=emerge-brya coreboot Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-24nb/intel/ironlake: Clean up `jedec_read()` functionAngel Pons
Deduplicate a condition and reflow some lines. Tested on HP ProBook 6550b, still reaches TianoCore payload. Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-24nb/intel/ironlake: Fix some quickpath init magicAngel Pons
Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still reaches payload (e.g. TianoCore). Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24nb/intel/ironlake: Move out HECI remainders into southbridgeAngel Pons
Move the remaining HECI-related stuff to southbridge scope, as the HECI hardware is in the southbridge. Note that HECI BAR is now enabled a bit earlier than before, but this shouldn't matter. Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24mb/google/brya/var/vell: Corrects ACPI _PLD macro settingRobert Chen
This patch is to denote the correct side of ACPI _PLD usb C ports. +-------------------------+ | LCD | | | | | +-------------------------+ PORT_C2 | | PORT_C1 PORT_C3 | DB MB | PORT_C0 | | +-------------------------+ BUG=b:220634230 TEST=emerge-brya coreboot Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24mb/google/brya/var/anahera{4es}: Add MT53E2G32D4NQ-046 WT:C supportWisley Chen
Add new memory MT53E2G32D4NQ-046 WT:C support BUG=b:220821471 TEST=emerge-brya coreboot Change-Id: I4c21254213c2107d015adebb510612e0256ffb5c Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24mb/google/brya/var/redrix{4es}: Add MT53E2G32D4NQ-046 WT:CWisley Chen
Add new memory MT53E2G32D4NQ-046 WT:C support. BUG=b:220804962 TEST=emerge-brya coreboot Change-Id: I3353d7c119798ebb0b5ee1ea32161e54b4eec826 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24security/intel/stm: Make STM setup MP safeEugene Myers
Some processor families allow for SMM setup to be done in parallel. On processors that have this feature, the BIOS resource list becomes unusable for some processors during STM startup. This patch covers two cases: (1) The BIOS resource list becomes twice as long because the smm_relocation function is called twice - this is resolved by recreating the list on each invocation. (2) Not all processors receive the correct resource list pointer - this is resolved by having every processor execute the pointer calculation code, which is a lot faster then forcing all processors to spin lock waiting for this value to be calculated. This patch has been tested on a Purism L1UM-1X8C and Purism 15v4. Signed-off-by: Eugene Myers <cedarhouse@comcast.net> Change-Id: I7619038edc78f306bd7eb95844bd1598766f8b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2022-02-24security/intel/stm: Use correct SMBASE for SMM descriptor setupEugene Myers
Commit ea3376c (SMM module loader version 2) changedhow the SMBASE is calculated. This patch modifies setup_smm_descriptor to properly acquire the SMBASE. This patch has been tested on a Purism L1UM-1X8C and a Purism 15v4. Signed-off-by: Eugene Myers <cedarhouse@comcast.net> Change-Id: I1d62a36cdcbc20a19c42266164e612fb96f91953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61688 Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24arch/x86/Kconfig: drop HPET_ADDRESS_OVERRIDEFelix Held
Commit b433d26ef11b78dda353723ff7c8797d06f76f21 (arch/x86: Define HPET_ADDRESS_OVERRIDE) added this Kconfig option and referenced the via/cx700 chipset which has been dropped before the 4.9 release. No SoC in the current tree selects HPET_ADDRESS_OVERRIDE and all SoCs have their HPET mapped at 0xfed00000, so drop this unused and no longer needed Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4021ed6f84473c7a9223323fc8aa5d3f935d8084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62276 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24soc/amd/*/include/soc/iomap.h: rework HPET base address checkFelix Held
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't set so that the HPET_ADDRESS Kconfig option will have the right default value. Instead check if the HPET_ADDRESS Kconfig value matches the HPET_BASE_ADDRESS define in the SoC code which is the case if HPET_ADDRESS_OVERRIDE isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23cr50: Increase cr50 i2c probe timeoutRob Barnes
Turns out 200ms still isn't enough in the worst reset conditions. There's been some reports of failures at 200ms with some older cr50 versions. Let's not take any chances and bump this way up since if this fails, it prevents boot. BUG=b:213828947 BRANCH=None TEST=Reboot and suspend_stress on Nipperkin Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I5be0a80c064546fd277f66135abc9d0572df11cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-23src/mediatek: Refactor dramc_param to share more structuresXi Chen
The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To prevent code duplication, move it as well as other related structs and enums to a common header. Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-23soc/mediatek/mt8186: disable VSRAM_CORERex-BC Chen
VSRAM_CORE is not used on kingler/krabby, so we disable it. This implementation is according to chapter 3.7 in MT8186 Functional Specification. BUG=b:220071688 TEST=the rail steadily shows 0V in either S0, S3, and S5. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23drivers/mrc_cache/mrc_cache.c: Change loglevelsUwe Poeche
Since commit 7cd8ba6eda (console: Add loglevel prefix to interactive consoles) on the very first boot some errors occur because no MRC data is present in the MRC cache. This is normal because the memory training is not done yet. This patch changes the loglevel to BIOS_NOTICE which will prevent an error in the log in this case. Change-Id: I1e36590e33507515e5b9dd4eb361b3dbe165511e Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61973 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22console: Fix LOG_FAST macroMario Scheithauer
In the LOG_FAST macro, the comparison was incorrectly made with 'level' value. Correct is the comparison with 'speed'. With the wrong comparison you cannot set a lower level for console log, the highest level is always output. TEST: - Boot mc_ehl2 with console log level 5 and check output Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-22mb/gizmosphere/gizmo/OptionsIds.h: Remove extra empty lineElyes Haouas
Change-Id: I8ad968da1771004f7f5869e5434473a498edeaa2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"Elyes Haouas
Change-Id: I273e29a26cf1c1ba34b95eb11bcb59a1360371e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/lenovo/g505s: Format codeElyes Haouas
Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22sb/amd/cimx/sb800/amd_pci_int_defs.h: Fix serial IRQ INT name in commentElyes Haouas
Change-Id: If351d93c47de2ef76fb24525ff6d134b35c5f3fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22sb/amd/pi/hudson/early_setup.c: Fix typo in commentElyes Haouas
Change-Id: Ib631cdc0794dc91df27cb984d5c585e0eee4a2ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22southbridge/amd/*/*/reset.c: Reduce stylistic differencesElyes Haouas
Change-Id: I2f58098e786e9b61b0d059723c375a90559e95a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22southbridge/amd/*/*/smbus.c: Reformat code and reduce differenceElyes Haouas
Change-Id: I43644b757a5a85864162da6a35f7f2a5335f8007 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/gizmosphere/gizmo/acpi/gpe.asl: Remove extra blank lineElyes Haouas
Change-Id: I0d9b07183b06915799f221390406e930ca253a0d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/gizmosphere/gizmo/devicetree.cb: Fix typo on 'pci'Elyes Haouas
While on it, use tab for indent. Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22sb/intel/i82371eb: Constify pci_devfn_t devicesElyes Haouas
Change-Id: I9056464b36cde89d2fe88ff27531e467297bed0b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22sb/intel/ibexpeak: Constify struct southbridge_intel_ibexpeak_configElyes Haouas
Change-Id: I096ccd0ec224b98038d290422f568666bbede43a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22src/Kconfig: Update the path to 'c_start.S' for GDB_STUB configElyes Haouas
Change-Id: Ib31defde0d4983a9418f05e0b812a7bbbe4fe2b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22mb/starlabs/labtop: Reconfigure GPIOsSean Rhodes
Reconfigure the GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I27ecf066685f2a81ac884a9f276c518544449443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Reconfigure CNVi GPIOsSean Rhodes
Reconfigure the CNVi GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Update trackpad GPIO configurationSean Rhodes
Update trackpad GPIO to avoid IRQ Storm, that causes high power consumption when idling or in S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGLSean Rhodes
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the hardware TPM can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756 Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22mb/starlabs/labtop: Don't configure ESPI GPIOsSean Rhodes
Don't configure ESPI GPIOs as the default values are correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22soc/intel/common/block/acpi: Drop duplicated 'fadt->header.revision'Elyes Haouas
The 'fadt->header.revision' is already done at src/acpi/acpi.c acpi_create_fadt(). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib9b6dc7e86ca17e0b2d374ee2c3bdf06f8b82dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62222 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22payloads/tianocore: Rework MakefileSean Rhodes
Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This sets the project directory based on the git repository name i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit ID without a branch. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02Ronak Kanabar
The headers added are generated as per FSP v3054.02. Previous FSP version was v2503_00. Changes Include: - UPD Offset Update in FspmUpd.h BUG=b:220076892 BRANCH=None TEST=Build and boot adlnrvp Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-22soc/amd/sabrina/i2c: remove TODOFelix Held
The SoC-specific I2C code and header file have been verified some time ago, but it seems that I forgot to remove the corresponding TODOs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-22treewide: Get rid of CONFIG_AZALIA_MAX_CODECSElyes Haouas
Get rid of Kconfig symbol introduced at commit 5d31dfa8 High Definition Audio Specification Revision 1.0a says, there are 15 SDIWAKE bits. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infoVarshit B Pandya
CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-22soc/amd/common/block/lpc/espi_util: use __fallthroughFelix Held
Using __fallthrough instead of a comment about the fall-through being intentional should make clang stop complaining about intended fall- through statements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-22vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependencyFelix Held
Compiling vboot_check.c depends on fmap_config.h already being generated so add this dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-02-22mb/siemens/mc_apl2: Enable PCI device for I2C bus 0Werner Zeh
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus devices (16.0, 16.1 and 16.2) have been disabled as they are not used. While coreboot can handle the case where a PCI device does not have function 0 enabled but a later one (here function 3), Linux seems to check for function 0 first and ignores the rest if function 0 is missing. So enable PCI device 16.0 in order to let Linux use 16.3 again. Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are visible and I2C attached RTC works properly. Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22include/acpi/acpi.h: Drop non-existing acpi_create_madt_lapic_nmis()Elyes Haouas
Change-Id: Ide854e5c8e2ed507548047cb6e1fad49efaffbb8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-21mb/google/volteer/var/drobit: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:204517112 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21mb/google/volteer/var/delbin: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:204523176 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21mb/google/volteer/var/copano: update default codec HID to 10EC5682FrankChu
Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:218245715 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21soc/amd/sabrina/fw.cfg: Change the instance of PMUI/D to 2Zheng Bao
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao
Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21mb/google/brya: Enable eMMC HS400 mode for nissaReka Norman
Based on the nivviks and nereid schematics, nissa is using eMMC HS400 mode, so enable this in devicetree. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByteFelix Held
Only the info about the location of the EC firmware will be stored right at the beginning of the flash, so the size can be reduced to 4kByte which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE file itself is smaller than this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21soc/intel/alderlake: Make clang static assert happyArthur Heymans
Change-Id: Ia3cd66f6b735f7430abcdba8a9323d5ee1320fd4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21drivers/intel/pmc_mux: Fix printing typeArthur Heymans
Change-Id: I1cb517323e7d609ae6624363e116e9814fc631cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21soc/intel/alderlake: Fix function pointer typeArthur Heymans
const void is not a proper return type for a function. It's the function pointer themselves that need to be const. This fixes building with clang. Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21drivers/intel/fsp2_0/hob: Remove unused variableArthur Heymans
Change-Id: Ie9f4562be9b019d8dd65d4e9040fefbb6834fa03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-21soc/intel/adl/bootblock/report_platform.c: Use the correct formatArthur Heymans
Change-Id: I54c40434f44621c4ea6564ac9c87c5b2fa083b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21ec/google/chromeec/ec_acpi.c: Cast compatible enum typesArthur Heymans
Clang complains about this. Change-Id: If7af9d5a81c1c381490c9634e3da68ff7f5edda8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21[acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in commentsElyes Haouas
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'Elyes HAOUAS
'printram(x, ...)' is already defined in 'include/device/dram/common.h' file Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-21soc/intel/denverton_ns: Add `pmc_mmio_regs` as public functionSubrata Banik
This patch adds `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=none TEST=none Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 06:55:46 +0000