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Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Instead of having PCI0's _BBN method in the DSDT that always returns 0,
use acpigen_write_BBN to generate the _BBN method that returns the first
PCI bus number in the PCI domain/host bridge.
TEST=On mandolin the _BBN method in the _SB/PCI0 scope is now in the
SSDT instead of the DSDT, but still returns 0.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8badeb0064b498d3f18217ea24bff73676913b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74992
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use amd_pci_domain_read_resources function that gets the configured MMIO
regions for the PCI root domain from the data fabric's MMIO decode
registers instead of using pci_domain_read_resources. This results in
the same IO port range being used by the allocator, but makes sure that
the allocator will only allocate non-fixed MMIO resources in the address
ranges that get decoded to the PCI root complex. In order for the PCI0
_CRS ACPI resource template to match the decoded PCI root domain MMIO
windows, use amd_pci_domain_fill_ssdt to generate the _CRS ACPI code
instead of having a mostly hard-coded _CRS method in the DSDT. This
makes sure that the OS will know about the MMIO regions it is allowed to
used.
Before this patch, only the region from TOM1 to right below
CONFIG_ECAM_MMCONF_BASE_ADDRESS was advertised as usable PCI MMIO in the
PCI0 _CRS method. Also the resource allocator didn't get any constraint
on which address ranges it can use to put the non-fixed MMIO resources.
This approach worked until now, since all address range from 0 up to
right below TOM1 was filled with either usable or reserved memory and
the allocator was allocating beginning right from TOM1, since it was
using the bottom-up allocation approach and everything below TOM1 was
already in use. The MMIO region from TOM1 to right below
CONFIG_ECAM_MMCONF_BASE_ADDRESS also matched the MMIO decode window
configured in the data fabric's MMIO decode registers, so everything
seemed to work fine. However, when either selecting
RESOURCE_ALLOCATION_TOP_DOWN or enabling above 4GB MMIO, things broke
badly. This was partially due to the allocator putting non-fixed MMIO
resources in regions that weren't decoded to the PCI root, since AMD
family 17h and 19h silicon doesn't subtractively decode PCI MMIO and the
wrong ranges the allocator used also weren't advertised in ACPI.
TEST=Even when selecting RESOURCE_ALLOCATION_TOP_DOWN that usually ends
up with a non-working system when the MMIO ranges aren't reported
correctly to the resource allocator due to the reasons descried above,
Ubuntu 22.04 LTS still boots on Mandolin both with SeaBIOS and EDK2
payload and Windows 10 boots with EDK payload. There's however an EDK2
bug that results the MMCONFIG region not being advertised in the e820
table, which causes Linux to not use the MMCONFIG and fall back to the
legacy PCI config access method. This only happens with EDK2 payload and
everything works fine when using SeaBIOS as payload. That e820 issue is
unaffected by this patch.
At the end of the data_fabric_set_mmio_np call, this is the data fabric
MMIO register configuration:
=== Data Fabric MMIO configuration registers ===
idx base limit control R W NP F-ID
0 fc000000 febfffff 93 x x 9
1 10000000000 ffffffffffff 93 x x 9
2 d0000000 f7ffffff 93 x x 9
3 fed00000 fedfffff 1093 x x x 9
4 0 ffff 90 9
5 0 ffff 90 9
6 0 ffff 90 9
7 0 ffff 90 9
The limit of the data fabric MMIO decode register 1 is configured as
0xffffffffffff although this is way beyond the addressable memory space.
add_data_fabric_mmio_regions fixes this up, so the range that gets
passed to the allocator in that case is 0x7fcffffffff which takes both
the reserved most significant address bits used for the memory
encryption and the 12GB reserved data fabric MMIO at the top of the
usable address space into account.
This results in the following domain ranges passed to the resource
allocator:
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: fc000000 size: 0 align: 0 gran: 0 limit: febfffff
DOMAIN: 0000 mem: base: 10000000000 size: 0 align: 0 gran: 0 limit: 7fcffffffff
DOMAIN: 0000 mem: base: d0000000 size: 0 align: 0 gran: 0 limit: f7ffffff
The IO resource producer region is split into two parts to not cover the
PCI config IO region resource consumer. This results in these resources
being added to the PCI0 _CRS resource template:
amd_pci_domain_fill_ssdt ACPI scope: '\_SB.PCI0'
PCI0 _CRS: adding busses [0-3f]
PCI0 _CRS: adding IO range [0-cf7]
PCI0 _CRS: adding IO range [d00-ffff]
PCI0 _CRS: adding MMIO range [fc000000-febfffff]
PCI0 _CRS: adding MMIO range [10000000000-7fcffffffff]
PCI0 _CRS: adding MMIO range [d0000000-f7ffffff]
PCI0 _CRS: adding VGA resource
Kernel version 5.15.0-43 from Ubuntu 2022.4 LTS prints this in dmesg:
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [bus 00-3f]
pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window]
pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff window]
pci_bus 0000:00: root bus resource [mem 0xfc000000-0xfebfffff window]
pci_bus 0000:00: root bus resource [mem 0x10000000000-0x7fcffffffff window]
Another noteworthy thing I wasn't aware of at first when testing ACPI
changes on Windows 10 is that a normal Windows shutdown and boot cycle
won't result in it processing the changed ACPI tables; you have to tell
it to reboot to do a proper full boot where it will process the updated
ACPI tables (and fail if it dislikes something about the ACPI tables and
bytecode).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia24930ec2a9962dd15e874e9defea441cffae9f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74712
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Generate the PCI0 _CRS ACPI resource template to tell the OS which PCI
bus numbers and IO and MMIO regions can be used for PCI devices below
_SB/PCI0. This data corresponds to what amd_pci_domain_scan_bus and
amd_pci_domain_read_resources provided to the resource allocator. This
makes sure that the PCI0 _CRS ACPI resource template matches the
constraints the resource allocator used when allocating resources.
TEST=With also the rest of the current patch train applied, the
generated _CRS resource template contains the expected PCI bus numbers
and IO and MMIO resources and both Linux and Windows boot on Mandolin.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74843
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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When an IO resource producer is generated that covers the whole IO space
from 0 to 0xffff, the length field in the word resource ACPI type would
overflow and be truncated which results in Linux not finding any usable
IO space to use for the PCI IO BARs. Instead generate a double word IO
resource producer to have all cases supported. Beware that covering all
IO ports with the IO resource producer while covering the PCI config IO
ports with a resource consumer in the same PCI root device will make
Linux a bit unhappy and it will complain due to the overlap, but still
end up doing the right thing:
acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored
The SoC code should make sure to carve out the PCI config IO ports from
the IO resource producer.
TEST=Both Ubuntu 2022.04.1 LTS and Windows 10 are ok with the IO DWord
resource producer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75613
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide amd_pci_domain_scan_bus to enumerate the PCI buses in the one
PCI root domain and amd_pci_domain_read_resources to read the MMIO
regions that the resource allocator can use to allocate the PCI MMIO
BARs in the one PCI root domain from the corresponding data fabric MMIO
decode registers. This makes sure that the allocator will only put PCI
MMIO resources in areas that are decoded to the PCIe root complex. The
current code only covers the case of a system with one PCI root where
all PCI bus numbers belong to the only PCI root, all IO ports get
decoded to the only PCI root and the MMIO regions from the data fabric
MMIO decode registers get decoded to the only PCI root. In future
patches, this will be extended to also support the multi PCI root case.
TEST=With also the rest of the current patch train applied, the resource
allocator uses the constraints on the MMIO regions and both Linux and
Windows boot on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4aada7c8a2a43145ad08d11d0a38d9cdc182b98e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74717
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In case the secure memory encryption is enabled, some of the upper
usable address bits of the host can't be used any more. Bits 11..6 in
CPUID_EBX_MEM_ENCRYPT indicate how many of the address bits are taken
away from the usable address bits in the case the secure memory
encryption is enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia810b0984972216095da2ad8f9c19e37684f2a2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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types.h provides uint32_t via a chain include.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I875e3bb096b56bbea862c9ad0e3e14e025e3298b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75622
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:285110121
TEST=boot Myst and verify the flash is recognized
Change-Id: I30aed5299f87f7cf02fe9a5569edd2b8dcf7b452
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Print the flash ID codes when find_match fails to match the flash.
BUG=b:285110121
Change-Id: I2106abfcfbd44c7d56d48ffbb43d8c76089af076
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Intel Meteor Lake SOC has a separate I/O Expander (IOE) die.
SRAM from this IOE die contains crashlog records for the IPs
of the IOE die.
This patch adds functions with empty implementation using
__weak attribute for IOE die related crashlog, changes common
data structures while maintaining backwards compatibility,
and support for filling IOE crashlog records, guarded by
SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data
function as weak because it needs SOC specific implementation.
Bug=b:262501347
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog
Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This makes sure that the resource allocator won't use those ports for
anything else.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75619
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This makes sure that the resource allocator won't use those ports for
anything else.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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To avoid magic constants in the code, add defines for the VGA MMIO
address range from 0xa0000-0xbffff.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75618
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-rex coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This commit adds a configuration option to enable RMT in the coreboot
build for the Intel Xeon SP SPR platform.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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All the DRAM module for Juniper/Willow can reuse the RAM ID in
offset 0x30 table, so change Juniper/Willow RAM table offset to 0x30
for introducing more DRAM modules.
BUG=b:284423187
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Uldren does not have PCIE device and should disable PCIE RP7 and
GPP_D7 for preventing PCIe controller not power gate in S0ix.
BUG=b:283735051
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6'
[SPEW ] PCI: 00:1c.6: enabled 0
[SPEW ] PCI: 00:1c.6: enabled 0
2. GPP_D7: iotools mmio_read32 0xfd6d0ab0
0x44000300
Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75644
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure
GOOGLE_OVIS built successfully
Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The K&D-ILI9882T panel and STA-ILI9882T share all DCS commands and EDID
information except for the manufacturer_name which has no effect to the
function of panel. Let's reuse the STA_ILI9882T struct in this case.
BUG=None
TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I510462a49d273f3d25158b25906d4c514f855cdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Based on the power sequence of the panel [1], the power on T2 sequence
VSP to VSN should be larger than 1ms, and the power off T2 sequence VSP
to VSN should be larger than 0ms. We modify the power sequence to meet
the datasheet requirement.
[1] B5 TV110C9M-LL0 Product Specification Rev.P0
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Set SSID UPD to program DID as SSID for all the on board PCIe devices
if SSID is not being overridden by CONFIG option or device tree.
BUG=b:263846223
TEST=Verify that SSID for all PCI devices is same as their respective
DIDs.
Output of lspci in the OS:
00:00.0 0600: 8086:7d02 (rev 01)
Subsystem: 8086:7d02
00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller])
Subsystem: 8086:7d45
00:04.0 1180: 8086:7d03 (rev 01)
Subsystem: 8086:7d03
00:05.0 0480: 8086:7d19 (rev 01)
Subsystem: 8086:7d19
00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode])
Subsystem: 8086:7e4d
Capabilities: [98] Subsystem: 8086:7e4d
00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode])
Subsystem: 8086:7ec4
Capabilities: [90] Subsystem: 8086:7ec4
00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode])
Subsystem: 8086:7ec6
Capabilities: [90] Subsystem: 8086:7ec6
00:0a.0 1180: 8086:7d0d (rev 01)
Subsystem: 8086:7d0d
00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI])
Subsystem: 8086:7ec0
00:0d.2 0c03: 8086:7ec2 (prog-if 40)
Subsystem: 8086:7ec2
00:0d.3 0c03: 8086:7ec3 (prog-if 40)
Subsystem: 8086:7ec3
00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI])
Subsystem: 8086:7e7d
00:14.2 0500: 8086:7e7f (rev 01)
Subsystem: 8086:7e7f
00:14.3 0280: 8086:7e40 (rev 01)
Subsystem: 8086:0094
00:15.0 0c80: 8086:7e78 (rev 01)
Subsystem: 8086:7e78
00:15.1 0c80: 8086:7e79 (rev 01)
Subsystem: 8086:7e79
00:15.3 0c80: 8086:7e7b (rev 01)
Subsystem: 8086:7e7b
00:16.0 0780: 8086:7e70 (rev 01)
Subsystem: 8086:7e70
00:19.0 0c80: 8086:7e50 (rev 01)
Subsystem: 8086:7e50
00:19.1 0c80: 8086:7e51 (rev 01)
Subsystem: 8086:7e51
00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode])
Subsystem: 8086:7e3e
Capabilities: [98] Subsystem: 8086:7e3e
00:1e.0 0780: 8086:7e25 (rev 01)
Subsystem: 8086:7e25
00:1e.3 0c80: 8086:7e30 (rev 01)
Subsystem: 8086:7e30
00:1f.0 0601: 8086:7e04 (rev 01)
Subsystem: 8086:7e04
00:1f.3 0401: 8086:7e28 (rev 01)
00:1f.5 0c80: 8086:7e23 (rev 01)
Subsystem: 8086:7e23
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Touchscreen may either use I2C1 or SPI0.
FW_CONFIG.TOUCHSCREEN is set to determine which is used.
This CL adds a probe to enable I2C1.
BUG=b:278783755
TEST=Tested on rex, confimed i2c1 is disabled when
TOUCHSCREEN != TOUCHSCREEN_I2C
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Follow 57263_FP8_MBDG_rev_0_92 Table.57 to update the alias. We
can match the schematic for now.
BUG=b:285793461
TEST=USB still works.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Id1058279fe5b0e3131608a0b9bbd708dbbde7e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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vboot code changes have eliminated the redundant call to WP the EC-RO
region as protecting RW flash implies protecting both RO and RW flash,
so the call to protect RO is redundant. google/rex currently takes
about 17 ms to lock down the EC.
Along with vboot changes, this patch drops argument to choose between
RO and RW slot to protect while calling into `vb2ex_ec_protect()`.
It ensures vb2ex_ec_protect() is explicitly meant for protecting RW
regions.
w/o this patch:
517:waiting for EC to allow higher power draw 846,196 (17,297)
w/ this patch:
517:waiting for EC to allow higher power draw 838,258 (9,719)
Additionally, update vboot submodule to upstream main to avoid the
compilation error.
Updating from commit id 35f50c3154e5:
Fix build error when compiling without -DNDEBUG
to commit id 034907b279c9db:
vboot_reference: eliminate redundant call to write protect EC-RO
Change-Id: I2974f0cb43ba800c2aaeac4876ebaa052b5ee793
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add Makefile.inc to include four LPDDR5x SPDs for the following
parts for Joxer:
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 3 (0011)
H58G56BK7BX068 4 (0100)
MT62F1G32D2DS-026 WT:B 4 (0100)
K3KL8L80CM-MGCT 4 (0100)
BUG=b:236576115
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ibdc89c882581cfe4e5978faf4c6f70d653e0813d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75610
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This adds printing content of 'manifest' file at ramstage.
It allows to learn about blobs version used to build the coreboot
binary, which is useful when investigating bugs.
Version data are stored in CBFS file, which was generated during
coreboot build. If AMD FW blobs will be manually replaced in coreboot
image, versions from CBFS file are no longer valid.
Log:
AMDFW blobs version:
type: 0x01 ver:00.3c.01.18
type: 0x08 ver:00.5a.28.00
type: 0x30 ver:2b.25.b0.10
type: 0x73 ver:00.3c.01.18
BUG=b:224780134
TEST=Tested on Skyrim device
Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74269
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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BUG=b:278783755
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74944
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code is supposed to output debug messages but is commented out, so
do the same for variables.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ief1f9d2175fe1375fe6ac4bb0765b00513321fa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Since we now explicitly compile both ramstage and smihandler code
without floating point operations and associated registers we don't need
to save/restore floating point registers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I180b9781bf5849111501ae8e9806554a7851c0da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Ensure USB-C ports' _PLD group numbers appear in order.
get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B
Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75572
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Ensure USB-C ports' _PLD group numbers appear in order.
get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B
Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Ensure USB-C ports' _PLD group numbers appear in order.
get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B
Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
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Select SOC_INTEL_RAPTORLAKE for kuldax so that it will use the RPL
FSP headers for kuldax.
BUG=b:285406822
BRANCH=firmware-brya-14505.B
TEST="FW_NAME=kuldax emerge-brask
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage"
Cq-Depend: chromium:4583807, chrome-internal:6003096
Change-Id: Icbf8b26bc2bfee2559cce236bde80a99f8bff859
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75599
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:285406822
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I9ae58d704cba8124c6cb9865431aff84c9d154f7
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75600
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Add the phoenix usb config struct for Myst since the FSP has been
updated to accept the config from coreboot and the default values
do not work.
BUG=None
TEST=Boot to OS on Myst, verify devices are seen with lsusb
Change-Id: I329aba80f3003a3a5f343b8dcc3efa8502b98e24
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in
case device is a tablet and motion sensors are handled by ISH instead
of EC.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled and loaded
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix for the "Onboard Keyboard and Type-C ports are not working after
resuming from powerd_dbus_suspend" issue. This issue was caused since
FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState
programming when GpioOverride UPD is enabled.
This patch moves the IO Standby State programming that FSP was doing to
coreboot.
BUG=b:284264580
TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add devicetree config for ALC1019_ALC5682I_I2S
BUG=b:278169268
TEST=emerge-rex coreboot and verified on screebo
Change-Id: I2814cc76aff43daf0353cfef41592591bbe3d213
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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To support the localized text, we need to get the locale id by vboot
APIs and read raw string content file: preram_locales located at either
RO or RW.
The preram_locales file follows the format:
[string_name_1] [\x00]
[locale_id_1] [\x00] [localized_string_1] [\x00]
[locale_id_2] [\x00] [localized_string_2] ...
[string_name_2] [\x00] ...
This code will search for the correct localized string that its string
name is `memory_training_desc` and its locale ID matches the ID vb2api
returns. If no valid string found, we will try to display in English
(locale ID 0).
BUG=b:264666392
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bmpblk chromeos-bootimage
Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
On Myst, the FSP is shutting down the PCIe lanes that the SSD is
on. Enable hotplug to force the FSP to keep the lanes active.
BUG=b:284213391
TEST=Boot to OS
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Enable s0ix on Myst.
BUG=b:277215113
TEST=builds
Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74279
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Intel Quark was dropped in commit 531023285e. Thus, drop the remaining
FSP headers.
Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
This patch ensures to update the FSP-M UPDs related to PCIe RP mask
properly as per the SoC type.
For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse
PCIe RPs are from PCH die in case of MTL-S.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Change-Id: Ice81553274682476bb4c927061b1196dc142836d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Intel/MTLRVP is built with Intel Meteor Lake-U SoC, so select it.
Currently, there is no functional difference, but in the future FSP
UPD parameters can be overridden properly.
BUG=b:276697173
TEST=Able to build and boot intel/mtlrvp.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75607
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Google/Rex is built with Intel Meteor Lake-U SoC, so select it.
Currently, there is no functional difference, but in the future FSP
UPD parameters can be overridden properly.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75612
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch introduces the different SoC flavors of Intel Meteor Lake as:
* MTL-U
* MTL-P
* MTL-S
MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die.
The task for mainboard is to specify the correct SoC type rather than
selecting the MTL SoC by default.
This change is necessary to support the different SoC flavors of Intel
Meteor Lake.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.
BUG=b:273962021
TEST=Verified the settings on google/rex using debug FSP logs.
Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
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Update header files for FSP for Meteor Lake platform to version 3194_81,
previous version being 3165_81.
FSPM:
1. Add 'PchPcieRpEnableMask' UPD
2. Address offset changes
Add "FspProducerDataHeader.h" file to support MRC version Info
BUG=b:284803304
TEST=Able to build and boot google/rex to ChromeOS.
Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the karis variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:285195072
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_KARIS
Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Generate RAM ID for Samsung K4UCE3Q4AB-MGCL
DRAM Part Name ID to assign
K4UCE3Q4AB-MGCL 3 (0011)
BUG=b:281950933
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL
DRAM Part Name ID to assign
K4UCE3Q4AB-MGCL 3 (0011)
BUG=b:281943392
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
The ramtop entry has to be 10 bytes long, and it was incorrectly set
to 10 bits, instead of 10 bytes. Change this to 80.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add newlines to log messages to prevent them from running into each
other.
Change-Id: I4f61c80385f384a3734a5122ccb4161c1ed7c6c5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75589
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
pci_rom_probe() can allocate memory when mapping a CBFS
file, so pci_rom_free() should be called before leaving
the function.
BUG=b:278264488
TEST=Build and run with additional debug prints added
to confirm that data are correctly unmapped
Change-Id: Ie6fbbfd36f0974551befef4d08423a8148e151e7
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74779
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
|
|
It adds simple function, which frees the memory which
could be allocated by pci_rom_probe(). In the next step
it will be modified to free only memory, which was mapped
from CBFS.
BUG=b:278264488
TEST=Build and run with additional debug prints added
to confirm that data are correctly unmapped
Change-Id: Ibc9aad34b6bf101a3a0c06b92ed2dc6f2d7b9b33
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74778
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move microcode load/unload to pre_mp_init and post_mp_init callbacks.
It allows to make sure that ucode is freed only if all APs updated
microcode.
BUG=b:278264488
TEST=Build and run with additional debug prints added
to confirm that data are correctly unmapped
Change-Id: I200d24df6157cc6d06bade34809faefea9f0090a
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The phoenix SoC does not support multiple EFS locations. Set the default
to the only valid value and prevent mainboard overrides by making the
option non-user-configurable.
TEST=build birman-phoenix
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsEnable'.
Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
|
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This adds manifest generated by amdfwtool to CBFS.
BUG=b:224780134
TEST=Tested on Skyrim device
Change-Id: I13c9d322735e0979484b120c665fb100cf187eab
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74267
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch adds FW_CONFIG to accommodate different Screebo BOM
components across various SKUs.
1. DB_CONFIG for DB_TPEC/DB_TBT/DB_UNKOWN
2. AUDIO for ALC1019_ALC5682I_I2S/AUDIO_UNKNOWN
BUG=b:278169268
TEST=build pass
Change-Id: I928aae61d4936509a7b68f4041c0cd72f298e83d
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Implementation of enable/disable cache functions aren't complex,
simply drop cr0 variable usage, still maintains good readablity.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: I81688e8bbb073e1d09ecf63f3f33e1651dbd778e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75552
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.
Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Follow the eKTH7B18U_Product_Spec_V1.1 to add the device.
BUG=b:284381267
TEST=Check touch screen can detect in coreboot.
[INFO ] \_SB.I2C1.H010: ELAN Touchscreen at I2C: 02:10
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I4bd521410953892a477020a872de0d882001b178
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Follow the data sheet SA577C-12C0, Rev. 1.1 to add the device.
BUG=b:284381266
TEST=check touch pad can detect in coreboot.
[INFO ] \_SB.I2C0.D015: ELAN Touchpad at I2C: 01:15
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0eb0ee1e6cb9c15bfe3964af6ce2ed02eee370a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
Follow the schematic_0502 to add the audio codec and amp.
BUG=b:270109435
TEST=Check device can detect in coreboot.
[INFO ] \_SB.I2C3.RT58: Realtek RT5682 at I2C: 04:1a
[INFO ] \_SB.I2C3.D029: Realtek SPK AMP R at I2C: 04:29
[INFO ] \_SB.I2C3.D02A: Realtek SPK AMP L at I2C: 04:2a
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Icfec8d99be8fde986c5516e0c4cd50dae1edfa98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75477
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are only SSD connected to SATA ports on this mainboard. To prevent
misbehavior, set the correct hard drive type for enabled SATA ports.
BUG=none
TEST=Boot into OS and check the stability of the SSD
Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
|
|
Intel's APL FSP offers the possibility to select the connected hard
drive type to SATA ports. One has the option to choose between HDD ('0'
- default) and SSD ('1').
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I52c3566fb3c959ada6be33f0546ac331f4867d10
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
|
|
Due to mainboard restrictions a SATA link at Gen 3 can cause issues as
the margin is not big enough. Limit SATA speed to Gen 2 to achieve a
more robust SATA connection.
Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In cases where there are limitations on the mainboard it can be
necessary to limit the used SATA speed even though both, the SATA
controller and disk drive support a higher speed rate. The FSP parameter
'SpeedLimit' allows to set the speed limit.
It should be noted that Gen 3 equals the default value '0'. This means
that inside FSP the same code is executed.
This patch provides a chip config so that this FSP parameter can be
set as needed in the devicetree on mainboard level.
Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Check existence of crashlog records in CBMEM before copying them
to BERT, otherwise it can lead to NULL pointer access.
Bug=None
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog.
Change-Id: I4288011866283a3a5fb8ec9e10cd51b794052b4e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75528
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Do not copy the crashlog record if the record is 0xdeadbeef
Bug=None
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog.
Change-Id: I0edbf6902685a882876d525e63c5b602c1590ea1
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Check pmc_record_size variable for collecting PMC records,
instead of cpu_record_size variable.
Bug=None
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog.
Change-Id: I4c35ba2bcf757231aa2872802eb82d4d50742cd9
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75526
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:217968734
TEST=Build guybrush firmware
Change-Id: I93dfa50cd1116e0f6652186acb37fd43d638cf84
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75491
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new Kconfig LINUXPAYLOAD_CMDLINE_VPD_OVERWRITE that can overwrite
Linux payload's kernel command line from VPD. Currently only overwrite
Linux kernel command line 'loglevel' via VPD key 'kernel_log_level'.
TESTED=On OCP Delta Lake, with kernel_log_level set to 0, warm reboot
time can see about 10 seconds improvement comparing to kernel log level
7.
Change-Id: Idf06c7ab9958c940fc3b23d560bb9dade991a6da
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
When the default pci_domain_read_resources() is used,
keep 32-bit memory resources below the limit given by
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT. This serves as a
workaround for missing/wrong reservations of chipset
resources.
This will help to get more stable results from our own
allocator, but is far from a complete solution. Indvi-
dual platform ASL code also needs to be considered, so
the OS won't assign conflicting resources.
Most platforms have reserved space between 0xfe000000
and the 4G barrier. So use that as a global default.
In case of `soc/intel/common/`, use 0xe0000000 because
this is what is advertised in ACPI and there are traces
of resources below 0xfe000000 that are unknown to core-
boot's C code (PCH_PRESERVED_BASE?).
Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top-
down allocation. Fixes EHCI w/ top-down in QEMU.
Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75102
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on the power sequence of the panel [1] and PMIC datasheet [2],
the power on T2 sequence VSP to VSN should be large than 1ms, but it's
-159us now, and the power off T2 sequence VSP to VSN should be large
than 0ms, but it's less than 0 now. Let's modify the power sequence
to meet the datasheet requirement.
[1] HX83102-J02_Datasheet_v03.pdf
[2] TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:282902297
TEST=power sequence T2 pass
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ib1625c6a211f849071393f69eaf5c649a8e7f72e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75298
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The TPS65132S is designed to supply positive/negative driven
application. It communicates through standard I2C compatible interface,
and it intergrates a EEPROM whose contents will be loaded into the
register at startup. Since TPS65132S is used in staryu and geralt
projects, we move the implementation to mediatek/common.
The datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:282902297
TEST=boot starmie to firmware screen
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75488
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The DPTF parameters were verified by the thermal team.
BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Use the proper format specifier for unsigned integers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5e39377d62981229531027b3153d5b343a0a7538
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75400
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Don't assume only one IO and one MEM domain resource.
Currently the code is awkward for bridge devices where loops over
resources are done twice. This would be avoided on top of other patches
that improve the allocator (topic:allocator) by adding a top-down mode.
However those patches break the tree and having the option to have
multiple resources per type would make it easier to get those patches in
without breaking the tree.
Change-Id: I3d3a60c9a4438accdb06444e2b50cc9b0b2eb009
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67018
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
This patch refers and backport some of previous work from Linux Kernel
(https://lore.kernel.org/all/1561689337-19390-3-git-send-email-ricardo.
neri-calderon@linux.intel.com/T/#u) that optimizes the MTRR register
programming in multi-processor systems by relying on the CPUID
(self-snoop feature supported).
Refer to the details below:
Programming MTRR registers in multi-processor systems is a rather
lengthy process as it involves flushing caches. As a result, the
process may take a considerable amount of time. Furthermore, all
processors must program these registers serially.
`wbinvd` instruction is used to invalidate the cache line to ensure
that all modified data is written back to memory. All logical processors
are stopped from executing until after the write-back and invalidate
operation is completed.
The amount of time or cycles for WBINVD to complete will vary due to the
size of different cache hierarchies and other factors. As a consequence,
the use of the WBINVD instruction can have an impact on response time.
As per measurements, around 98% of the time needed by the procedure to
program MTRRs in multi-processor systems is spent flushing caches with
wbinvd(). As per the Section 11.11.8 of the Intel 64 and IA 32
Architectures Software Developer's Manual, it is not necessary to flush
caches if the CPU supports cache self-snooping (ss).
"Flush all caches using the WBINVD instructions. Note on a processor
that supports self-snooping, CPUID feature flag bit 27, this step is
unnecessary."
Thus, skipping the cache flushes can reduce by several tens of
milliseconds the time needed to complete the programming of the MTRR
registers:
Platform Before After
12-core (14 Threads) MeteorLake 35ms 1ms
BUG=b:260455826
TEST=Able to build and boot google/rex.
Change-Id: I83cac2b1e1707bbb1bc1bba82cf3073984e9768f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
This patch removes the wbinvd call preceding CR0.CD setting in
disable_cache() to improve the boot time performances. According to
some experimental measurements, the wbinvd execution takes between 1.6
up and 6 milliseconds to complete so it is preferable to call it only
when necessary.
According to Intel Software Developer Manual Vol 3.A - 12.5.3
Preventing Caching section there is no need to flush and invalidate
the cache before settings CR0.CD. The documented sequence consists in
setting CR0.CD and then call wbinvd.
We also could not find any extra requirements in the AMD64
Architecture Programmer’s Manual - Volume 2 - Memory System chapter.
This extra wbinvd in coreboot disable_cache() function does not seem
documented and looking into the history of the project got us all the
way back to original commit 8ca8d7665d67 ("- Initial checkin of the
freebios2 tree") from April 2003.
Even the original disable_cache() implementation (see below) is a bit
curious as the comment list two actions:
1. Disable cache cover by line 74, 75 and 77
2. Write back the cache and flush TLB - Line 78
But it does not provide any explanation for the wbinvd call line 76.
68 static inline void disable_cache(void)
69 {
70 unsigned int tmp;
71 /* Disable cache */
72 /* Write back the cache and flush TLB */
73 asm volatile (
74 "movl %%cr0, %0\n\t"
75 "orl $0x40000000, %0\n\t"
76 "wbinvd\n\t"
77 "movl %0, %%cr0\n\t"
78 "wbinvd\n\t"
79 :"=r" (tmp)
80 ::"memory");
81 }
BUG=b/260455826
TEST=Successful boot on Skolas and Rex board
Change-Id: I08c6486dc93c4d70cadc22a760d1b7e536e85bfa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
|
|
Enabling MIPI UCAM for screebo project
BUG=b:277883010
TEST=none
Signed-off-by: jason.z.chen <jason.z.chen@intel.corp-partner.google.com>
Change-Id: Id06e5c162d911a4bd78190757c25e7f760160a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Registered DIMM should be 'FORMFACTOR_DIMM' with 'DETAIL_REGISTERED'
instead of 'FORMFACTOR_RIMM', RIMM has been EOL for so many years.
Memory form factor info is now correct on 4th Gen Xeon server platform
with registered DIMM.
Signed-off-by: Ziang Wang <ziang.wang@intel.com>
Signed-off-by: Kehong Chen <kehong.chen@intel.com>
Change-Id: I1eea4717a2d60c6100c262a2284a2ac5109f114a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit
(TCC) activation feature for proto phase.
BUG=b:282865187
BRANCH=None
TEST=Build FW and test on Screebo board
Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Incorrect filename "MakeFile.inc" cause gpio.c can not be complied.
Rename to "Makefile.inc" and confirm gpio.c can load correctly.
BUG=b:281620454
BRANCH=dedede
TEST=build and confirm gpio.c can be loaded
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I39947c66de04695e5242ab1affc328894f34f9f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75520
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move I2S config from common to board.
BUG=none
TEST=Build google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I51ca902e9b0077d5d5cc9c3507d26301a0f61bc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75513
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable drivers for SoundWire codecs and define the topology in
the devicetree for the rex0 variant with the SoundWire daughter
board connected.
+------------------+ +--------------------+
| | | Headphone Codec |
| Intel Meteor Lake| +--->|Cirrus Logic CS42L42|
| SoundWire | | | ID 0 |
| Controller | | +--------------------+
| | |
| Link 0 +----+ +-------------------+
| | | Left Speaker Amp |
| Link 1 | +--->| Maxim MAX98363 |
| | | | ID 0 |
| Link 2 +----| +-------------------+
| | |
| Link 3 | | +-------------------+
| | | | Right Speaker Amp |
+------------------+ +--->| Maxim MAX98363 |
| ID 1 |
+-------------------+
This was tested by booting the firmware and dumping the SSDT table
to ensure that all SoundWire ACPI devices are created as expected with
the properties that are defined in coreboot under \_SB.PCI0:
HDAS - Intel Meteor Lake HDA PCI device
HDAS.SNDW - Intel Meteor Lake SoundWire Controller
HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec
HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp
HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS. Playback and recording are also
validated on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FBVDD_PWR_EN signal should be inverted in its control level
on Agah v.s. Hades. The original change covered the Hades
implementation, but needs to be updated to invert for Agah. This
change can be removed once we drop support for Agah.
BUG=b:280467267
TEST=built for Hades and Agah
Change-Id: I7f90c03b8d9b859004e5c124bf0a1f7b59921c3d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75530
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Fine tune eMMC DLL settings based on Uldren board.
BUG=b:280120229
TEST=executed 2500 cycles of cold boot successfully on all eMMC sku.
Change-Id: I82a55a1fe17aa910eb02464df463603dcbbbef05
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75459
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI DmaProperty for WLAN device. `is_untrusted` is eventually
ended up by adding DMA property _DSD which is similar to what
`add_acpi_dma_property` does for WWAN drivers, hence it makes sense to
have a unified name across different device drivers.
BUG=b:279676191
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I6d898a939aa0be31a671d2436a81c34f7a1ec030
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75460
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add 'common_config.acp_config' to the device tree, so we have the
correct pin configuration.
BUG=b:225320579
TEST=USE=fwconsole emerge-skyrim ... ; verify 'devbeep' works in
depthcharge console
TEST=Boot into ChromeOS, verify YouTube sound works with internal
speakers and headphone jack
TEST=Boot into ChromeOS, verify microphone with Google Meet
Change-Id: Ie2d79408104273d8a53214b683800fa0663c14d3
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Improve boot time performances by replacing the wbinvd instruction
with multiple clflush to ensure that the SIPI data is written back to
RAM.
According to some experimental measurements, the wbinvd execution
takes between 1.6 up and 6 milliseconds to complete. In the case of
the SIPI data, wbinvd unnecessarily flushes and invalidates the entire
cache. Indeed, the SIPI module is quite small (about 400 bytes) and
cflush'ing the associated cache lines is almost instantaneous,
typically less than 100 microseconds.
BUG=b/260455826
TEST=Successful boot on Skolas and Rex board
Change-Id: I0e00db8eaa6a3cb41bec3422572c8f2a9bec4057
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Suggested-by: Erin Park <erin.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75391
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This brings the ACPI code more in line with both what the new code for
the AMD SoCs will do and also what the current Intel code does. This was
mainly done to have a reduced delta to the new AMD domain resource
handling functions to debug it, but it might still be useful to upstream
this change.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cca05976b1c9d4e994e407b8c0197da7dd35eb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Add beeps and blink SATA LED on critical errors.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I45b8b4fda00d58a1ab1d7dfab49d6f841bc0b000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69821
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Incorrect memory part was used in CB:74745 to generate the DRAM Strap
ID. Amend the memory_parts_used.txt and regenerate the DRAM Strap ID.
BUG=b:272746814
TEST=Generate the DRAM Strap ID.
Change-Id: I0668d7e02345610a11f9113d8bbe99a474f33f1a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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The acpigen_resource_[bus_number,io,mmio*] functions didn't make it very
clear that they are generating resource producer ranges and not resource
consumer ranges. To clarify this, change the function names to
acpigen_resource_producer_[bus_number,io,mmio*] and explicitly add the
ADDR_SPACE_GENERAL_FLAG_PRODUCER flag which evaluates to 0, so this
doesn't change the functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I334f38aa8ab418d5577f92b980ff750504e2bb4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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cbfs_boot_map_optionrom will generate lower case hex digits for the
filename to look for in CBFS, so make sure that the file name will use
lower case hex digits and no upper case hex digits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d4daa04120de0f2c853a44691b7e2c52eb2af20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75483
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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