summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2024-01-26mb/amd/onyx_poc: Add and use APCB configuration dataVarshit Pandya
This patch adds APCB blobs to the mainboard directory and it replaces CB:76445 Also this brings onyx_poc mainboard inline with how APCB are included in other AMD mainboard: commit 95d05d830162 ("mb/google/zork: Add and use APCB configuration data"), commit I352f58e0d39 ("mb/google/ skyrim: Add and use APCB configuration data") and commit I1c34528fa0f ("mb/amd/onyx_poc: Add and use APCB configuration data"). BUG=none TEST=build/boot onyx_poc Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80204 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/amd: factor out common acpi_add_ivrs_table implementationFelix Held
Instead of open-coding this functionality in all AMD SoCs, factor it out into a common implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80208 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-01-26mb/purism/librem_cnl: Set edk2 boot timeout for Librem MiniMatt DeVillier
As with other devices with only an external display, the Librem mini/ mini-v2 need a few extra seconds (vs an internal panel) for display init in order for the edk2 boot splash to be visible before the default boot target is booted. TEST=build/boot Librem Mini v2 w/edk2 payload, verify splash screen shown / user has time to enter setup menu. Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-26src, util: Update toolchain.inc references to .mkMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ieaf7894f49a90f562b164924cc025e3eab5a3f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-26lib/smbios: Add 32 bit entry point if below 4GMaximilian Brune
If the smbios table is not below 4G there is no need to have a 32 bit entry point. Even worse it could cause the payload to try to use the entry point. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I4cb426bb0c45282ed03ff4c65d15004b7f985dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/76911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-26mb/google/brya: alphabetize model configsNick Vaccaro
Alphabetize the ordering of model configs and selects in Kconfig and Kconfig.name BUG=None BRANCH=None TEST='emerge-brya coreboot' and verify it builds. Change-Id: Id9347421337d451ce72fcf3984489b06f372f70c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-26mb/google/rex/var/karis: Skip tcc_offset overrideSubrata Banik
This change eliminates the unnecessary override of the tcc_offset chip configuration to 10, as the default rex baseboard now handles this setting correctly. TEST=Successfully built and booted google/karis, confirming tcc_offset remains at 10. Change-Id: Ie40db1431fb0197ee360ad5656878e57f51c855b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-26mb/google/rex/var/screebo: Modify TCC_offset to 20Subrata Banik
Follow thermal team request, override tcc_offset to 20. TEST=Build and verified by thermal team using google/screebo. Change-Id: Idc76f9c0054f21f066b779e6404a1c175eb396a0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-26soc/intel/commonlake: Re-add SATA to soc_api_name() listMatt DeVillier
Now that we've added an ACPI device for SATA, add the name back to the soc_acpi_name() list so the PEPD LPI constraint list generates a valid reference to the SATA device. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80059 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26soc/intel/common/block/sata: Add ACPI stub for SATA deviceMatt DeVillier
Add an ACPI stub containing the SATA device in proper scope, along with the device status, so that there exists a device to be referenced from the PEPD LPI constraint list. Fixes a Windows BSOD INTERNAL_POWER_ERROR on devices with enabled SATA ports. TEST=build/boot Win11 on google/puff (kaisa). Change-Id: I951c62d09609ed73079fe97ea9ce49fdee333272 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-26Revert "soc/intel/cannonlake: Add missing min sleep state for thermal device"Matt DeVillier
This reverts commit d64b66ba267a217d0b6716309019c36c8cfdf8c2: "soc/intel/cannonlake: Add missing min sleep state for thermal device." Reverting because commit e00523aae2ea ("soc/intel/cannonlake: Drop entries from soc_acpi_name()") removed the ACPI device name for the PCH thermal device, since there is no ACPI device defined for it. Removing the name without removing the minimum sleep state caused an invalid LPI entry to be created, which caused a Windows BSOD: INTERNAL_POWER_ERROR. TEST=build/boot Win11 on google/puff (wyvern). Change-Id: I2dfe76d5f72cde7742cee338fa24eaafb84c4604 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80057 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-25vc/amd/opensil/genoa_poc/mpio: don't add duplicate MPIO descriptorsFelix Held
When the device right below the MPIO chip driver has downstream devices without another chip in between, those downstream devices will also have their chip_ops entry set to vendorcode_amd_opensil_genoa_poc_mpio_ops. To avoid adding the same MPIO descriptor again for those additional downstream devices, make sure that the chip_info pointer of the device isn't the same as the one of the parent device, since that's only the case for those additional downstream devices. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6ba90fdc83ba089127e6722778bfef29dd480bb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25soc/amd/genoa_poc: rely less on boot state hooksFelix Held
Call setup_opensil, opensil_entry, and fch_init in the right order from the init method of the SoC's chip operations. This brings this SoC both more in line with the other SoCs and avoids using boot state hooks for this which also makes the sequence in which those functions are called easier to understand. Previously the boot states were used so that setup_opensil was run before configure_mpio which was run before opensil_entry(SIL_TP1), but since configure_mpio is called from setup_opensil, this is no longer necessary. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same. The FCH init code now runs before the resource allocation like on the AMD SoCs that rely on FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79985 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensilFelix Held
Instead of calling configure_mpio from the init function of the MPIO chip struct for the first device that has this struct as chip_ops, call if from setup_opensil. This will allow to do the calls into openSIL from the SoC's chip_ops init function instead of having to rely on boot state hooks. configure_mpio needs to be called after the xSimAssignMemoryTp1 call which sets up the openSIL data structures, but before the opensil_entry(SIL_TP1) call for which the MPIO data structures need to be filled for it to be able to initialize the hardware accordingly. Since the vendorcode_amd_opensil_genoa_poc_mpio_ops struct now no longer assigns configure_mpio to the init function pointer, we have to check if the device's chip_ops pointer points to vendorcode_amd_opensil_genoa_poc_mpio_ops instead of checking if the chip_ops' init function is configure_mpio to match for the devices below the MPIO chips in the devicetree. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If37077c879e266763fd2748a1a8d71c63c94729b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc/opensil_console: fix host debug print functionFelix Held
Since we pass va_list list to the print function, we need to use vprintk instead of printk. Earlier versions of this code used vsnprintf and a local buffer, but when that code was reworked to not need the temporary buffer, it was replaced by printk instead of the correct vprintk. TEST=Now the console output from openSIL looks as expected: Example line from openSIL's console output when it prints the MPIO configuration from a log some commits before this patch: Host PCI Address - -1352681400:-1353251983:7 Same line with this patch applied looks how it's supposed to: Host PCI Address - 0:0:0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Ia931cc80dea5b7eabb75cfb19f8baa9a09cd2dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/80203 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/rex/variants/deku: update USB-C port configurationTony Huang
This CL update setting according to schematic v0.4. BUG=b:320201111 BRANCH=firmware-rex-15709.B TEST=Built FW image correctly. Change-Id: Ia4570d26ee9fd175ed9099bd057cee3c30c95704 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80156 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-01-25soc/amd/common: Fix typoVarshit Pandya
Change-Id: Ida6e87908ae6996529057c8df12dbe046ee54b98 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-25mb/hp/snb_ivb_laptops: Add SMBIOS slot informationRiku Viitanen
Looking at photos and service manuals, all the WLAN slots are short (half-height) and WWAN slots long (full-height). Change-Id: I894f8216d1b836fbc41423180177bb8651040fbb Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-25mb/google/brya/var/*: Ensure LCD device has a valid addressMatt DeVillier
Some variants added the generic gfx driver with an LCD device without specifying the address, which is required for the backlight controls to be functional under Windows. Add the address value where missing. Address value used (0x80010400) is same as on other Brya variants which did properly set it, and is taken from the ACPI 6.5 spec section B.4.2, _DOD (display output device enumeration), table B-2: - bit 31 = use the ACPI-defined (vs vendor-defined) bit scheme for bits 15-0 - bit 16 = platform firmware can detect the device - bit 10 = display type is internal/integrated flat panel (aka LCD) TEST=build/boot Win11 on google/brya (osiris), verify ACPI backlight controls functional. Change-Id: Id24e330cfb7c993d12665a704e1ca78e2e38874f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-25mb/google/dedede/var/metaknight:Add fw_config probe for multi codecMorris Hsu
and amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:183305590 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Change-Id: I4f212f063a1180d7a1c14769f61b0afef7565cad Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/fizz: Update OEM name listMatt DeVillier
Endeavour and Karma were missing, leading those devices to have empty SMBIOS mainboard names. Fix by adding the missing entries. TEST=build/boot google/fizz (endeavour), verify SMBIOS name correctly shown via dmidecode. Change-Id: I1d4fb2473d27ff5611f9d2b962aae2d6bf6d1da0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80181 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/brox: Switch EC INT and WAKE GPIOsShelley Chen
There was a mistake in the gpio spreadsheet provided by the HW team and the GPIO assignments for the EC INT and WAKE signals got switched from what it was in the schematics. The correct assignments are: GPP_D0 = EC_PCH_INT_ODL GPP_D1 = EC_PCH_WAKE_ODL BUG=b:311450057,b:300690448 BRANCH=None TEST=emerge-brox coreboot Will try to boot OS image on device and see if there are any ec errors. Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79886 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/brya/var/pujjo: Add i2c device for Parade touch screenleo.chou
Add new i2c address 0x24 of touch IC for Parade touch panel. BUG=b:320731709 Test=emerge-nissa coreboot Change-Id: I51bd89beffd912fc147da11d19f38cb44cbe570a Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-24vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpioFelix Held
As a preparation for the following patch, rename mpio_config to configure_mpio to make it both a bit more descriptive and to match the naming scheme used for the functions that get called by setup_opensil. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4b1aa6e964cbbb4affb89cacd33af8b24871bb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-01-24*/mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth
Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/hp to mb/kontron: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icfdadfa6705a64655b38aca25be0818ec26429f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80110 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/sarien to zork: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib8a2ae26ed4380592d15e1a7b2d682639413af01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/google/oak to rex: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I85cda24aa7dec82d23e8a321dac03ec737f4c503 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80108 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/gale to nyan_blaze: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I92f8bd7e1c9fc6e4120fb94c2299a266304e19de Reviewed-on: https://review.coreboot.org/c/coreboot/+/80107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/daisy to foster: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I134acc26c0a79d974a6dd0a3b257f961db7e2d86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80106 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24drivers/mipi: Fine tune VFP, CLK and init code for IVO_T109NW41 panelRuihai Zhou
1. Adjust VFP and CLK to meet 60 +- 0.01 Hz 2. Fine tune init code for panel internal circuit Fixes: 520137f("drivers/mipi: Add support for IVO_T109NW41 panel") BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I4d7c7bd4d79301fbb6d555117d190c358bceafcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/80086 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-24soc/intel: Add Lunar Lake device IDsAppukuttan V K
Added Lunar Lake specific CPU and PCIE device IDs Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Ic0aae6fd7aa8ba3a6a794f8af5ecf3967509b704 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79899 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-01-24mb/google/rex/var/rex: Set TCC to 100°CSumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for rex. BUG=b:270664854 TEST=Build, boot and test on rex with value under sysfs /sys/bus/pci/devices/0000:00:04.0/tcc_offset_degree_celsius Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79992 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Peter Ou <peter.ou@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/asurada to cyan: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5855f49984db59d786decad6142e3525b146a573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80105 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/51nb to mb/gigabyte: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I422cb475723006ca42be93508fb0bf4b1e4e84d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80104 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24device, security: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41f8a9b5d1bdb647a915da1a5e95161b2e34df28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80082 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24lib,console,sbom: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9eabe84d55fd9f434e4128866810c0e4970f2ae7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80081 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24driver/parade to /driver/wwan: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cf3d2e2cd1b6ebe4e941ad64f27698379fef696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80080 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24driver/intel to /driver/ocp: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id47a5ef3c53f767d1e03c788e0022d05b21f5c28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24driver/i2c: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I358b878b97adfd9be156a5dd4a9cbaf9e81bca1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24driver/acpi to /driver/gfx: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f299920eb7c6d6f8888cfe5e223ae03093a1d88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80077 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24superio: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41191f6971bdd8ecff2c56f4bfa2b57c87530b83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80076 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-01-24southbridge: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic80d27a963da8eddc3d1f0d9a3d59763028d4ed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80075 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-01-24soc/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24soc/intel: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24soc/amd/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie449267fe4fdd75110f577e1b9f748cd06140950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24northbridge: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iddac15cc42532f44dda44032be0f8525f6347abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80070 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24soc/intel/xeon_sp/chip_common: Improve the domain IDPatrick Rudolph
Use a union to access the PCI domain ID. This will become handy in the following commits to gather meta-data from the domain ID. Change-Id: I5c371961768410167a571358f6f366847a259eb6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80099 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24device/device_util: Add method to retrieve the domainPatrick Rudolph
Add a function to return the PCI domain device for the specified device. On multi PCI domain platforms this function allows to determine which domain and thus which socket the PCI device belongs to. Change-Id: I0068b82e139fe7a35e6b1b91b7d386b750c80748 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80090 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-24device: Add inline method to identify PATH_ROOTPatrick Rudolph
Add and use inline method to identify the root device. Change-Id: I394c8668245bcfea6414b8ca5f14ef8135897e59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80169 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-24ec: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic060f3605cd18d4bf774573c21957f626f984e2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80069 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-01-24cpu: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I552d487978906f5ea74c3d0d85373fe5b2de3f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80068 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24vendorcode: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I80559b7c86a8fd2583cb0335279f676e0aa0209e Reviewed-on: https://review.coreboot.org/c/coreboot/+/80067 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-01-24acpi,arch,commonlib: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice5dadd3eaadfa9962225520a3a75b05b44518ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/80066 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24soc/intel/cannonlake: Report correct latencies for C statesNico Huber
The C_STATE_LATENCY_FROM_LAT_REG() macro uses values that we also write into the respective MSRs in configure_c_states(). Match the indices to those used there. Change-Id: Ie01a53d6f06bc02a53d95e390e16e9963f4c65ee Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-23ec/dell/mec5035: Hook up radio enables to option APINicholas Chin
Change-Id: Ibfa17ca83ca178c942d9c41533152235384e0cdf Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Original-Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-23ec/dell/mec5035: Add command to control radio stateNicholas Chin
This was determined by sniffing the LPC bus while moving the hardware wireless switch between the enabled and disabled positions on the Latitude E6400. The vendor BIOS provides options to change which radios the switch controls, which was used to determine the mapping between each radio device and the command argument values. Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77534 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-23mb/google/brox: Move cnvi to overridetreeShelley Chen
We need to disable the cnvi device when pcie wifi is enabled, so need to use the FW_CONFIG defined in the overridetree for this. BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=This will be tested on the device when received Change-Id: If9e861db37e321fd69c09f9b4aafa2e212f92caa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79898 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-23mb/google/brox: Enable WLAN on root port 5Shelley Chen
BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=test on device with lspci & make sure can see the Intel Network controller Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-22mb/google/brya: Create xol variantYH Lin
Create the xol variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:319506033 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_XOL Change-Id: Id60c50b70c9ab53d62ad48cfc15462f2410f9f02 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80145 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22device/device_util: Print full domain IDPatrick Rudolph
Print the whole 32bit of the domain ID. Change-Id: Iae0752f3ae8ed683d4f61c7a47d0dee223a1ba22 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-22mb/hp/snb_ivb_laptops: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from hp/snb_ivb_desktops are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I42b680f753fb2ed8bc0ae8b5bfb20ee8a7cf8bdb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80049 Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22device/device.h: Drop acpi_inject_dsdtArthur Heymans
This is now unused in the tree and filling SSDT should always be used. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-22soc/intel/xeon_sp: Add IIO resources via SSDTArthur Heymans
There is no need to inject this code in DSDT. Just generating a _CRS Name in SSDT containing a resource template works well and reduces the need to sync up on names being used to return _CRS names in DSDT. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-22soc/intel/xeon_sp: Scan and allocate resources on all stacksArthur Heymans
The code can now deal with stacks that have no resources so just hook them all up. Intel XEON-SP FSP reports all report the state of its stacks, which comprise of PCI root bridges and their respective resources, like PCI busses, IO and MEM resources, via HOB. Parsing all of those into native coreboot structures makes it possible to handle those in a more native fashion like use PCI drivers, native helper functions, ... As opposed parsing those structures again out of the HOB each time. This makes code reuse across the tree more feasible. An additional advantage is that Linux does not need to redo resource allocation since the one done by coreboot will be valid, which potentially decreases boot time. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/78332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-22mb/hp/snb_ivb_laptops: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I58e5dfa57856e80d1a5e4a6fab0b2523301fa8f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80048 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-01-22commonlib/bsd/compiler.h: Define __section(section) macroYu-Ping Wu
Define __section(section) to be a shorthand for __attribute__((__section__(section))). Change-Id: I67a37e5b2aae0bfa68b0319c477ab5d6c55e6501 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-22mainboard/Kconfig: add 24MB ROM sizeMaciej Pijanowski
16MB + 8MB flashes are used on some boards, such as Lenovo M920 Change-Id: Iac6e076ed17d7e944cc829ff0cb27ede50c6f7db Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80072 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-01-22mb/google/dedede/var/galtic: Correct name for mem-part K4U6E3S4AA-MGCRDaniel Peng
Repo sync code recently, run command as memtioned in TEST and found the changed for the auto-gen files. Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR, and no new for the used hex file. BUG=b:320181366 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79976 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22soc/intel/xeon_sp: Fix devicetree walking upPatrick Rudolph
Connect the PCI domain to the bus to allow walking the devicetree up. This is required to figure out which PCI domain a device belongs to. Change-Id: I8cc50cabf7ad540c52498e1ffe7f9246550ed87b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-01-22soc/intel/cmn/block/pmc: Fix prev_sleep_state string name mappingAnil Kumar
commit d078ef2152052b5ce8686249dcd05ebd50010889 ("soc/intel/cmn/block/pmc: Add previous sleep state strings in log") used SLP_TYP numbers to map ACPI sleep state value. This incorrectly printed wrong string for prev_sleep_state during S5. ex: after a cold reset the previous sleep state printed was [DEBUG] prev_sleep_state 5 (S3) This patch corrects this by using ACPI sleep state numbers for mapping the prev_sleep_state values. TEST=test the logs on google/rex board after cold reset [DEBUG] prev_sleep_state 5 (S5) Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I9bcdacc4d01a8d827a6abdf9af2b9e5d686ed847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80144 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-22soc/intel/meteorlake: Fix system hang by enabling SMI handlingKane Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:306267652 TEST=Cold reboot test on 20 google/screebo by ODM, all passed w/o hang. Change-Id: Ie1f096f8eda4adcf1627e44afa517b02adddad76 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-21device_util: Drop unused function bus_pathArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id23a291af20473c3b3e67178b66fcde920d49984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-20mb/purism/librem_skl: Fix pcie_rp5 in device tree (WLAN)Jonathon Hall
WLAN has always been pcie_rp5, there is nothing on pcie_rp1. RP5 gets promoted to function 0 (RP1's function) since no earlier functions are enabled. This simplifies later refactoring that will handle the FSP root port enable flags (which were correctly set already) using the device tree enables. Test: Boot librem_13v2 and verify WLAN is enabled. Change-Id: I7a724a01b5f171a16de83ff6122630e2d66557c1 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-20soc/amd/*/chip: factor out FSP-S callFelix Held
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-20soc/amd: factor out non-CAR romstage to common codeFelix Held
Since the romstage code is very similar between all AMD non-CAR SoCs, factor out a common romstage implementation. All SoCs that select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so this Kconfig option can be used to determine whether to make that call. In the FSP case, amd_fsp_early_init gets called, while in the case of an implementation that doesn't rely on an FSP to do the initialization, cbmem_initialize_empty gets called to set up CBMEM which otherwise would be done inside the FSP driver code. Since only some SoCs call fch_disable_legacy_dma_io again in romstage right after amd_fsp_early_init, introduce the new SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the SoCs can specify if this call is needed or not. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-20soc/amd/*/romstage: factor out FSP-M callFelix Held
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code and a preparation to make the romstage of all non-CAR AMD SoCs common. Without isolating the call into the FSP-M code, building the common romstage would fail for genoa_poc due to fsp/api.h not being in the include path. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/80002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-20soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.cFelix Held
fsp_m_params.c and fsp_s_params.c only contain FSP-specific code, so only add those to the build if the SOC_AMD_PHOENIX_FSP Kconfig option is selected. Other files have FSP-specific parts too, but those will be reworked in future patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ife38ca6a548d7c3c2e765d9c9f30e0a4057bb373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79984 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20soc/amd/phoenix/Kconfig: factor out FSP-specific optionsFelix Held
Split the SOC_AMD_PHOENIX Kconfig option into SOC_AMD_PHOENIX_BASE that selects the non-FSP-specific options and SOC_AMD_PHOENIX_FSP that selects both SOC_AMD_PHOENIX_BASE and the FSP-specific options. This will help to separate the FSP-specific from the FSP-agnostic code. The mainboards using this SoC now select SOC_AMD_PHOENIX_FSP instead of SOC_AMD_PHOENIX. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e95fbfd9d16930ba3e6cc497557d61adba5a6fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79983 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20mb/google/brox: enable WIFI_SARShelley Chen
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG for WIFI to choose the right wifi_sar hex file. Below is the file mapping: wifi_sar_0.hex = wifi6 wifi_sar_1.hex = wifi7 BUG=b:319302319 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Change-Id: I212c80412141e7770a512bd8ccf4111963bab395 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80085 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19device/Kconfig: Move Intel/ACPI/USB4 specific Kconfig optionsArthur Heymans
This options should not be visible on !Intel, !ACPI and !USB4. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia515d52baead9e151533278c33fda9436ee56168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79669 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/hp/snb_ivb_desktops: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from hp/snb_ivb_desktops are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I0974052c6c18f54b588d296c5c5d11e930f0fcd7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80047 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I31e348ba5954bc463f43e769ddb4aed413faf193 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/x230: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/x230 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Ia06f976ef1439377ff22149044feaa3463d2aeb8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/t430: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t430 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I84f432e89c41a02115715f7f1b56123dd0d81171 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/t530: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t530 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I5ba08843506bc22136aea42ac37936a4f5cad5ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/siemens/chili: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80022 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-19mb/purism/librem_cnl: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-19mb/purism/librem_l1um_v2: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Id592241a1dc33559115800da10a57a5fc10867f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-19mb/protectli/vault_cml: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I76ec42fccfa42bbe3943e048968a76eec3584ee8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-01-19mb/dell/snb_ivb_workst: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from dell/snb_ivb_workstation are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Iac70aa25dd324e1ed5fa0bb995eb995ec3545715 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-01-19mb/dell/snb_ivb_workst: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80052 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/starlabs/starbook/cml: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ia004de6606a1685822d5567123887c60d89e3119 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-01-18mb/google/brya: Drop primus4es boardJakub Czapiga
Primus4es board is no longer supported thus drop it from the tree. TEST=Build all Brya boards in CrOS-SDK - Primus4ES not built. No negative impact observed. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-18include/bootmem.h: Add commentMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I8f6752e887af8c1ceba56153e3da864abd040ffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79947 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18include/memlayout.h: Add OPENSBI linker macroMaximilian Brune
This adds an opensbi linker macro for easier integration into memlayout.ld linker scripts. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I4f138de685c6bfb3cdbf79d63787eb0c5aab8590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77974 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/dedede/var/pirika: Add initial fw_config configuration settingDaniel Peng
1. Describe the FW_CONFIG probe for the settings for Palutena. - WIFI_SAR_ID_0 for AW Wi-Fi module AW-CM421NF - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW 2. In contrast to the AW Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table in dedede platform. 3. For Palutena project, the SKU ID segment of Palutena is set for "0x350000~0x35FFFF". BUG=b:319792428 BRANCH=firmware-dedede-13606.B TEST=build pass Change-Id: Ic4f38928d24c4398d90df226cfe0788a30075bf2 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79930 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2024-01-18mb/google/nissa/var/craaskov: Add fan performance controlRex Chou
Add 6w and 15w fan performance control. BUG=b:318454915 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: If21baa2f6f9bcd527cec2bced27c5fb2cd607830 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79988 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/nissa/var/craaskov: Modify 6W and 15W DPTF parametersRex Chou
1. Modify 6w/15w DPTF parameters based on b:290705146#comment41. 2. 6W MSR power limit_1 power (Watts) increase to 20. 3. 15W MSR power limit_1 power (Watts) increase to 20. BUG=b:290705146 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: I15fa4b8f7c7088ff56da6493659ae45572913b5a Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>