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2016-09-30i945/gma.c: use linux code to calculate divisorsArthur Heymans
The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divisors must be such "refclk * (5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which is defined by the resolution and refresh rate). This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays, like many displays found on the Lenovo T60 might work now. Some examples of T60 displays that were known to not work (in payload): Samsung LTN141XA-L01 (14.1" 1024x768) LG-Philips LP150X09 (15.1" 1024x768) IDtech N150U3-L01 (15.1" 1600x1200) IDtech IAQX10N (15.1" 2048x1536) Samsung LTN154X3-L0A (15.4" 1280x800) LG-Philips LP150E06-A5K4 (15.1" 1400x1050) Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16504 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30vboot: clear tpm when requiredVadim Bendebury
Function which invoked when TPM clear is requested was left empty, this patch fixes it. BRANCH=gru BUG=chrome-os-partner:57411 TEST=verified on a chromeos device that tpm is in fact cleared when CLEAR_TPM_OWNER_REQUEST is set by userland. Change-Id: I4370792afd512309ecf7f4961ed4d44a04a3e2aa Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/16805 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-30mainboard/intel/galileo: Make FSP 2.0 the defaultLee Leahy
Switch from FSP 1.1 to FSP 2.0 as the default build. BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: Icbb3a36cdde68baf4d68fbfc371f8847c56e1162 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16810 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30drivers/intel/fsp2_0: Fix debug display supportLee Leahy
Fix errors in debug display support. BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug on) and run on Galileo Gen2 Change-Id: I2ece056d66dc8568a7b7206970f20368ec5bf147 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16809 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30soc/intel/quark: Fix FSP 2.0 buildLee Leahy
Fix the build issues with FSP 2.0: * Remove struct from the various data structures. * Properly display the serial port UPDs. * Change chipset_handle_reset parameter type BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug off) and run on Galileo Gen2 Change-Id: Icae578855006f18e7e5aa18d2fd196d300d0c658 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30soc/intel/quark: Support multiple version of FSPLee Leahy
Add support for multiple versions of FSP. BRANCH=none BUG=None TEST=Build FSP 1.1 (SEC/PEI core, with all FSP debug off) and run on Galileo Gen2 Change-Id: Ie7e7f0f883c4d3bfcb18fa25571e505cdde00b2d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16807 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30mainboard/intel/quark: Add FSP selection valuesLee Leahy
Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: If6b36ebef49dd2733d272f990bb7c6623d4ab1b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16785 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/via/epia-m850/romstage.c: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ic5359f794c64a9a67ec9e059af337a65073baff4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16784 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/lanner/em8510: Use tabs for indentsElyes HAOUAS
Change-Id: Ib6191c590144438d7d9d6772d792a83e92d5516a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/iwill/dk8_htx: Use tabs for indentsElyes HAOUAS
Change-Id: I303270a45171dda88b7661e3797fd3724e3b055f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/gigabyte/ga_2761gxdk: Use tabs for indentsElyes HAOUAS
Change-Id: Ie752fe0a74acd4b79711596e56fc5ebf83884a0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16779 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29mainboard/elmex: Add new board pcm205401Yuichi Ito
pcm205401 is CPU board equipped with T40R of AMD. We used SeaBIOS and Windows Embedded Standard 7 to test pcm205401. In comparison to pcm205400, only VGA PCI ID is changed and board identifier strings in SMBIOS / DMI. Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155 Signed-off-by: Yuichi Ito <yui.corebt@gmail.com> Reviewed-on: https://review.coreboot.org/15930 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-29mainboard/elmex: Add new board pcm205400Yuichi Ito
pcm205400 is CPU board equipped with T56N of AMD. We used SeaBIOS and Windows Embedded Standard 7 to test pcm205400. I disable the port5, 6, and 7 of the PCI-e in elmex/pcm205400/PlatformGnbPcieComplex.h. I disable the audio capabilities at the 236th line of elmex/pcm205400/platform_cfg.h. Coding style is modified to avoid the error and warning that occur when I commit. Change-Id: I77cb76903fe3c1b500a306426f5399936382695b Signed-off-by: Yuichi Ito <yui.corebt@gmail.com> Reviewed-on: https://review.coreboot.org/15929 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-29src/mainboard: Add vendor ELMEX with a boardYuichi Ito
Add board with amd/persimmon as template. Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67 Signed-off-by: Yuichi Ito <yui.corebt@gmail.com> Reviewed-on: https://review.coreboot.org/15926 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-28google/reef: Mark touchpad and touchscreen as probed devicesDuncan Laurie
Add the 'probed' flag to the touchpad and touchscreen devices so they are probed by the kernel before being loaded, in case they do not exist or are replaced with another vendor. BUG=chrome-os-partner:57686 Change-Id: I0a61964e6874cd99fab0c21fa404a43548fc8ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28drivers/i2c/generic: Add config for marking device as probedDuncan Laurie
Add a config option to the generic I2C device driver to indicate to the OS that this device should be probed before being added. This can be used to provide ACPI device instantiations to devices that may not actually exist on the board. For example, if multiple trackpad vendors are supported on the same board they can both be described in ACPI and the OS will probe the address and load the driver only if the device responds to the probe at that address. BUG=chrome-os-partner:57686 Change-Id: I22cffb4b15f25d97dfd37dc58bca315f57bafc59 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16742 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28mainboard/amd/rumba: Use tabs for indentsElyes HAOUAS
Change-Id: I005e607faa2a6c527584ba9cdcad92f4517a15e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16778 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/supermicro/h8dmr/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: I008ccc5fa9d96e52ee59a4562d81e4f7c1d1a6ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/sunw/ultra40/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: I9b7be74625dfcb6317a1cdb61d0dc77d7f359462 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16776 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/technexion/tim5690: Use tabs for indentsElyes HAOUAS
Change-Id: Icd1f145b3575c6d95dacceb9c0426fbdedcdd686 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16777 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/supermicro/h8qme_fam10/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: I6ca564294ff3d8eaeae21c0e2c008401aa3f32ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/asus/dsbf/romstage.c: Use tabs for indentsElyes HAOUAS
Change-Id: I74d4ef76b8166c8567b1b855c6bc963b4312df77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16773 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-28mainboard/intel/emeraldlake2/gpio.c: Use tabs for indentsElyes HAOUAS
Change-Id: I369c2063a5e57d1fd33d3c6bf7c715c22970fc32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16772 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/intel/eagleheights/debug.c: Use tabs for indentsElyes HAOUAS
Change-Id: I4d2d876d48e018c247e7f365f7c237a4d8ced332 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16771 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28mainboard/broadcom/blast: Use tabs for indentsElyes HAOUAS
Change-Id: I61bef70ec572c12518cd3763a6a860e56bfdb716 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16745 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28soc/intel/apollolake: Add pmc_ipc device supportLijian Zhao
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16649 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28soc/intel/apollolake: Use fixed resource for SRAM and IPC1Lijian Zhao
Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources on BAR0, BAR1 and BAR2 (PMC only) for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into Chrome OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16648 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-27northbridge/sandybridge/raminit_mrc.c: fix missing includeMatt DeVillier
Compilation (w/o native raminit) fails due to missing include Change-Id: Ic79a77006257b32e0181c88c4e24d7c1f5c5f7ce Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/16735 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27mainboard/msi/ms9185/resourcemap.c: Use tabs for indentsElyes HAOUAS
Change-Id: I30b5830442da65ae3ddd35e8bca67795c34e9020 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16737 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27mainboard/msi/ms9185/romstage: Use tabs for indentsElyes HAOUAS
Change-Id: I101462105da31654032ac7e6abd3f9423ad7a7ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16736 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-27x86: acpi: Use GOOG ID for coreboot tableDuncan Laurie
Use the GOOG ACPI ID until there is an official ID allocation for coreboot. Since I administer this range I allocated 0xCB00-0xCBFF for coreboot use. Change-Id: I38ac0a0267e21f7282c89ef19e8bb72339f13846 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16724 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-27mainboard/msi/ms9185/mb_sysconf.h: Use tabs for indentsElyes HAOUAS
Change-Id: Ib2ab95b26c3bb1cbd58aafb1fafd1b285d6a5ba8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-27i945/gma.c: Generate fake VBTArthur Heymans
This generates a fake VBT for the Intel i945 graphic device. i945 supports both the mobile chipset 945gm (calistoga) and the desktop chipset 945gc (lakeport), which is why a VBT with a different id string needs to be created for each target. The VBT id string is obtained from the vbios blob in the following way: "strings vbios.bin | grep VBT". Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16530 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-27nb/intel/*/gma.c: remove spaces at the fake vbt generationArthur Heymans
Padding the VBT id string is now done automatically. Change-Id: I8f9baf7b1585026bc29b82d07e451aa11e284ffb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16740 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-27intel/gma/vbt.c: pad the ID string with spaces.Arthur Heymans
The VBT id string is 20 characters long. If the string is shorter than 20 it needs spaces at the end. This change is cosmetic as all strings were padded by hand. Change-Id: Id6439f1d3dbd09319ee99ce9d15dbc3bcead1f53 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16739 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-26mainboards,ec: provide common declaration for mainboard_ec_init()Aaron Durbin
Add a header file to provide common declarations that the mainboards can use regarding EC init. BUG=chrome-os-partner:56677 Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16734 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins)
2016-09-26mainboards/google/reef: use chromeec's ASL lid switch implementationAaron Durbin
Defer to the lid switch implementation provided by the chromeec. BUG=chrome-os-partner:56677 Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-09-26ec/google/chromeec: provide optional ASL lid switch implementationAaron Durbin
Instead of relying on the mainboards to provide their own LID0 ACPI device, provide the infrastructure so that the mainboards can signal to the EC ASL code to provide the default lid switch implementation. BUG=chrome-os-partner:56677 Change-Id: Ie43b1c4f8522db1245f1f479bfdb685d3066121d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16732 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-09-26soc/intel/apollolake: provide power button ACPI deviceAaron Durbin
Instead of having each mainboard provide the power button, uncondtionally provide the power button ACPI device on behalf of each mainboard. BUG=chrome-os-partner:56677 Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16731 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-26mainboard/*/*/dsdt.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26mainboard/*/*/mptable.c: Improve code formattingElyes HAOUAS
Change-Id: I341293cd334d6d465636db7e81400230d61bc693 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26mainboard/*/*/irq_tables.c: Use tabs for indentsElyes HAOUAS
Change-Id: Idc29373cb01f4304d22ae315812bd40f0aaa94c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16729 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26mainboard/lippert: Use tabs for indentsElyes HAOUAS
Change-Id: If16d55e4ba0702176dc61524915d215ea46c14ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16686 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-24intel/amenia: Remove Amenia mainboardAndrey Petrov
The mainboard is not being worked on anymore, not available outside of Intel and thus has litle practical use. Remove mainboard code completely. Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16725 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-23mainboard/lippert/frontrunner-af: Use tabs for indentsElyes HAOUAS
Change-Id: Id8b60d32d5bdaaa6c693dcf5db992ed975cc2400 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23mainboard/lippert/toucan-af: Use tabs for indentsElyes HAOUAS
Change-Id: Ibd1fa89b450d52691dfef5616712f03fd675f123 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23mainboard/nvidia/l1_2pvv: Use tabs for indentsElyes HAOUAS
Change-Id: I4171e9bbf14c9aa65f698feabd78aa8fbf2a105f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16687 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-22soc/intel/apollolake: Initialize processor count in GNVSDuncan Laurie
Initialize the PCNT variable in GNVS so it is available to ACPI code that expects to know the number of CPUs. Change-Id: I7a6e003ac94218061bf98e8883ed2c62d856af8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-22Build system: Remove IASL_WARNINGS_ARE_ERRORS optionMartin Roth
All systems are building with IASL warnings as errors enabled. Remove the option to disable it. Remove the notification at the end of the build. Change-Id: I5c6218c182fdf173b4026fd010d939a5fa36040e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16606 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21northbridge/amdk8: Improve code formattingElyes HAOUAS
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16644 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-21northbridge/amd/amdmct: Improve code formattingElyes HAOUAS
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21google/enguarde: Adapt to current treePatrick Georgi
Some changes were made in upstream in the meantime that broke the build: - CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS - recovery_move_enabled() -> vboot_recovery_mode_enabled() - chromeos.asl was replaced by an acpi generator Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16683 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-21google/enguarde: Upstream Lenovo N21 ChromebookMatt DeVillier
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to upstream, using google/rambi as a reference. original source: branch firmware-enguarde-5216.201.B commit cf1f57b [Enguarde: Adjust rx delay for norm.] TEST=built and booted Linux on enguarde with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.elf) external reference code (refcode.elf) Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/15444 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21southbridge/sis/sis966/aza.c: Improve code formattingElyes HAOUAS
Change-Id: If5342a2b5bae18b70ea671522efd2691bc9872dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16602 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21northbridge/amd: Improve code formattingElyes HAOUAS
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21soc/apollolake: Correct the comment section in gpio.aslShaunak Saha
This patch corrects the comment section in gpio.asl for GPE method. Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16647 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16673 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Support interrupts for statusDuncan Laurie
Support reading the ACPI GPE status (on x86) to determine when the cr50 is ready to return response data or is done processing written data. If the interrupt is not defined by Kconfig then it will continue to use the safe delay. This was tested with reef hardware and a modified cr50 image that generates interrupts at the intended points. BUG=chrome-os-partner:53336 Change-Id: Ic8f805159650c45382cacac8840450a1f8b4d7a1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16672 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21soc/intel/apollolake: Add function to read and clear GPE statusDuncan Laurie
Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16671 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21soc/intel/apollolake: Initialize GPEs in bootblockDuncan Laurie
Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21x86: acpi: Add function for querying GPE statusDuncan Laurie
Add a function that can be implemented by the SOC to read and clear the status of a single GPE. This can be used during firmware to poll for interrupt status. BUG=chrome-os-partner:53336 Change-Id: I551276f36ff0d2eb5b5ea13f019cdf4a3c749a09 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16669 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Improve data handling and function namesDuncan Laurie
Unify the function names to be consistent throughout the driver and improve the handling while waiting for data available and data expected flags from the TPM. BUG=chrome-os-partner:53336 Change-Id: Ie2dfb7ede1bcda0e77070df945c47c1428115907 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16668 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Clean up locality functionsDuncan Laurie
Clean up the mask and timeout handling in the locality functions that were copied from the original driver. BUG=chrome-os-partner:53336 Change-Id: Ifdcb3be0036b2c02bfbd1bcd326e9519d3726ee0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16667 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Rename i2c read/write functionsDuncan Laurie
Rename the low-level functions from iic_tpm_read/write to cr50_i2c_read/write to better match the driver name, and pass in the tpm_chip structure to the low-level read/write functions as it will be needed in future changes. BUG=chrome-os-partner:53336 Change-Id: I826a7f024f8d137453af86ba920e0a3a734f7349 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16666 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Clean up timeoutsDuncan Laurie
Use two different timeouts in the driver. The 2ms timeout is needed to be safe for cr50 to cover the extended timeout that is seen with some commands. The other at 2 seconds which is a TPM spec timeout. BUG=chrome-os-partner:53336 Change-Id: Ia396fc48b8fe6e56e7071db9d74561de02b5b50e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16665 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Reduce max buffer sizeDuncan Laurie
Reduce the static buffer size from the generic default 1260 down to 64 to match the max FIFO size for the cr50 hardware and reduce the footprint of the driver. BUG=chrome-os-partner:53336 Change-Id: I6f9f71d501b60299edad4b16cc553a85391a1866 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16664 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm: Split cr50 driver from main driverDuncan Laurie
Originally I thought it would be cleaner to keep this code in one place, but as things continue to diverge it ends up being easier to split this into its own driver. This way the different drivers in coreboot, depthcharge, and the kernel, can all be standalone and if one is changed it is easier to modify the others. This change splits out the cr50 driver and brings along the basic elements from the existing driver with no real change in functionality. The following commits will modify the code to make it consistent so it can all be shared with depthcharge and the linux kernel drivers. BUG=chrome-os-partner:53336 Change-Id: I3b62b680773d23cc5a7d2217b9754c6c28bccfa7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm: Move common variables to headerDuncan Laurie
Move the common enums and variables to tpm.h so it can be used by multiple drivers. BUG=chrome-os-partner:53336 Change-Id: Ie749f13562be753293448fee2c2d643797bf8049 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16662 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21Makefiles: update cbfs types from bare numbers to valuesMartin Roth
These values are found in util/cbfstool/cbfs.h. Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/getac - kontron: Add space around operatorsElyes HAOUAS
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/amdfam10: Improve code formattingElyes HAOUAS
Change-Id: I86a252598666af635281eaa467020acb53d71c77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20selfboot: Move the usable-RAM check into a functionSimon Glass
In preparation for making this check optional, move it into its own function. load_self_segments() is already long and we don't want to make it longer. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs correctly Change-Id: If48d2bf485a23f21c5599670e77a7b8b098f1a88 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2381e02efa2033857ac06acbc4f0c0dd08de1080 Original-Change-Id: I005e5e4d9b2136605bdd95e9060655df7a8238cb Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381092 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16585 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-20arm_tf: Fix code style nits and commentsSimon Glass
Tidy up a few things which look incorrect in this file. BUG=chrome-os-partner:56314 BRANCH=none TEST=build for gru Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 434e9ceb5fce69b28de577cdc3541a439871f5ed Original-Change-Id: Ida7a62ced953107c8e1723003bcb470c81de4c2f Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376848 Original-Commit-Ready: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: If8c283fe8513e6120de2fd52eab539096a4e0c9b Reviewed-on: https://review.coreboot.org/16584 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru/kevin: Decrease voltage for little cpu 1.5G to 1.15vShunqian Zheng
In kernel side we set 1.1v for 1.5G, even for coreboot RO, a higher voltage could be safer, 1.2v now seems too high. BRANCH=none BUG=chrome-os-partner:56948 TEST=bootup Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380896 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20rockchip: spi: Improve SPI read efficiencySimon Glass
The SPI driver is quite slow at reading data. For example, with a 24MHz clock on gru it achieves a read speed of only 13.9Mbps. We can correct this by reading the status registers once, then reading as many bytes as are available before checking the status registers again. It seems likely that a status register read requires synchronizing with the SPI FIFO clock domain, which takes a while. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru and see the speed increase from 13.920 Mbps to 24.712 Mbps Change-Id: I24aed0c9c6c5445634c4e056922afaee4e9a7b33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 49c2fc20d7d7d703763e9b0a6f68313a349a84b9 Original-Change-Id: I42745f01f0fe069f6ae26d866004d36bb257e6b2 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376945 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Veyron: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted Jerry Change-Id: Ia19d585b69e7701040209e8bf0b8a6990a166c95 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e7a42c999673ebd89c5b30845a4a5ec93852166 Original-Change-Id: I126cb7077c834e1a8b0a625a592dce8789b5876c Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376884 Reviewed-on: https://review.coreboot.org/16581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20google/gru: Fix up PWM regulator rangesJulius Werner
We did yet another small adjustment to the PWM regulator ranges for Kevin rev6... this patch reflects that in code. Also rewrite code and descriptions to indicate that these new ranges are not just for Kevin, but also planned to be used on Gru rev2 and any future Gru derivatives (which as I understand it is the plan, right?). BRANCH=None BUG=chrome-os-partner:54888 TEST=Booted my rev5, for whatever that's worth... Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9 Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/379921 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16580 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Gru: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted kevin-tpm2 Change-Id: I2fc943f89386ccc6cd9293f5811182a5a51d99b0 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bb1f0fb00d023c045305edc6c9fc655b764a4e8c Original-Change-Id: Ieb61830b9555da232936087cdcf7c61a1e55bab4 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376883 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16579 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru: Add watchdog reset supportJulius Werner
This patch adds support to reboot the whole board after a hardware watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to Veyron. From my tests it looks like both SRAM and PMUSRAM get preserved across warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that makes it easier to deal with in coreboot (PMUSRAM is currently not mapped as cached, so we don't need to worry about flushing the results back before reboot). BRANCH=None BUG=chrome-os-partner:56600 TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30 seconds. Confirm that system reboots correctly without entering recovery and we get a HW watchdog event in the eventlog. Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098 Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/375562 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16578 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20vboot/vbnv_flash: Binary search to find last used entryRandall Spangler
This improves the previous linear search to O(log n). No change in storage format. BUG=chromium:640656 BRANCH=none TEST=Manual (test empty) flashrom -i RW_NVRAM -e Reboot; device should boot normally. (start using records) crossystem kern_nv=0xaab0 crossystem recovery_request=1 && reboot Device should go into recovery mode with reason 1 Reboot again; it should boot normally. crossystem kern_nv (should still contain 0xaab0) Repeat steps several times with request=2, 3, etc. flashrom -i RW_NVRAM -r nvdata Modify nvdata to copy the first record across all valid records flashrom -i RW_NVRAM -w nvdata Reboot; device should boot normally. Change-Id: Ieb97563ab92bd1d18a4f6a9e1d20157efe311fb4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: db9bb2d3927ad57270d7acfd42cf0652102993b1 Original-Change-Id: I1eb5fd9fa6b2ae56833f024bcd3c250147bcc7a1 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376928 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16577 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/via: Add space around operatorsElyes HAOUAS
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16623 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-20northbridge/intel/e7505/debug.c: Improve code formattingElyes HAOUAS
Change-Id: I63f58d95fa01b1f73f3620a5d13f21ef62e2404c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/a-trend - emulation: Add space around operatorsElyes HAOUAS
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-20northbridge/intel/i3100: Add space around operatorsElyes HAOUAS
Change-Id: I5ff894f23dc2a2c59bc5e5d1de4287a6b9c9922c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i945: Add space around operatorsElyes HAOUAS
Change-Id: I24505af163544a03e3eab72c24f25fcdc4b1b16c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16624 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/agesa: Improve code formattingElyes HAOUAS
Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7505: Improve code formattingElyes HAOUAS
Change-Id: I964512c0e913f7443f3dea859b01358645cfd8a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/superio: Add space around operatorsElyes HAOUAS
Change-Id: Ibeab5e7fe0a9005e96934b3b43cfb247ef2e2340 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-20src/include: Add space around operatorsElyes HAOUAS
Change-Id: I0ee4c443b6861018f05cfc32135d632fd4996029 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16614 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-20northbridge/intel/i82830: Add space around operatorsElyes HAOUAS
Change-Id: Ic4e287209cc45fae574e7af9d45b8a0e648ef686 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/haswell: Add space around operatorsElyes HAOUAS
Change-Id: I8fa1e39bfd950475e3b55d6debcbfd92615aa379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16628 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7501: Add space around operatorsElyes HAOUAS
Change-Id: I53aa17076135e55665f2f7c6ede217388fc50cca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_rangeley: Add space around operatorsElyes HAOUAS
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20southbridge/via: Add space around operatorsElyes HAOUAS
Change-Id: Ib48c98bb161b92b28497df26fcfd0eae2c6829df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16635 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_sandybridge: Add space around operatorsElyes HAOUAS
Change-Id: I1b5cdfaf39be639a7ef71e66e91284fa186fbb86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16630 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/gm45: Add space around operatorsElyes HAOUAS
Change-Id: I3781c36a3f354bfd54d20488b95d4f2307c3bce2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16629 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20southbridge/amd: Add space around operatorsElyes HAOUAS
Change-Id: I949ff7de072e5e0753d9c8ff0bf98abfca25798b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-19Revert "drivers/i2c/tpm: Move common variables to header"Duncan Laurie
This reverts commit 64df72e8e2d1c086705325533767ca5e201e842a.
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 13:25:26 +0000