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The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18032
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The console output is garbled until it is fixed in ramstage
by devicetree which sets the uart clock predivider correctly.
Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17969
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Restores KB backlight functionality for auron variants
gandof, lulu, and samus.
TEST: boot Lulu and observe KB backlight functional
Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17960
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add rmu.bin to the list of files that exist only in the read-only
section (COREBOOT) of the SPI flash.
TEST=Build and run on Galileo Gen2.
Change-Id: I30cbd3fb2ef1848807e4de4c479dc7a561c1faba
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18031
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
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Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.
Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.
Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the
TSC for the monotonic timer. Simplify the routine to get the TSC
frequency.
TEST=Build and run on Galileo Gen2
Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18002
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a break statement instead.
While there, fix a bunch of typos in comments.
Change-Id: I465c0188d4b46eabf8d17e69fa0fdc6a9c2ad66e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1229645
Reviewed-on: https://review.coreboot.org/18013
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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When CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH is set, vbnv_cmos will try
to load VBNV from flash if the VBNV in CMOS is invalid. This is usually
correct, except the case of battery cut-off.
CMOS will always be invalid after battery cut-off if there is no RTC
battery (or if that is dead). However, in current implementation the
backup in flash is only updated in coreboot, while the real battery
cutoff (and the clearing of cutoff flags in VBNV) is done in payload
(Depthcharge) stage. This will create an endless reboot loop that:
1. crossystem sets battery cutoff flag in VBNV_CMOS then reboot.
2. coreboot backs-up VBNV_CMOS to VBNV_flash.
3. Depthcharge sees cutoff flag in VBNV_CMOS.
4. Depthcharge clears cutoff flag in VBNV_CMOS.
5. Depthcharge performs battery cutoff (CMOS data is lost).
6. (Plug AC adapter) Reboot.
7. Coreboot sees invalid VBNV_CMOS, load backup from VBNV_flash.
8. Jump to 3.
As a result, we should always clear battery cutoff flags when loading
backups from VBNV_flash.
BRANCH=glados,reef
BUG=chrome-os-partner:61365,chrome-os-partner:59615
TEST=emerge-reef coreboot bootimage;
Change-Id: I3250a3a179a7b0de9c6e401e4a94dcd23920e473
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/423460
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/18008
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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I've recently added an assertion to ensure that the effective I2C
frequency on Rockchip SoCs is not too far off the 400KHz target due to
divisor rounding errors. A 10KHz margin worked fine for RK3399, but it
turns out that RK3288 actually only ever hit 387KHz since its I2C clocks
are based off the already pretty low 75MHz PCLKs. While we could
probably change the PCLKs to make this closer, that seems like a too
intrusive change for something that has already worked just fine for
years, so just loosen the restriction a little more instead.
BRANCH=None
BUG=chromium:675043
TEST=None
Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421095
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/18007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We've found that the SLB9645 TPM sometimes seems to randomly start
returning 0xFF bytes for all requests. The exact cause is yet unknown,
but we should try to write our TIS code such that it avoids bad
interactions with this kind of response (e.g. any wait_for_status()
immediately succeeds because all "status bits" are set in the response).
At least for status and burstCount readings we can say for sure that the
value is nonsensical and we're already reading those in a loop until we
get valid results anyway, so let's add code to explicitly discount 0xFF
bytes.
BRANCH=oak
BUG=chrome-os-partner:55764
TEST=None
Change-Id: I934d42c36d6847a22a185795cea49d282fa113d9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420470
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/18006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This reverts commit 34a6537512d412363bf56428b7ae284e6dd80fb3, which
appears to cause random stability issues on some elm units.
BRANCH=oak
BUG=chrome-os-partner:60869
BUG=chromium:673349
TEST=None
Change-Id: I5ce9e2673db1bc7a1f487a3c3bcce4651a5e3567
Reviewed-on: https://chromium-review.googlesource.com/419862
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18005
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Kconfig values and early debugging code to better segment and debug
the early code in bootblock by using the SD LED as an indicator. Update
the help text for the debug Kconfig values to point to the various
failure locations.
TEST=Build and run on Galileo Gen2
Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Fix serial port configuration broken by how PCI configuration space was
referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default
to enabled).
TEST=Build and run on Galileo Gen2
Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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This extra check is based on comparing CPU BSEL pins and reports in
MCH configuration. This gives false positives in the case of 1333MHz
CPUs which automatically get downgraded to 1067MHz by the northbridge
(max supported frequency by 945gc).
TESTED with Intel Xeon 5460 (does not boot but completes raminit)
Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17997
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Checking for dram self refresh in MCHBAR8(SLFRCS) generates false positives.
Change-Id: I25afd565cae0269616e38ecbcdf385281bae5d1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17996
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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amd_generate_powernow is never called by in lpc_slave_ops.
Move it to lpc_ops like on all other AMD southbridges.
TESTED on Gigabyte ga-m57sli-s4
Change-Id: I7db036e681d591a19e15dd3eaafb88b72a41bea1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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If the cmos checksum is incorrect it should fall back to sane defaults.
Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17968
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Update DPTF TSR1/TSR2 passive/critial trigger points.
TSR1 passive point:53, critial point:80
TSR2 passive point:90, critial point:100
2. Update PL1 Min to 4W and PL1 Max to 12W
3. Update thermal relationship table (TRT) setting.
BUG=none
BRANCH=master
TEST=build, boot on snappy dut and verified by thermal team member.
Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17955
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT1_v0.3_20161227.xlsx)
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU critical point:103
TSR1 passive point:45
TSR2 passive point:55, critical point:90
2. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 3secs
Change Charger Effect on Temp Sensor 2 sample rate to 60secs
Change CPU Effect on Temp Sensor 1 sample rate to 8secs
BUG=chrome-os-partner:60038
BRANCH=master
TEST=build and boot on electro dut
Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17975
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Write gpio level twice to make sure the level is set
after pins have been configred as GPIO and to minimize
glitches on newer hardware.
Required to set correct GPIO layout on T500.
Tested on T500.
Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18012
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
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uart_fill_lb() was added to drivers/uart/uart8250mem.c, so when the
Oxford OXPCIe952 Kconfig option is enabled, we were getting an error.
"multiple definition of `uart_fill_lb'"
The new version of uart_fill_lb sets the regwidth depending on the
Kconfig symbol DRIVERS_UART_8250MEM_32, so if that's selected, don't
give DRIVERS_UART_OXPCIE as a choice.
Change-Id: Ife24ab390553b10b2266809595c2e06463de708c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I57dd933ad70ffac95388d832bd5047f2225688e3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17973
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The devicetree lacks the 'chip' option for the Super I/O,
which causes the Super I/O related entries to be ignored.
This also adds other LDN that are present on this Super I/O.
Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17965
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Because the binary repo is disabled by default, we get frequent
questions about why the build failed, relating to microcode in the
binary repository.
- Show an error saying that the file is missing instead of the typical
make error of no rule to build the file.
- Show a note encouraging users to try enabling the binary repo if it's
not enabled.
Change-Id: If4148c18cfb781ed2932bd2ae4a289b621afdebf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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SPD revision 1.1 introduced FTB timings, an extra set of SPD values that
specify a more precise tCKmin, tAAmin, tRCDmin, tRPmin and tRCmin.
For backwards compatibility, the MTB is usually rounded up and the FTB
part is negative. For this reason some memories were not set up optimally,
as the FTB part was ignored and the resulting timing wasn't set to the
minimum value.
The tests were performed on a Lenovo X220 with two Micron 8KTF51264HZ-1G9E
(1866 MHz): reading only the MTB part, coreboot reports a tCKmin of
1.125 ns, corresponding to a working frequency of 800 MHz; with the
additional tCKmin FTB part (-0.054 ns) the new (rounded) value is
1.070 ns, valid for a 933 MHz operation.
Tested also with Ballistix DDR3-1866 SODIMM on Lenovo T420: the memory is
now detected as DDR3-1866 instead of DDR3-1600.
Some manufacturers (like Micron) seems to expect a small rounding on the
timings, so a nearest-value rounding is performed. If this assumption
isn't correct, an error up to ~2 ps can be committed, which is low enough
to be safely ignored.
Change-Id: Ib98f2e70820f207429d04ca6421680109a81f457
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/17476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use CONFIG_VBOOT to enable do_printk_va_list to match the conditionals
in include/console/console.h and the only caller is vboot/vboot_logic.c.
CONFIG_VBOOT is also selected for CONFIG_CHROMEOS.
TEST=Build and run on Galileo Gen2
Change-Id: Ia115c74afa498a14d5edd6f7940ec2edc124516f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Migrate duplicated enable_vmx() method from multiple CPUs to common
folder. Add common virtualization option for CPUs which support it.
Note that this changes the default to enable virtualization on CPUs
that support it.
Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Enable an internal pull-up on the power button input as a quick
press is resulting in power button override being asserted.
BUG=chrome-os-partner:61312
TEST=tested on eve P0b to ensure quick power button press does
not result in a shutdown due to power button override.
Change-Id: I3028cf7faef309cf4d60c3585b48adab6e1549d4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17962
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Correct tabs that were intended as spaces.
Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17905
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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With the default TCC activation offset value as 0 and Tjmax
temperature value as 100 degree C, Pcode firmware starts taking
prochot action at 100 degree C [Tjmax-Offset].
But before Pcode firmware starts prochot action at 100 degree C,
device is getting shutdown at 99 degree C due to DPTF critical
CPU temperature.
This patch sets TCC activation offset value to 10 degree C for
thermal throttle action to prevent this kind of shutdown.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built, booted on skylake and verified target offset value.
Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17921
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TCC activation functionality has package scope. It was set
for all CPU in the system which is unnecessary.
In this patch TCC activation is being set by the BSP only.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built for skylake platform and verified the TCC activation
value before and after S3.
Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with
the ability to perform tx and rx of flash command and response at the
same time. Instead of introducing this notion at SPI flash driver layer,
clean up the interface to SPI used by flash.
Flash uses a command-response kind of communication. Thus, even though
SPI is duplex, flash command needs to be sent out on SPI bus and then
flash response should be received on the bus. Some specialized x86
flash controllers are capable of handling command and response in a
single transaction.
In order to support all the varied cases:
1. Add spi_xfer_vector that takes as input a vector of SPI operations
and calls back into SPI controller driver to process these operations.
2. In order to accomodate flash command-response model, use two vectors
while calling into spi_xfer_vector -- one with dout set to
non-NULL(command) and other with din set to non-NULL(response).
3. For specialized SPI flash controllers combine two successive vectors
if the transactions look like a command-response pair.
4. Provide helper functions for common cases like supporting only 2
vectors at a time, supporting n vectors at a time, default vector
operation to cycle through all SPI op vectors one by one.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17681
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash
controller in different files.
BUG=chrome-os-partner:59832
BRANCh=None
TEST=Compiles successfully for chell and eve.
Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.
Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use level (vs edge) interrupt triggering
- HDA verb entries use simplified macro entry format
- correct FADT table header version
- remove unused ACPI device entries / .asl file(s)
- clean up ACPI code (e.g., trackpad on Lulu)
- adjust _CID for trackpad on Lulu in order to not load non-functional
Windows driver (does not affect Linux)
- remove unused header includes (multiple/various)
- correct I2C addresses used for SMBIOS device entries
- correct misc typos etc
The existing auron_paine samus boards are removed.
Variant setup modeled after google/slippy
Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.
Additional changes besides simple consolidation include:
- simplify power LED functions
- simplify HDA verb definitions using azelia macros
- use common SoC functions to generate FADT table
- correct FADT table header version
- remove unused haswell_pci_irqs.asl
- remove unused header includes (various)
- set sane default fan speed (0x4d) for all variants
Variant setup modeled after google/beltino
Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Tested to work:
* GPU (Nvidia gt210) in PCIe x16 slot;
* SATA;
* serial;
* 800MHz and 1067MHz FSB Core 2 Duo CPUs;
* ethernet;
* native VGA graphic init.
What does not work:
* resume from s3 suspend;
* superio hardware monitor (not initialised in coreboot).
Quirks:
* does not boot with just one dimm in slot B.
Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Make the ending comment associated with "chip ...hudson" match the
appropriate directory name.
Change-Id: I5e0d6d41a2e3f963760aad08ed6108acac5b66b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17904
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown. Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Values based on vendor bios and suggested by Arthur Heymans for FSB1067.
FSB1067:
The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits:
0x1a / 0x14 ~ 1067/800
EPVC1IST:
The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800.
Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17198
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Both HDMI and eDP work (simultaneously).
TESTED on Acer C720 (peppy).
Change-Id: Ifc4e3c187bcabd8965d9586237a52b440bfa7f20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17916
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Change-Id: I55e2d99b3f9929703f34d268f4490f3c5c2c766f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17915
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit
bc8613ec (Fix i945 based boards) fixes that to use the correct
delay of 200 ms. This code was then copied over, when adding support for
the Lenovo X60.
The reset was related to the shipped crypto card on the Roda RK886EX and
Kontron 986LCD-M, so is not needed on the Lenovo X60. So remove it.
TEST=Build and boot on Lenovo X60t.
Change-Id: Ia37d9f0ecf5655531616edb20b53757d5d47b42f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17703
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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GPP_D12 needs an internal pull-up to get this rail working on
current boards. GPP_D0-GPP_D3 were changed from SPI interface
and I just missed this change earlier.
BUG=chrome-os-partner:58666
TEST=test camera and touchpad on eve
Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The user and supervisor counters could not be safely enabled
before as the register numbers were not finalized. Now that
everyone agrees, we can enable them. Until we are sure the
toolchains are caught up, we use the hardcode name with
the register names in comments. As soon as toolchains
settle down we'll do one more pass and convert to
the symbolic names.
Tested on lowrisc bitstream and SPIKE simulator.
Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17920
Tested-by: build bot (Jenkins)
Reviewed-by: Alex Bradbury <asb@lowrisc.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andrew Waterman <aswaterman@gmail.com>
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There was an assumption that all SPI controllers could
consume a full page of data to write. However, that
assumption doesn't hold when spi_crop_chunk() indicates
sizes smaller than page size. If the requested offset isn't
page aligned from the start then writes will fail corrupting
data since a page boundary isn't honored.
The spansion driver needed quite a bit more work to honor
the spi_crop_chunk() result. It now mimics the other
driver's code. Also, needed to add spi_crop_chunk() to
marvell/bg4cd SoC to make google/cosmos build. SPI obviously
doesn't work on that platform, but it fixes the build error.
Change-Id: I93e24a5a717adcee45a017c164bd960f4592ad50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17910
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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Add poppy board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Compiles successfully
Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17866
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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An incorrect board name was propagated over various generations of mainboards.
Correct the comments for these. Addressing the todo items will come in a
later patch.
Change-Id: I4abd028fee5087955a7b6ba8d38f99c8207d24b4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17903
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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Declutter the conditional building of fchec.c. Use the CONFIG
setting directly instead of ifeq ().
Change-Id: I6d3721764e66e5615a639c1979d60ff1291b5d33
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17902
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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Reduce the Bettong devices and match up the comments to the
northbridge.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from e7c38571be6406453640d671210b2074a91f162e)
Change-Id: I53adff741f5cf2bd75c37421949bd30f214f5692
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17849
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Utilize libgfxinit's support for scaling to simplify the framebuffer
configuration. In case of multiple displays of different resolutions,
we had configured one framebuffer big enough for their union, each
display only showing its respective upper left window. Instead, we use
the smallest resolution now and show the whole image on all displays.
Change-Id: I70a9d92f88ef891703829945264f94ac7eff09b0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17492
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
|
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Add an alternative gfxinit implementation for textmode. The legacy VGA
plane and textmode is configured through coreboot provided functions.
libgfxinit uses this plane as alternative to the usual high resolution
plane.
Change-Id: Iad0754c50fc6faec35f49583fe1c7cb50ac6c0c5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17279
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.
Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.
memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.
SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872
SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.
Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder
Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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Add the region used by the A-Link to AHB configuration registers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705
and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b)
Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17848
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Add the missing two I2C controllers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d)
Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Remove the unused Name field. Its previous design generates an FWTS
error and a recommendation for changing it to Serialized.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0)
Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Required to add rules.h as default include, otherwise we get error:
./src/include/rules.h:128:5: error:
"__COREBOOT_ARM_ARCH__" is not defined [-Werror=undef]
Previously, rules.h was not included in omap-header build at all.
Change-Id: I75265916856f2f21f7966619ea65d63acd599e2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17746
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Also remove config.h, kconfig.h will pull that one in.
Change-Id: I798b3ffcf86fca19ae4b0103bb901a69db734141
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17667
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Required fix to have rules.h as default include.
Change-Id: I6ce2d4e13de5139a84c709b5836ecd41c0abc836
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17747
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.
As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.
There are no reasons to have this as board-specific setting.
Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Select this to provide menu in menuconfig to add flash
descriptor file. ME or GbE firmwares themselves are not
required, but integrated NIC MAC and SPI configuration
fields are still useful.
Change-Id: I14b86e2f38ec39924d2cbf0932d82f66ed356a03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17805
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Larger size fits GRUB payload and fixes case to
build 82801ix with HAVE_INTEL_FIRMWARE.
Change-Id: I90e33fb3a0b0e1a60dcc2a9a022bef034f3270d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17830
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Just before jumping to OS wakeup vector do the same
tasks to signal coreboot completion that would be done
before entry to payload on normal boot path.
Change-Id: I7514c498f40f2d93a4e83a232ef4665f5c21f062
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17794
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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RISCV requires that timer interrupts be handled in machine
mode and delegated as necessary. Also you can only reset the
timer interrupt by writing to mtimecmp. Further, you must
write a number > mtime, not just != mtime. This rather clumsy
situation requires that we write some value into the future
into mtimecmp lest we never be able to leave machine mode as
the interrupt either is not cleared or instantly reoccurs.
This current code is tested and works for harvey (Plan 9)
timer interrupts.
Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17807
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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This reverts commit c86da67436827c25919a2f5966049485a58fc984.
Alas, I have to disagree with this in every single line. The comment
added to the top of the file only applies to a single function therein
which sits over a hundred lines below. That's not much helpful. More-
over, the link in the comment is already down ofc.
The comment is also irritating as it doesn't state in which way (enco-
ding!) it applies to the code, which presumably led to the wrong in-
terpretation of the IDs.
At last, if anything should have changed it is the strings, the IDs
are resolved to. `smbios_fill_dimm_manufacturer_from_id()` has to
resolve the IDs it gets actually fed and not a random selection from
any spec.
Since I digged into it, here's why the numbers are correct: The func-
tion started with the SPD encoding of DDR3 in mind. There, the lower
byte is the number of a "bank" of IDs with an odd-parity in the upper
most bit. The upper byte is the ID within the bank. The "correction"
was to clear the parity bit for naught. The function was later exten-
ded with IDs in the DDR2-SPD encoding (which is actually 64-bit not
16). There, a byte, starting from the lowest, is either an ID below
127 plus odd-parity, or 127 which means look in the next byte/bank.
Unused bytes seem to be filled with 0xff, I guess from the 0xff2c.
Change-Id: Icdb48e4f2c102f619fbdca856e938e85135cfb18
Reviewed-on: https://review.coreboot.org/17873
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Currently only there is only one eaglelake board in coreboot
(ga-g41m-es2l) featuring a G41 variant northbridge.
Adding boards with a different variant (Q43, Q45, G43, G45, B43) will
require this change for graphic initialisation.
Change-Id: Ida32c563a99576b66685dfdadf9a534fd6e197dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17900
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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This change adds the required device node in SSDT for defining
GPIO-based fixed voltage regulator.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that ELAN touchscreen works with exported GPIOs and ACPI
regulator.
Change-Id: I4380aea0929fb7e81dbe83f940e3e51e983819f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17798
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Set the thermal throttle (prochot) activation to be 10 degrees
below TJmax so PROCHOT# kicks in at 90C instead of 100C.
BUG=chrome-os-partner:58666
TEST=boot on eve, check msr value before and after resume:
> iotools rdmsr 1 0x1a2
0x000000000a6400e6
> echo mem > /sys/power/state
> iotools rdmsr 1 0x1a2
0x000000000a6400e6
Change-Id: I3ab3a050a1e27c18a940bd7519eabaf015ef93eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17901
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Turn on LPC decoding in romstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc)
Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17227
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Add ALC286 commands and update the PLATFORM_CONFIGURATION structure
with the list address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee)
Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17226
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Change the Carrizo settings used for Bettong to ones specific
to Stoney on Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb)
Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Duplicate the code from DB-FT3lc and use the correct names.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c)
Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17224
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove a duplicated check and setting for xHCI during the
AMD_INIT_RESET callout. This is handled by the wrapper. Also
remove nearby commented code. EcChannel0 is not a member of
FCH_RESET_DATA_BLOCK.
Leave the check in AMD_INIT_ENV. Although AGESA honors what
was previously requested, additional settings depend on the
state of Usb.Xhci0Enable.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd)
Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17223
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change the default configuration for the following settings:
AGPIO14: BT radio disable
AGPIO64: NFC PU
AGPIO65: NFC wake
AGPIO66: Webcam
AGPIO69: PCIe presence detect
AGPIO70: GPS sleep
AGPIO116: MUX for Power Express Eval
EGPIO119: SD power
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4)
Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17222
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the last bit of Bettong board_id checking from Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c)
Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17221
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Gardenia doesn't have the ability to modify settings depending on
the board ID.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89)
Change-Id: I2c928431306c669735cf735042855e95721bb107
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17220
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Gardenia makes no special considerations for a board_id regarding
SPD access and addressing. Remove this from the source and use
the standard AGESA call.
Make SPD address changes to devicetree.cb. Note that Gardenia is
designed to be a two channel, single DIMM/channel system (some SKUs
with two DIMMs on the second channel). However, this port is for
the Stoney processor which is a single channel. As a result, the
second DIMM slot is not usable. A future improvement could involve
a port using a different processor, with unique devicetree files
for each.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15)
Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Use bettong as the reference for the gardenia mainboard.
Update makefiles etc so it builds.
This patch intentionlly keeps the carrizo_fch.asl file to
remain synchronized with the AMD PI package.
Remove items that do not apply to the Stoney APU, rewrite the
comments associated with the PCIe devices, and fix up the
SPD register association to match the 00670F00 chip.h.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e)
Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17218
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable default acpi path PCI0.LPCB if TPM support is
selected in the kconfig system and the acpi path is not set via
acpi_name callback in the platform code.
Thanks to Aaron Durbin for providing this fix.
Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/17855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add custom files for Sandybridge and IvyBridge functions.
Move only the minimal required functions into separate files.
Both files' functions are going to call raminit_common functions.
No functionality is changed.
Sandybridge code path tested on Lenovo T420.
Change-Id: I1b1dfbd0857b59d3ae4392b73c033ee7a5aed243
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17605
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Some part of preram cbmem console output is truncated.
Increase preram cbmem console size to 0xd00 to avoid the same.
Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Sometime preram cbmem logs are truncated due to lack of
space (default preram cbmem console size is 0xc00).
Provide Kconfig option to configure preram cbmem console
size so that mainboard can configure it to required value.
Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17839
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On Netburst (Pentium 4) the fsb cannot be read from
MSR_FSB_FREQ (msr 0xcd). One has to use msr 0x2c instead.
Change-Id: I0beccba2e4a8ec5cd23537b2207f9c49a040fd73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17832
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add power management type config option that allows mainboards to
either:
1. Define a power resource that uses the reset and enable gpios to
power on and off the device using _ON and _OFF methods, or
2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can
directly toggle the GPIOs as required.
GPIO type needs to be updated in drivers_i2c_generic_config to use
acpi_gpio type so that it can be used for both the above cases.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that elan touchscreen works fine on reef using exported
GPIOs.
Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17797
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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BUG=chrome-os-partner:60194
BRANCH=None
TEST=Compiles successfully
Change-Id: I0fe146cf2235c7c4ad3ea5589ed556884de3a368
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17842
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Enable the actual touch devices to be probed by the kernel
and remove the placeholder devices that I put in before
and were used for initial bringup.
BUG=chrome-os-partner:58666
TEST=tested on eve
Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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When trying to bring up a device with a malfunctioning TPM2 chip, the
driver currently gets stuck waiting for SPI flow control, causing
bricked devices.
This patch puts a 100 ms cap on the waiting time - this should be
enough even for a longest NVRAM save operation which could be under
way on the TPM device.
BRANCH=gru
BUG=chrome-os-partner:59807
TEST=with a matching change in depthcharge, now a gru with corrupted
SPI TPM comes up to the recovery screen (it was not showing signs
of life before this change).
Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17898
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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It was unsigned, not a good place to be for testing < 0.
Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1241911
Reviewed-on: https://review.coreboot.org/17888
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Change-Id: Ic1d1b85a1d7e85b555a93b3a0b55fe310b26e34a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1353362
Reviewed-on: https://review.coreboot.org/17875
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Put the UART pins into native mode in bootblock so they are not
floating when we try to communicate with H1 over I2C. Without
a serial console enabled BIOS these pins were not configured
until ramstage.
BUG=chrome-os-partner:60935
TEST=Boot Eve board without serial console and H1 TPM enabled
Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add a generic I2C-HID driver for these types of devices that
do not need extra functionality. This allows a new device to
be added without having to write a new driver.
The i2c-hid PNP0C50 is automatically added as the _CID for the
device in the ACPI Device.
BUG=chrome-os-partner:58666
TEST=used on eve to describe a new i2c-hid touch controller
Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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The Roda Lizard RV11 is a comparatively lightweight, full-rugged
notebook. It's based on a 17W TDP dual core Ivy Bridge CPU.
The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o
options).
The RV11 is the first board to use the native graphics initialization
by libgfxinit. Tested so far, are the internal eDP port, DP and VGA.
Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Checking for memory self refresh can generate false positives,
as explained in faa6beb: "northbridge/intel/i945:
CHECK_SLFRCS_ON_RESUME Kconfig option".
This seems to be the case for this motherboard.
TESTED on ga-945gcm-s2l.
Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17617
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The type3 SMBIOS table has a non-optional SKU field at the end,
which causes a parsing error when missing. Add but do not populate it.
Change-Id: I988d0626b8680740697e1db58eb6d0b87874bfde
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17851
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
Change-Id: Ic86048d1d6354b9b0dac3c8957df318d0825c905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17783
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For Chrome OS the normal MRC cache should be cleared when a hardware
retrain recovery request is observed. The reason is that since there
are 2 different MRC cache slots there needs to be a mechanism which
allows an end user make a system bootable again if the MRC settings
happen to not allow the system to boot any longer. Therefore, one
just needs to enter recovery with the hardware retrain flag and
the system normal MRC cache slot will be invalidated.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17871
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Allow a board/platform to invalidate the normal MRC cache when
hardware retraining is requested in recovery mode. A small 4 byte
payload is used to update the latest data written. It will of course
fail on MRC cache retreival on next usage.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17870
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The EC switches, including the hardware retrain flag, are
cleared when handing off the vboot state in romstage. However,
one may still want to query the state of the hardware retrain
flag. Thus, add a method to get the flag from cbmem.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17869
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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