| Age | Commit message (Collapse) | Author |
|---|
|
This patch adds support for disabling the heci1 device
at the end of boot sequence. Prior to this, FSP would have
sent the end of post message to ME and initiated the d0i3 bit.
This uses the Psf unlock policy and the p2sb device to disable
the heci1 device, then lock the configuration and hide the device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu or glados board. set the hecienabled policy
to 0 and check for heci 1 device status in kernel lspci.
CQ-DEPEND=CL:*238451
Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358
Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311912
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12976
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
CB used to clear recovery status towards romstage end after FSP
memory init. Later inside FSP silicon init due to HSIO CRC mismatch
it will request for an additional reset.On next boot system resume
in dev mode rather than recovery because lost its original state
due to FSP silicon init reset.
Hence an additional 1 reset require to identify original state.
With this patch, we will get future platform reset info during romstage
and restore back recovery request flag so, in next boot CB can maintain
its original status and avoid 1 extra reboot.
BUG=chrome-os-partner:43517
BRANCH=none
TEST= build and booted Kunimitsu and tested RO mode
Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7
Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302257
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.
BUG=none
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)
Change-Id: I761d623d1064b8030f2703500d174259bb20ca79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f7bdb1091b7dd62a3c0b4a2272ab9f56fd7acc9
Original-Change-Id: Id1a867980d2e28a1f328aa36bed3c846b2137bec
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317471
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12974
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
At S0, S0ix and S3 LPC LAD signals are
floated at 400~500mV.
BRANCH=none
BUG=chrome-os-partner:48331
TEST=Build and boot on lars
Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38
Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317071
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Count DIMMs on current memory channel instead of all memory channels.
The current code is only able to correctly handle the following memory
configurations:
One DIMM installed in either channel.
Four DIMMs installed, two in each channel.
Two DIMMs installed, both in the same channel.
For systems that have any other configuration the DRAM On-Die-Termination
setting is wrong.
For example:
Two DIMMs installed, one in each channel.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
Change-Id: I0e8e1a47a2c33a326926c6aac1ec4d8ffaf57bb6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
|
|
Remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and boot on lars
Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9
Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317080
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12962
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Provide an option for including the NHLT blobs within the
lars mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted lars board.
Audio worked with MAXIM audio card.
Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271
Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316092
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12961
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This corresponds with the changes that have already gone into the
soc/intel/skylake chip.h file and is needed to get skylake platforms
building again.
Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13022
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
I don't think the warning is valid, because we already verify
that num_channels is 2 or 4 as soon as we enter the function.
Adding the default case makes the compiler happy.
Fixes warning:
src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array':
src/soc/intel/skylake/nhlt/dmic.c:100:2: error: 'formats' may be used
uninitialized in this function [-Werror=maybe-uninitialized]
return nhlt_endpoint_add_formats(endp, formats, num_formats);
^
Change-Id: Idc22c8478ff666af8915d780d7553909c3163690
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Make sure the latest & greatest Intel targets actually
build in our build system.
intel/sklrvp is still failing for reasons unrelated to the rest
of the skylake boards. Leaving that disabled for now.
Change-Id: Ie784628a57257cea30e5e47074648198b884f6db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12857
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
|
|
remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
Change-Id: Ia523e7956c06c9f4a60e0a2296f771cc3c70bc25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12a07eebfb8fa4ee8013fbbb12283a0b429cacfd
Original-Change-Id: I2be6c5b0114e4c7d8a7b9ceb59ee32f28f61769f
Original-Reviewed-on: https://chromium-review.googlesource.com/316717
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12958
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Follow kunimitsu setting of
https://chromium-review.googlesource.com/#/c/313309/
BRANCH=none
BUG=none
TEST=Build and boot on lars.
Change-Id: I77a4454b3702dc58dc70a7b981b25a656e97f534
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c390322b4c770a0206549257dd34d1ef1242cc3
Original-Change-Id: I612e799433a396a6cce5742adb6de72a305b5df1
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316270
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12954
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
LARs design don't have SD Connector over native SD Controller.
BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot LARs. Use "lspci" doesn't list 0x1E:06
device in list.
CQ-DEPEND=CL:315420
Change-Id: Idff7243a6aaf4b8d5f49e4bf215a77131f716485
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca769138b97b404598c4a6bfa6c2ff5c1c3ec896
Original-Change-Id: I71416ac89a8c91ab272d6737d1b46c8045567e17
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12947
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Skylake Core boot should have configurable option to skip
PCH based SD 3.0 Controller from customer/reference design.
Addition to that no unused or unnecessary should list under
device view.
BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot Kunimitsu and LARs.
Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb
Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315420
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Cofigure VR settings for kunimitsu
BRANCH=none
BUG=chrome-os-partner:45387
TEST=Build and booted in kunimitsu
CQ-DEPEND=CL:311317
Change-Id: Ib2afe7694d2a807cea1befa73349bd21a3e7d909
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3548d7cb3a00826377e819f20d07167b4eb2c65
Original-Change-Id: I6b80f509bc0ab6f65f26eec0651a3b44fb38fbf9
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313068
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12945
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Adding VrConfig UPDs and assign values to those from devicetree
BRANCH=none
BUG=chrome-os-partner:45387
TEST=Build and booted in kunimitsu
CQ-DEPEND=CL:310192
Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd
Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311317
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12944
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
This patch helps to enable SkipMpInit token of FSP SiliconInit UPD
BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.
CQ-DEPEND=CL:310869
Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577
Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310192
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Even though the data32 variable was getting written by
pch_pcr_read(), GCC still flagged it as being used while
uninitialized and failed the build.
Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the
successful path, depending on the size of the read.
Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12860
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
|
|
Tested on Intel D510MO
Before this patch, I was unable to get the SATA controller into AHCI
mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus.
With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1
Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7)
No regressions detected.
Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12923
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add new configuration parameters eg. #SLP_S3 assert width
BRANCH=none
BUG=chrome-os-partner:44075
TEST=Build and booted on kunimitsu, verified that CB is doing
the Lockdowns which were previously done by FSP.
CQ-DEPEND=CL:310869
Change-Id: I782df49bbf73c121b191f0661907173c4fd29b64
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de0742869b1b148597d3714a3bc29a0dc08642aa
Original-Change-Id: I2b4041cdc22a29e79d2ff7f2cc49f51f80da5567
Original-Reviewed-on: https://chromium-review.googlesource.com/313309
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12942
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Some more PCH Policy UPD Parameters are added in FSP.
Lockdown config moved from FSP to coreboot.
Removing settings in devicetree.cb which are zero.
BRANCH=none
BUG=none
TEST=Build and booted on kunimitsu, verified that CB is doing
the Lockdowns which were previously done by FSP.
CQ-DEPEND=CL:*237842, CL:310191
Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553
Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310869
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12941
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
Some MemoryInit UPD parameters have been moved to
SiliconInit in FSP 1.8.0. This patch has the respective
changes in coreboot for this.
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
CQ-DEPEND=CL:*237423, CL:*237424
Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118
Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
At S0, S0ix and S3 LPC LAD signals are
are floated at 400~500mV.
BRANCH=chrome-os-partner:48331
BUG=None
TEST=Build and Boot kunimitsu
Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f4b902e220dcde73df56970208c45fe3148b70e
Original-Change-Id: I597d4816d09d0cfd9b0ec183a9273551aed8688a
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316529
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://review.coreboot.org/12957
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
GPIO ASL APIs to get GPIO Value.
Need such APIs to read GPIO config settings.
Example: Kunimitsu need to read AUDIO_DB GPIO
to identify codec select.
BUG=chrome-os-partner:44481
BRANCH=none
TEST=build and boot on Kunimitsu.
Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb
Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316352
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12956
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
DPTF may power off the system when it starts if the CPU temp is >90C.
Since TJmax is 100C set the critical threshold to just below that value.
BRANCH=none
BUG=none
TEST=Build and boot on lars.
Change-Id: I3abf946ae09c3c691480e468d0c1d74730dc6c06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c2230009edb840e88a20c2d8a87f942c09b6bf3
Original-Change-Id: Iee1a3596dbbe934f68637f012c02c078c3751eeb
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316102
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Disable kepler device, it is removed and was not used on proto anyway.
BUG=none
BRANCH=none
TEST=build and boot on lars proto
Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1
Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315950
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12950
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Adding support for Maxim 98357A audio amplifier.
Removed SSM4567 support from LARs.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Build & boot on LARs.
Verify audio playback works using MAXIM amplifiers.
Change-Id: I2cd8b20e936319b434017b6dd73d4739684d21d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76cbc20826c884194a144f6b6bc644900e5d475d
Original-Change-Id: I1156096b6aa367c0b8d8e3952d92f0eb5cf2820f
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314543
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12960
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BUG=chrome-os-partner:48292
BRANCH=None
TEST=Boot with the write protect screw in place. Issue
crossystem wpsw_boot. It should show 1.
Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c
Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81
Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316009
Original-Commit-Ready: Arindam Roy <rarindam@gmail.com>
Original-Tested-by: Arindam Roy <rarindam@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12952
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=none
BUG=none
TEST=Build and booted on lars.
Change-Id: Ic1313385e0aa1760b473a34c853a95c76257eecf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a47faee53e08da81602b485937621fd49eb2ddbf
Original-Change-Id: I7c91dcdc82525a6d2b706f8f504ba48601097ef7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316370
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12953
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
modify the P/N in samsung K4E6E304EE-EGCF SPD from K4E6E304ED-EGCE to
K4E6E304EE-EGCF
BRANCH=none
BUG=chrome-os-partner:48299
TEST=build chell and use gooftool to probe and P/N match
Change-Id: Ie560e5c0d4b9a3cfb34c3856911930fb8159764e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dabe5eaa8abf54f4e4a5492062adca6ef9b4634d
Original-Change-Id: Ie8d44ac6032e5213928bfae2a2ac5877d4193d62
Original-Signed-off-by: Wisley <wisley.chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316100
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12951
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Adding support for Maxim 98357A audio amplifier.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Build & boot on Skylake kunimitsu Fab4 with MAXIM codec.
Verify audio playback works using MAXIM.
Change-Id: I4f020ccae540b02d5d533704a52cebb7805715fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c0a81300e02e917500fa3c0241c95dd795abaf04
Original-Change-Id: I8875c9a55f09b1ec353203cfcb2186dc5fd66542
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309894
Original-Tested-by: Rohit M Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12949
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3
Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315520
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d
Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313794
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12939
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The use of a NHLT table is required to make audio work
on the skylake SoCs employing the internal DSP. The table
describes the audo endpoints (render vs capture) along with
their supported formats. These formats are not only dependent
on the audio peripheral but also hardware interfaces. As such
each format has an associated blob of DSP settings to make
the peripheral work. Lastly, each of these settings are provided
by Intel and need to be generated for each device's hardware
connection plus mode/format it supports. This patch does not
include the dsp setting blobs.
The current supported connections:
- digital mic array 2 channel
- digital mic array 4 channel
- Maxim 98357 amplifier
- ADI ssm4567
- NAU88L25 headset codec
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built glados. Speakers, headphones, and mic on camera decently
worked.
CQ-DEPEND=CL:*239598
Change-Id: If1a9be97573b9b160893944661790cac7df26fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7
Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313998
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12938
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Intel's SST (Smart Sound Technology) employs audio support
which may not consist of HDA. In order to define the topology
of the audio devices (mics, amps, codecs) connected to the
platform a NHLT specification was created to pass this
information from the firmware to the OS/userland.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Tested on glados. Audio does get emitted and some mic recording
works.
Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c
Original-Change-Id: If469f99ed1a958364101078263afb27761236421
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312264
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12935
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=None
BUG=None
TEST=Built and boot on kunimitsu. Check for the PL1 value over
sysfs interface
"/sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw".
Load the system with Aquarium 1000 Fish, average FPS should be
meeting target 60 with this change.
Change-Id: I8e083192e8018edc2cf8b88530df1e05ede10bde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb9aa00a4271875b5471c33883aa7da022f1cb0e
Original-Change-Id: I0c61fe1a9f76a9cf9a306240fb66d4c081d2bb5e
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314416
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/12934
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
BUG=chrome-os-partner:48017
BRANCH=none
TEST=Verify eMMC is working fine.
Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491
Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313912
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12618
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.
memmove.c came from the linux kernel, so also gets the standard
coreboot v2 license header, but gets the added attribution that it
was derived from the linux kernel. Unlike many coreboot files,
this file may not be re-licensed as GPL V3.
Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12916
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Original-Reviewed-on: https://chromium-review.googlesource.com/309122
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://review.coreboot.org/12727
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
thermal.asl was written as part of the coreboot project, so gets
the standard coreboot license header.
ec_commands.h came from the chrome ec tree, so gets the BSD license
from that tree as mentioned in the header that has been replaced.
Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12918
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12917
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12912
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Incorrect bus-core-ratio been used to generate P-state table
Original-Reviewed-on: https://chromium-review.googlesource.com/290681
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12731
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The read and write routines take a number of bytes to write, which
should be 1,2, or 4. We now return an error if an invalid size
is specified.
Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12936
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Values are taken from the vendor BIOS of my X200s. Notable effect:
Stops display from flashing during native graphics init / Linux mode
setting.
Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Register settings are the same as on newer chips (compare sandy-
bridge), just at different locations.
Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Skip everything but the final setting of PP_CONTROL, i.e. triggering
the power up. The settings with PANEL_UNLOCK_REGS are useless as no
lockable registers were touched in between. Also the loop waiting for
the panel power up to finish was a no-op as the registers with the
power timings were never filled (see follow-up commits).
Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The century byte is used by most RTC (default 0x32@nvram).
Even the century byte can disabled via ACPI it's more safe to reserve
it's space. Because some RTC will act with that byte anyhow.
Some OS overwrite it when syncronize the RTC.
Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/11853
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I74438e8032c84f4190ef49f306969f7157234001
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This continues what was done in commit a73b93157f2
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Because these platforms haven't been getting build testing, they've
missed out on some of the improvements that the other platforms have
gotten.
Enable MAINBOARD_HAS_LPC_TPM so that they will build.
Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Remove redundant call to dram_mrscommands().
Change-Id: I157915b4432093c556b538433e3337db1e9c525f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Ifa7dd593f70921a99d937104960e26100de28089
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12421
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h
- Move TPMBASE and TPM32() definitions into iomap.h
- Use "" style include for x4x.h in nortbridge files.
- Move includes of .h files out of x4x.h and into the c files that need
them.
- Protect function definitions in bootblock.
Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Ieae41cab97293831a0c49c3b472b9e6c62ba36c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12899
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.
Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream,
using google/auron and google/panther as refs.
TEST=built and booted guado with full functionality
Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12800
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12883
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
There's nothing in these files that needs to be hidden if
GOP support is disabled. Removing this allows skylake to
build when GOP support is turned off.
Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12859
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Since only X220 with i7 have the USB3 controller this was
probably overlooked.
Before this patch lspci on Linux would not show the NEC USB 3 controller
as well as the PCI bridge it is behind. After, both the bridge and the
NEC controller can be found in the output:
05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller
(rev 04)
Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331
Signed-off-by: Marian Tietz <mtcoreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/12882
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
I think this has a fairly low likelyhood of happening, but if AGESA
can't determine the voltage of the memory, it assignes a value of 255
to the variable that it later uses to read from an 3-value array. There
is an assert, but that doesn't halt AGESA, so it would use some random
value. If the voltage can't be determined, fall back to 1.5v as the
default value.
Fixes coverity warning 1294803 - Out-of-bounds read
Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12855
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This just tells the OS that it can use the 16GB of address space
at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit
physical address space.
This could be hardcoded into the UMEM definition, but doing it this way
makes it more plain what it's doing, and allows for modification
to put it just above the top of upper memory, similar to what is done
with the standard PCI region above the top of low memory.
Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12791
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
|
|
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so
disable them by default for now.
Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Make sure the latest & greatest Intel targets actually
build in our build system.
Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12463
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller
Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
This has been broken out from http://review.coreboot.org/#/c/10581/
Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/11025
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ic3df9bf7d7f3c4c39789f3f496bcb7fc2ee50931
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Since the GOP drivers aren't published in the 3rdparty blobs repo yet,
disable the GOP support for now so that abuild can build these
platforms.
Change-Id: Ic98671c163b433ebde89c8bf240ef4b2be393586
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12829
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
When microcode updates are enabled, this fixes an issue identical
to that described in GIT hash 7b22d84d:
* drivers/pc80: Add optional spinlock for nvram CBFS access
Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12063
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The AMD Family 10h/15h processors use a TSC that increments at
the P0 core frequency. Allow coreboot to query the TSC frequency.
Change-Id: I73ead4fd4af18991452d59985b667a54689778cd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12834
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This reverts commit 65e33c08a9a88c52baaadaf515b9591856115a77.
This was the wrong logic to fix the master header.
Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12824
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions. Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime. This should allow one rom to be used for all revisions.
The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues. This
seems like the best way to eliminate the need for that symbol.
Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Provide a common routine to hash the contents of a cbfs
region. The cbfs region is hashed in the following order:
1. potential cbfs header at offset 0
2. potential cbfs header retlative offset at cbfs size - 4
3. For each file the metadata of the file.
4. For each non-empty file the data of the file.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized in chromeos cros_bundle_firmware as well as at
runtime during vboot verification on glados.
Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12786
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
|
|
We will soon need to handle empty files.
Change-Id: Ia72a4bff7d9bb36f6a6648c3dd89e86593d80761
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12785
Tested-by: build bot (Jenkins)
|
|
Some of the files need to be adjusted so that they can be used
both in cbfstool as well as coreboot proper. For coreboot,
add a <sys/types.h> file such that proper types can be included
from both the tools and coreboot. The other chanes are to accomodate
stricter checking in cbfstool.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Built on glados including tools. Booted.
Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
To continue sharing more code between the tools and
coreboot proper provide cbfs parsing logic in commonlib.
A cbfs_for_each_file() function was added to allow
one to act on each file found within a cbfs. cbfs_locate()
was updated to use that logic.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.
Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Provide a helper function which returns the relative offset
between 2 region_devices that have a parent-child child relationship.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.
Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The code committed in GIT hash
* 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support
did not correctly locate the CPU MMCONFIG resource, leading to failures
with operating systems and firmware (e.g. SeaBIOS) when the PCI
extended configuration space option was activated.
Due to the southbridge routing not being set up, MMCONFIG accesses were
targetting DRAM and therefore the PCI devices were not being configured.
The failure normally manifests as a system hang immediately after PCI
configuration starts.
Search for the CPU MMCONFIG resource on all domains below the root
device.
Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12821
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
This reverts commit d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93.
Do not mix open-source AGESA and binary PI trees. Once you have
working S3 support for binaryPI platforms, add the adapted
oem_s3.c file as northbridge/amd/pi/oem_s3.c instead.
Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/12282
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/12820
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Make the low-power and small form factor (SFF) options overridable
from romstage main. Also disable both options by default. That's ok
as there aren't yet any in-tree users of the GS45 chipset. As a nice
side-effect, this adds X200s support to the lenovo/x200 port.
Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12814
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
All southbridge interrupt pin and routing registers (D*IP and D*IR)
are left at their default values (see ICH9 datasheet) and this file
just has to reflect them.
Change-Id: I687262556d918311757fda9afda9ebfdd7edf947
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12813
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef
Original-Reviewed-on: https://chromium-review.googlesource.com/262832
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Set up External Temperature to read via thermal diode/resistor
into TMPINx register by setting thermal_mode switch.
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034
Original-Reviewed-on: https://chromium-review.googlesource.com/260545
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a)
Original-Reviewed-on: https://chromium-review.googlesource.com/262340
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12798
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
The RPU Clock register defaults to on for all clocks.
This is modified to OFF, and the MIPS clock control modified to ON,
by default. This is because the linux kernel will manage the
clocks at all times, but the RPU can only disable clocks if the WIFI
module has been loaded.
Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role
of SRAM) was placed at a 4K aligned address, resulting in a size of
408KB.
Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
The base address for the I2C dividers (DIV1 and CLOCKOUT)
was erroneously set to the toplevel clock controller base
address and not to the correct peripherals clock controller
base address.
Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
This region must be mapped uncached. This is necesary for an
U-boot payload which will obtain all register base addresses
as physical addresses from the device tree and will use them
as such.
Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
When used with a U-boot payload it will need this region
identity mapped also, so we're defining it in preparation
for that functionality.
Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12768
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Use SYS PLL in integer mode by default to reduce jitter.
DSMPD_MASK is defined and can be used to switch to fractional mode.
Tested on pistachio bring up board.
Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Board uses x4x native raminit
Board boots into Debian 8 with full graphics
IRQ9: nobody cared, gets disabled
(PIC needs IRQ settings?)
VGA:
- VGA native init works in grub with analog connector
- Fails to boot with both channels of ram populated
Change-Id: I7417813456817529b8cbaace45cefe47467d0a82
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11306
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Passes memtest86+ with either one or two sticks of 2GB ram
but memory map needs a hole at 0xa0000000 to 0xc0000000
Change-Id: Ib34d862cb48b49c054a505fffcba1c17aeb39436
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11307
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Id6d50d4d6af31e43f851645f09383121755291f6
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12815
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
This code looks like it was created from a disassembly of some
other driver. Attempt to fix it, without hardware or documentation.
CID 142909: Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
Change-Id: I9b9cadf2acdba73913aad6bbe0d14ad64a652915
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12774
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
|
The FMD is board-specific, so it makes sense to have it in the
mainboard menu.
Change-Id: I52fba5ced869d51d10065f8c9ebd258d3a1d4156
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/12805
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Non-code flow assembly stubs do not have to be included in
bootblock.S, now that we have more freedom in bootblock linking.
Rather than bringing these stubs to the config system, just link them
in the bootblock.
Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this
point, as some intel SOCs use this stub for code flow.
objdump -h build/cbfs/fallback/bootblock.debug on a few random boards
confirms that the appropriate sections are still included in the
final binary.
Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/11856
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Since the introduction of the new (interim?) master header, coreboot
searches the whole ROM for CBFS entries. Fix that by aligning it on top
of the ROM.
Change-Id: I080cd4b746169a36462a49baff5e114b1f6f224a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12810
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
