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2023-06-14mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAMMatt DeVillier
One specific Hynix LPDDR5x DRAM part requires an ABL workaround to eliminate DRAM-related failures during a FAFT test, but due to the use of generic/common SPDs, there is no way for the ABL to determine the DRAM part # itself. Consequently, we will have coreboot check the DRAM part #, and set/clear a CMOS bit as appropriate, which the ABL will check in order to apply (or not apply) the workaround. The ABL already uses byte 0xD of the extended CMOS ports 72/73 for memory context related toggles, so we will use a spare bit there. BUG=b:270499009, b:281614369, b:286338775 BRANCH=skyrim TEST=run FAFT bios tests on frostflow, markarth, and whiterun without any failures. Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2023-06-14soc/intel/xeon_sp: Fix HEST table lengthJeff Li
"current" points to the start of HEST table, so "next - current" already includes the size of its header, no need for increment here. This issue was found on SPR-SP platform. The length of HEST table is now correct with this patch. Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Signed-off-by: Jeff Li <lijinfeng01@inspur.com> Signed-off-by: Ziang Wang <ziang.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-14mb/google/nissa/var/joxer: Add DmaProperty for ISHMark Hsieh
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on joxer. BUG=b:285477026 TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA-FQ After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75758 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/rex/variants/ovis: Add basic DTTJakub Czapiga
Add default Intel DPTF. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/variants/ovis: Add USB and TCSS configurationJakub Czapiga
+-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/nissa/var/joxer: Remove fw_config probe for storage devicesMark Hsieh
When fw_config is unprovisioned, devicetree will disable all probed devices. However, boot-critical devices such as storage devices need to be enabled. As a temporary workaround while adding devicetree support for this, remove the fw_config probe for storage devices so that all storage devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI scan, but keeping it enabled should have no functional impact, only a possible power impact. BUG=b:285477026 TEST=On joxer eMMC and UFS SKUs, boot to OS and `suspend_stress_test -c 10` Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I834bd81ce636a6f32d50434cbf07b1d572620492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75757 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14drivers/wwan/fm: Fix format string vulnerability with snprintfJamie Ryu
This fixes format string vulnerability issues with snprintf statement found by klocwork scan. Foundby=klocwork BUG=NONE TEST=Boot to OS on Meteor Lake rex platform and run klocwork scan. Check related ACPI tables and modem driver behavior after changes. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ia6b7d70c0b2b86d0918e58348dccd206a7ee9193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75733 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14vc/intel/fsp/fsp20/meteorlake: Add VR config entriesSubrata Banik
This patch adds UPD entries into the FSP header file to configure VRs (IA, GT and SA). - `IccLimit` : VR Fast Vmode ICC Limit support - `EnableFastVmode` : Enable/Disable VR FastVmode - `CepEnable` : Enable/Disable CEP (Current Excursion Protection BUG=b:286809233 TEST=Able to build google/rex. Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-06-13mb/google/myst: Update PCIE_RST_L driveJon Murphy
PCIE_RST_L is attached to a pull down, change the init to NC. BUG=None TEST=Boot to OS Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-13mb/google/myst: Update PCIe romstage gpiosJon Murphy
Update PCIe GPIOs during rom stage to properly initialize the PCIe devices and allow the NVMe/eMMC to be properly detected. BUG=b:284213391 TEST=Boot to OS Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-13soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bitsFelix Held
Rename get_smee_reserved_address_bits to get_sme_reserved_address_bits since the feature is called secure memory encryption and the last 'e' in SMEE bit in the SYSCFG MSR just stands for enable. The function will return a valid number of reserved address bits no matter if this is enabled or not, so drop the second 'e'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-13mb/google/brya/variants/hades: Set WP signal to GPP_E12Tarun Tuli
Move the WP signal to GPP_E12 from the current GPP_E15 to match the design. BUG=b:285084125 TEST=WP signal reports as we expect Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-13mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPDDavid Wu
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-12soc/amd/stoney: Expand the SMM region for cacheZheng Bao
Currently the data to be put to cache region is 0x14FF90. With the limit size 0x150000, the data for S3 can not be put into. So we expand it a little. Change-Id: If6b03b713059c54c7dae8f2db0f6426d8aa1aab1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69782 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/mt8188: Support 4K resolution displayHsiao Chien Sung
The original clock rate 416MHz is insufficient for 4K resolution and causing the screen to glitch. Set the clock rate to 594MHz to support 4K resolution. BUG=b:236328487 TEST=Glitching screen was fixed after applying this patch Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3 Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2Jonathon Hall
Define a CMOS layout for Librem Mini v1/v2 spanning both banks. The only setting provided is the automatic power-on setting, which is implemented by the EC. This can now be configured in a firmware image by replacing cmos.default in CBFS. Since cmos.default is applied early in bootblock, the EC BRAM interface must now be configured in bootblock, including opening the LPC I/O range. Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74363 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/common: Disable DRAM scramble by defaultYidi Lin
Geralt SoC does not support 'persist certain regions' across reboots. Considering the impact of missing ramoops for debugging, set MEDIATEK_DRAM_SCRAMBLE to default n to disable this feature in production FW image. BUG=b:269049451,b:278478563 TEST=emerge-geralt coreboot and confirm CONFIG_MEDIATEK_DRAM_SCRAMBLE=n Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/75562 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/mediatek/mt8195: Fix typo for SPIM2_MIYidi Lin
Fix a typo in an enum type name, "PIM2_MI" -> "SPIM2_MI". TEST=emerge-cherry coreboot Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: Ib43a044dc69a93ad1dcaa5e65c66a82046a40777 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-06-12acpi/acpi.c: Reduce scope of functions used locallyArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-12mb/google/rex/var/screebo: Enable touchscreenZhongtian Wu
Enable ILI2901 and eKTH7B18 touchscreen for Google Screebo. BUG=b:278167967 BRANCH=none TEST=Build and boot to Google Screebo. Verify touchscreen works. Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
2023-06-12soc/amd/smm: Sanity check the SMM TSEG sizeZheng Bao
As per AMD64 Architecture Programmer's Manual, section 10.2.5 SMRAM Protected Areas: The TSEG range must be aligned to a 128 Kbyte boundary and the minimum TSEG size is 128 Kbytes. The SMM TSEG size should be less than SMM reserved size. AMD TSEG mask works like an MTRR. It needs to be aligned to it's size and it's size needs to be a power of 2. Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75405 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-12mb/intel/mtlrvp: Add CPU power limit valuesSumeet Pawnikar
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for mtlrvp baseboard. BRANCH=None BUG=None TEST=Built the changes Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-12mb/google/brya/var/hades: Abort power on if any rails fail to come upTarun Tuli
Currently if a rails PG fails to assert, the power on sequence continue after the 20ms timeout. Instead, we should abort and enter a power down. BUG=b:285980464 TEST=sequence now aborts and powers down on failure Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-12soc/amd/block/ivrs: Generalize IVRS table generationNaresh Solanki
This commit introduces a refactored version of the IVRS (I/O Virtualization Reporting Structure) table generation. The main objective of this refactoring is to generalize the process of generating the IVRS table based on the IOMMU (Input/Output Memory Management Unit) domains and their corresponding resources. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75451 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12mb/google/rex/variants/ovis: Enable EC in device treeJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-12mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx railsMark Hsieh
This patch configures external V1p05/Vnn/VnnSx rails for Joxer to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:285477026 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-06-11arch/riscv: Add clang as supported architectureArthur Heymans
All emulated targets properly compile and boot to the same extent as with gcc. Change-Id: I11ddd9347c2638fb7c26cd4939aa96ff8ddd1e66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74571 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Daniel Maslowski <info@orangecms.org>
2023-06-11arch/riscv: Always build opensbi with GCCArthur Heymans
Building with clang is currently broken as /usr/bin/ld.bfd is used rather than the proper crosstoolchain linker. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Idd8006a26b2c2f9f777fdffe231c3c774320d805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75397 Reviewed-by: Daniel Maslowski <info@orangecms.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-11arch/risc/mcall.h: Make the stack pointer globalArthur Heymans
Clang complains about the stack pointer register variable being uninitialized. This can remediated by making the variable global. Change the variable name to be more unambiguous. Change-Id: I24602372833aa9d413bf396853b223263fd873ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74570 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Daniel Maslowski <info@orangecms.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entryTarun Tuli
Properly shutdown NV12 rail in the off sequence (current implementation leaves it asserted). BUG=b:286287940 TEST=NV12 now shuts down on GCOFF entry Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75533 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-09mb/google/myst: Add pen detect supportJon Murphy
Add pen detect support on the SOC pen detect GPIO. BUG=b:286296762 TEST=Verify pen detect works on Myst Change-Id: I922d643a83c5cd8ea0ab9fe6733f7aa05d935802 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-09acpi: Add struct for SPCR tableArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I46d5caa0af95ec27fd49b0cf8fa704d656c89e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75684 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09mb/google/nissa/var/uldren: Modify WWAN power sequenceDtrain Hsu
Follow spec[1] to modify WWAN power sequence. The WWAN power sequence of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD reset when warm reset. [1]: [JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing Review_V1.6_20230602.xlsx BUG=b:285065375 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power sequence meets spec. Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75690 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09mb/google/nissa/var/yavilla: Enable wifi SARShon Wang
Enable wifi sar function for yavilla/yavilly/yavijo. Use the fw_config to separate SAR setting for different wifi card. BUG=b:286141046 BRANCH=firmware-nissa-15217.B TEST=build, enabled iwlwifi debug, and check dmesg Change-Id: I1bd111a734a250df49535a07ef056d5b68fccb33 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-09mb/google/brya/var/vell: Generate SPD ID for supported memory partShon Wang
Add new memory parts DRAM Part Name ID to assign Hynix H58G66AK6BX070 3 (0011) Hynix H9JCNNNFA5MLYR-N6E 4 (0100) Micron MT62F2G32D8DR-031 WT:B 4 (0100) BUG=b:279325772 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I2e6a916de08e7c05e95909d2b69bc839d13192d9 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74713 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-09mb/google/dedede/var/taranza: Update memory part and generate SPD IDSheng-Liang Pan
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AB-MGCL 2. K4UBE3D4AB-MGCL BUG=b:285504022 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I87a4dcdb6196c3ca7bed4b5c1bc654297339c16d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75605 Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILEFelix Held
The file VGA_BIOS_FILE points to is right now the Mendocino VBIOS. Since the default value probably shouldn't point to a location in site-local, drop this for now, but leave a TODO to put that back once the correct VBIOS files are available in 3rdparty/amd_blobs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifbc6cbe1e371d8d247f86555a5361ed237897dea Reviewed-on: https://review.coreboot.org/c/coreboot/+/75484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-09soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetreeFelix Held
Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. TEST=SSDT entries for the XHCI controllers are still generated on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-08mb/google/myst/bootblock.c: Initialize spi flashFred Reitberger
Initialize the SPI Flash in bootblock to ensure that CONFIG_SPI_FLASH_EXIT_4_BYTE_ADDR_MODE will exit 4-byte addressing mode. BUG=b:285110121 TEST=boot myst and verify flash operations work correctly Change-Id: Ia88d2b46884b096b4c558bc86513159ec6d35eb5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75588 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-08mb/google/brya/var/kano: Add Micron MT53E2G32D4NQ-046 WT:C SPDDavid Wu
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I0abf1f1105f9a6f16af23b0ed3eb4faeb669eee6 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75716 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-08mb/google/brya: Enable GPU ACPI for HadesTarun Tuli
Include the GPU ACPI methods for all of Hades baseboard. BUG=b:285981616 TEST=built for Hades and verify shutdown works Change-Id: Iec3c4b59a9e7a9d4a902db51d40b60e114521774 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-08soc/amd/stoneyridge/acpi/northbridge: drop _STA method from PCI0 scopeFelix Held
The PCI root complex itself isn't on an enumerable bus, so without providing an _STA method, the device will still be assumed to be present and visible, so this won't change behavior. This also brings Stoneyridge more in line with the newer SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I663c7bcba89ffe25d0819d83461cb95e10f49028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75671 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-08soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scopeFelix Held
The PCI root complex itself isn't on an enumerable bus, so without providing an _STA method, the device will still be assumed to be present and visible, so this won't change behavior. This also brings Picasso more in line with Cezanne and newer SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-08soc/amd/phoenix: Hook up xhci ops in chipset.cbEric Lai
Hook up xhci ops for Phoenix xHCI device. Benefit is we don't have to bother by adding xhci DID. BUG=b:285981912 TEST=check coreboot log shows below. [INFO ] \_SB.PCI0.GP41.XHC0.RHUB.SS01: USB3 Type-A Port A0 (MLB) Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-07mb/google/myst: Correct CROS_WP_GPIO to active highEric Lai
HW has invert the signal, set it to active high. BUG=b:285964562 TEST=check crossystem wpsw_cur change as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75628 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-06-07soc/intel/common: Make get_ramtop_addr non staticPratikkumar Prajapati
Make get_ramtop_addr not static to allow other code to use it. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I8ef8a65b93645f25ca5e887342b18679d65e74b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-07mb/google/myst: Enable USB WWANEric Lai
Add usb wwan device tree entry. Also set wwan_rst to high due to HW design active high. BUG=b:285792436 TEST=check FM101 is detected by Linux kernel. Bus 002 Device 002: ID 2cb7:01a2 Fibocom Wireless Inc. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0aa60cb284d4b7f99e16643a92ee58467a355026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75660 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/myst: Enable fingerprint on UARTEric Lai
Add fingerprint into device tree. Also set RST to low per HW requirement. BUG=b:285799911 TEST=check ectool --name=cros_fp version. RO version: bloonchipper_v2.0.5938-197506c1 RO cros fwid: CROS_FWID_MISSING RW version: bloonchipper_v2.0.14348-e5fb0b9 RW cros fwid: bloonchipper_14931.0.0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75629 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/*/root_complex: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I16179a37b6ee19bc3b4862b7dcb3bbc4caf63f2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07soc/amd/stoneyridge/acpi/sb_pci0_fch: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94ad285a2c5712d352d4f92697fc3140847d88de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75667 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/stoneyridge/northbridge: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6303e5a697a7ad09a48cb7a2c79fa76f4c6ce232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07nb/amd/pi/00730f01/northbridge: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie558de02cd4f8914409639a74c54b57df3418ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75665 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07sb/amd/pi/hudson/acpi/fch: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3cb150aee8030d1a419f3596ddbc32cb29f65b52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07mb/google/brya/var/redrix: Add new GFX device with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Change-Id: Ia083617c58d6b7ebc108e07e29a1c8061580eae5 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-07soc/amd/glinda/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I373c171f7f4754391012b41d44965561ced4f0b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75595 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/phoenix/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If293188fc8d0ff41b47ab84c9655333e9ebe58e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/mendocino/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6fc4b09f79e633208ab7536543c876c2c6129eb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75593 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/cezanne/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75592 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/rex/variants/ovis: Add SSD card configJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I3795313e784595ac02ee2a38f466bcb9e613a6a4 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75576 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jan Dabros <dabros@google.com>
2023-06-07mb/google/rex/variants/ovis: Add I2C configJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75503 Reviewed-by: Jan Dabros <dabros@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-07mb/google/rex/variants/ovis: Add GPIO configurationJakub Czapiga
Based on Platform Mapping Document for Ovis (go/ovis_mapping_doc) state for June 6, 2023 (Rev 0.3) BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Iae3ca243a245928e8ec3d48877cf578843922fc7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75502 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/nissa/var/joxer: disable PCIE RP7Mark Hsieh
joxer removed SD card from all SKUs, thus disable pcie_rp7. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3486d665ddb1de521ab4e656addb2209055174c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75658 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/nissa/var/joxer: Remove VBOOT_GSC_BOARD_ID configReka Norman
Board IDs are now filled in as part of the signing process, so we don't need to set them in coreboot. BUG=b:240620735 TEST=Build and check VBOOT_GSC_BOARD_ID is set to ZZCR. Change-Id: I7dda8ad59046a1dd9a28595e037eda86e91c98df Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75641 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07security/intel/cbnt: Remove unneeded go stepsArthur Heymans
This updates the go modules in the intel-sec-tools git submodule. This is not needed. Change-Id: I2012d519b07321317fef415df892bbb966512ee2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55845 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.aslFelix Held
This file only contain the ACPI code describing the MMIO devices in the FCH, so rename it to mmio.asl. This also brings the Stoneyridge ACPI code a bit more in line with the ACPI code of the other SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iccef1fc5230e3e104d8dea586a9cbaf894471c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75597 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macroFelix Held
Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75596 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07soc/amd/picasso/acpi: rename sb_fch.asl to mmio.aslFelix Held
This file only contain the ACPI code describing the MMIO devices in the FCH, so rename it to mmio.asl. This also brings the Picasso ACPI code a bit more in line with the ACPI code of the newer SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I64490ba8e34ae1fbe6aea1ab6496b5b04ac4d0aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75591 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/picasso/acpi: move remaining parts of sb_pic0_fch.asl to soc.aslFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785abfc90c99b58c11d57847573f550fcea1f774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07soc/amd/picasso/acpi: use ROOT_BRIDGE macroFelix Held
Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. TEST=Both Ubuntu 2022.4 and Windows 10 still boot successfully and don't show any new ACPI-related error. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2587d8bb270dc3edce9dfa570a5018116fc9187f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macroFelix Held
When instantiated in the DSDT, this macro will expand to the static part of the PCIe root bridge device. This macro allows both to deduplicate parts of the DSDT code as well as adding more than one PCIe root bridge device in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75568 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/acpi: move acpi_fill_root_complex_tom to StoneyridgeFelix Held
Now that Stoneyridge is the only AMD SoC that still needs the part of the SSDT that contains the TOM1 and TOM2, move it from the common code to the Stoneyridge northbridge code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9091360d6a82183092ef75417ad652523babe075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75564 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/glinda/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I948d882b2e2c6d19f73c0be094e4ff6e42ec81d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75560 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/phoenix/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. BUG=b:283495475 TEST=Myst still boots and both the coreboot console and the kernel show the expected PCI MMIO ranges being used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I425876c4ef470574e00e123d36101641240c98cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/75559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/mendocino/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad34d74d9f6cbed1d8a71a561a505f563e31db18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/cezanne/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/common/data_fabric/domain: write _BBN method in SSDTFelix Held
Instead of having PCI0's _BBN method in the DSDT that always returns 0, use acpigen_write_BBN to generate the _BBN method that returns the first PCI bus number in the PCI domain/host bridge. TEST=On mandolin the _BBN method in the _SB/PCI0 scope is now in the SSDT instead of the DSDT, but still returns 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8badeb0064b498d3f18217ea24bff73676913b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74992 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/picasso/chip: use common data fabric domain resource codeFelix Held
Use amd_pci_domain_read_resources function that gets the configured MMIO regions for the PCI root domain from the data fabric's MMIO decode registers instead of using pci_domain_read_resources. This results in the same IO port range being used by the allocator, but makes sure that the allocator will only allocate non-fixed MMIO resources in the address ranges that get decoded to the PCI root complex. In order for the PCI0 _CRS ACPI resource template to match the decoded PCI root domain MMIO windows, use amd_pci_domain_fill_ssdt to generate the _CRS ACPI code instead of having a mostly hard-coded _CRS method in the DSDT. This makes sure that the OS will know about the MMIO regions it is allowed to used. Before this patch, only the region from TOM1 to right below CONFIG_ECAM_MMCONF_BASE_ADDRESS was advertised as usable PCI MMIO in the PCI0 _CRS method. Also the resource allocator didn't get any constraint on which address ranges it can use to put the non-fixed MMIO resources. This approach worked until now, since all address range from 0 up to right below TOM1 was filled with either usable or reserved memory and the allocator was allocating beginning right from TOM1, since it was using the bottom-up allocation approach and everything below TOM1 was already in use. The MMIO region from TOM1 to right below CONFIG_ECAM_MMCONF_BASE_ADDRESS also matched the MMIO decode window configured in the data fabric's MMIO decode registers, so everything seemed to work fine. However, when either selecting RESOURCE_ALLOCATION_TOP_DOWN or enabling above 4GB MMIO, things broke badly. This was partially due to the allocator putting non-fixed MMIO resources in regions that weren't decoded to the PCI root, since AMD family 17h and 19h silicon doesn't subtractively decode PCI MMIO and the wrong ranges the allocator used also weren't advertised in ACPI. TEST=Even when selecting RESOURCE_ALLOCATION_TOP_DOWN that usually ends up with a non-working system when the MMIO ranges aren't reported correctly to the resource allocator due to the reasons descried above, Ubuntu 22.04 LTS still boots on Mandolin both with SeaBIOS and EDK2 payload and Windows 10 boots with EDK payload. There's however an EDK2 bug that results the MMCONFIG region not being advertised in the e820 table, which causes Linux to not use the MMCONFIG and fall back to the legacy PCI config access method. This only happens with EDK2 payload and everything works fine when using SeaBIOS as payload. That e820 issue is unaffected by this patch. At the end of the data_fabric_set_mmio_np call, this is the data fabric MMIO register configuration: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 The limit of the data fabric MMIO decode register 1 is configured as 0xffffffffffff although this is way beyond the addressable memory space. add_data_fabric_mmio_regions fixes this up, so the range that gets passed to the allocator in that case is 0x7fcffffffff which takes both the reserved most significant address bits used for the memory encryption and the 12GB reserved data fabric MMIO at the top of the usable address space into account. This results in the following domain ranges passed to the resource allocator: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: fc000000 size: 0 align: 0 gran: 0 limit: febfffff DOMAIN: 0000 mem: base: 10000000000 size: 0 align: 0 gran: 0 limit: 7fcffffffff DOMAIN: 0000 mem: base: d0000000 size: 0 align: 0 gran: 0 limit: f7ffffff The IO resource producer region is split into two parts to not cover the PCI config IO region resource consumer. This results in these resources being added to the PCI0 _CRS resource template: amd_pci_domain_fill_ssdt ACPI scope: '\_SB.PCI0' PCI0 _CRS: adding busses [0-3f] PCI0 _CRS: adding IO range [0-cf7] PCI0 _CRS: adding IO range [d00-ffff] PCI0 _CRS: adding MMIO range [fc000000-febfffff] PCI0 _CRS: adding MMIO range [10000000000-7fcffffffff] PCI0 _CRS: adding MMIO range [d0000000-f7ffffff] PCI0 _CRS: adding VGA resource Kernel version 5.15.0-43 from Ubuntu 2022.4 LTS prints this in dmesg: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00-3f] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff window] pci_bus 0000:00: root bus resource [mem 0xfc000000-0xfebfffff window] pci_bus 0000:00: root bus resource [mem 0x10000000000-0x7fcffffffff window] Another noteworthy thing I wasn't aware of at first when testing ACPI changes on Windows 10 is that a normal Windows shutdown and boot cycle won't result in it processing the changed ACPI tables; you have to tell it to reboot to do a proper full boot where it will process the updated ACPI tables (and fail if it dislikes something about the ACPI tables and bytecode). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia24930ec2a9962dd15e874e9defea441cffae9f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74712 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-07soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdtFelix Held
Generate the PCI0 _CRS ACPI resource template to tell the OS which PCI bus numbers and IO and MMIO regions can be used for PCI devices below _SB/PCI0. This data corresponds to what amd_pci_domain_scan_bus and amd_pci_domain_read_resources provided to the resource allocator. This makes sure that the PCI0 _CRS ACPI resource template matches the constraints the resource allocator used when allocating resources. TEST=With also the rest of the current patch train applied, the generated _CRS resource template contains the expected PCI bus numbers and IO and MMIO resources and both Linux and Windows boot on Mandolin. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74843 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-06-07acpi/acpigen: generate DWord IO resource in acpigen_resource_producer_ioFelix Held
When an IO resource producer is generated that covers the whole IO space from 0 to 0xffff, the length field in the word resource ACPI type would overflow and be truncated which results in Linux not finding any usable IO space to use for the PCI IO BARs. Instead generate a double word IO resource producer to have all cases supported. Beware that covering all IO ports with the IO resource producer while covering the PCI config IO ports with a resource consumer in the same PCI root device will make Linux a bit unhappy and it will complain due to the overlap, but still end up doing the right thing: acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored The SoC code should make sure to carve out the PCI config IO ports from the IO resource producer. TEST=Both Ubuntu 2022.04.1 LTS and Windows 10 are ok with the IO DWord resource producer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75613 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/data_fabric/domain: provide scan_bus and read_resourcesFelix Held
Provide amd_pci_domain_scan_bus to enumerate the PCI buses in the one PCI root domain and amd_pci_domain_read_resources to read the MMIO regions that the resource allocator can use to allocate the PCI MMIO BARs in the one PCI root domain from the corresponding data fabric MMIO decode registers. This makes sure that the allocator will only put PCI MMIO resources in areas that are decoded to the PCIe root complex. The current code only covers the case of a system with one PCI root where all PCI bus numbers belong to the only PCI root, all IO ports get decoded to the only PCI root and the MMIO regions from the data fabric MMIO decode registers get decoded to the only PCI root. In future patches, this will be extended to also support the multi PCI root case. TEST=With also the rest of the current patch train applied, the resource allocator uses the constraints on the MMIO regions and both Linux and Windows boot on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4aada7c8a2a43145ad08d11d0a38d9cdc182b98e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74717 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/block/cpu/noncar: add get_usable_physical_address_bits()Felix Held
In case the secure memory encryption is enabled, some of the upper usable address bits of the host can't be used any more. Bits 11..6 in CPUID_EBX_MEM_ENCRYPT indicate how many of the address bits are taken away from the usable address bits in the case the secure memory encryption is enabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia810b0984972216095da2ad8f9c19e37684f2a2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75623 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/block/cpu/noncar/cpu: add missing types.h includeFelix Held
types.h provides uint32_t via a chain include. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I875e3bb096b56bbea862c9ad0e3e14e025e3298b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75622 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06drivers/spi/winbond.c: Add W25Q256JW_DTR partFred Reitberger
BUG=b:285110121 TEST=boot Myst and verify the flash is recognized Change-Id: I30aed5299f87f7cf02fe9a5569edd2b8dcf7b452 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-06drivers/spi/spi_flash.c: Print the flash ID when find_match failsFred Reitberger
Print the flash ID codes when find_match fails to match the flash. BUG=b:285110121 Change-Id: I2106abfcfbd44c7d56d48ffbb43d8c76089af076 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-06soc/intel/common/crashlog: Add support for IOE diePratikkumar Prajapati
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die. SRAM from this IOE die contains crashlog records for the IPs of the IOE die. This patch adds functions with empty implementation using __weak attribute for IOE die related crashlog, changes common data structures while maintaining backwards compatibility, and support for filling IOE crashlog records, guarded by SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data function as weak because it needs SOC specific implementation. Bug=b:262501347 TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06soc/amd/stoneyridge/northbridge: reserve PCI config IO portsFelix Held
This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75619 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-06soc/amd/*/root_complex: reserve PCI config IO portsFelix Held
This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-06arch/x86/include/arch/vga: add defines for VGA MMIO addressesFelix Held
To avoid magic constants in the code, add defines for the VGA MMIO address range from 0xa0000-0xbffff. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Reviewed-on: https://review.coreboot.org/c/coreboot/+/75618 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/rex/var/rex0: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06soc/intel/xeon_sp/spr: Add RMT configNaresh Solanki
This commit adds a configuration option to enable RMT in the coreboot build for the Intel Xeon SP SPR platform. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-06mb/google/kukui: Change Juniper/Willow RAM table offset to 0x30Sheng-Liang Pan
All the DRAM module for Juniper/Willow can reuse the RAM ID in offset 0x30 table, so change Juniper/Willow RAM table offset to 0x30 for introducing more DRAM modules. BUG=b:284423187 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-06-06mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7Dtrain Hsu
Uldren does not have PCIE device and should disable PCIE RP7 and GPP_D7 for preventing PCIe controller not power gate in S0ix. BUG=b:283735051 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage 1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6' [SPEW ] PCI: 00:1c.6: enabled 0 [SPEW ] PCI: 00:1c.6: enabled 0 2. GPP_D7: iotools mmio_read32 0xfd6d0ab0 0x44000300 Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75644 Reviewed-by: Harsha B R <harsha.b.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-06mb/google/rex/variants/ovis: Add RAM IDsJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06mb/google/rex: Create ovis variantJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/corsola/var/starmie: Add K&D-ILI9882T panel supportRuihai Zhou
The K&D-ILI9882T panel and STA-ILI9882T share all DCS commands and EDID information except for the manufacturer_name which has no effect to the function of panel. Let's reuse the STA_ILI9882T struct in this case. BUG=None TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I510462a49d273f3d25158b25906d4c514f855cdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/75479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-06-06mb/google/geralt: Fix MIPI panel power on/off sequenceRuihai Zhou
Based on the power sequence of the panel [1], the power on T2 sequence VSP to VSN should be larger than 1ms, and the power off T2 sequence VSP to VSN should be larger than 0ms. We modify the power sequence to meet the datasheet requirement. [1] B5 TV110C9M-LL0 Product Specification Rev.P0 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-06-06soc/intel/meteorlake: Fill PCI SSID parametersKapil Porwal
Set SSID UPD to program DID as SSID for all the on board PCIe devices if SSID is not being overridden by CONFIG option or device tree. BUG=b:263846223 TEST=Verify that SSID for all PCI devices is same as their respective DIDs. Output of lspci in the OS: 00:00.0 0600: 8086:7d02 (rev 01) Subsystem: 8086:7d02 00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller]) Subsystem: 8086:7d45 00:04.0 1180: 8086:7d03 (rev 01) Subsystem: 8086:7d03 00:05.0 0480: 8086:7d19 (rev 01) Subsystem: 8086:7d19 00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e4d Capabilities: [98] Subsystem: 8086:7e4d 00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec4 Capabilities: [90] Subsystem: 8086:7ec4 00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec6 Capabilities: [90] Subsystem: 8086:7ec6 00:0a.0 1180: 8086:7d0d (rev 01) Subsystem: 8086:7d0d 00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI]) Subsystem: 8086:7ec0 00:0d.2 0c03: 8086:7ec2 (prog-if 40) Subsystem: 8086:7ec2 00:0d.3 0c03: 8086:7ec3 (prog-if 40) Subsystem: 8086:7ec3 00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI]) Subsystem: 8086:7e7d 00:14.2 0500: 8086:7e7f (rev 01) Subsystem: 8086:7e7f 00:14.3 0280: 8086:7e40 (rev 01) Subsystem: 8086:0094 00:15.0 0c80: 8086:7e78 (rev 01) Subsystem: 8086:7e78 00:15.1 0c80: 8086:7e79 (rev 01) Subsystem: 8086:7e79 00:15.3 0c80: 8086:7e7b (rev 01) Subsystem: 8086:7e7b 00:16.0 0780: 8086:7e70 (rev 01) Subsystem: 8086:7e70 00:19.0 0c80: 8086:7e50 (rev 01) Subsystem: 8086:7e50 00:19.1 0c80: 8086:7e51 (rev 01) Subsystem: 8086:7e51 00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e3e Capabilities: [98] Subsystem: 8086:7e3e 00:1e.0 0780: 8086:7e25 (rev 01) Subsystem: 8086:7e25 00:1e.3 0c80: 8086:7e30 (rev 01) Subsystem: 8086:7e30 00:1f.0 0601: 8086:7e04 (rev 01) Subsystem: 8086:7e04 00:1f.3 0401: 8086:7e28 (rev 01) 00:1f.5 0c80: 8086:7e23 (rev 01) Subsystem: 8086:7e23 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06mb/google/rex/var/rex0: probe for i2c1 touchscreenEran Mitrani
Touchscreen may either use I2C1 or SPI0. FW_CONFIG.TOUCHSCREEN is set to determine which is used. This CL adds a probe to enable I2C1. BUG=b:278783755 TEST=Tested on rex, confimed i2c1 is disabled when TOUCHSCREEN != TOUCHSCREEN_I2C Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06soc/amd/phoenix: Update USB device aliasEric Lai
Follow 57263_FP8_MBDG_rev_0_92 Table.57 to update the alias. We can match the schematic for now. BUG=b:285793461 TEST=USB still works. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Id1058279fe5b0e3131608a0b9bbd708dbbde7e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-06vboot: Drop argument to select slot from `vb2ex_ec_protect()`Subrata Banik
vboot code changes have eliminated the redundant call to WP the EC-RO region as protecting RW flash implies protecting both RO and RW flash, so the call to protect RO is redundant. google/rex currently takes about 17 ms to lock down the EC. Along with vboot changes, this patch drops argument to choose between RO and RW slot to protect while calling into `vb2ex_ec_protect()`. It ensures vb2ex_ec_protect() is explicitly meant for protecting RW regions. w/o this patch: 517:waiting for EC to allow higher power draw 846,196 (17,297) w/ this patch: 517:waiting for EC to allow higher power draw 838,258 (9,719) Additionally, update vboot submodule to upstream main to avoid the compilation error. Updating from commit id 35f50c3154e5: Fix build error when compiling without -DNDEBUG to commit id 034907b279c9db: vboot_reference: eliminate redundant call to write protect EC-RO Change-Id: I2974f0cb43ba800c2aaeac4876ebaa052b5ee793 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>