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2019-11-01mb/facebook/fbg1701: Remove confusing text boxes from menuWim Vervoorn
The Kconfig contained some items that were only intended to set a default and that now were displayed in two locations in the menuconfig. BUG=N/A TEST=build Change-Id: If5d9c993c03a0e901fd6c2a2107a6be6b94d063b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36481 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01mb/google/drallion: Add second touch pad supportEric Lai
Add second source touch pad with i2c address 0x15. BUG=b:142629138 BRANCH=N/A TEST=check new touch pad can work properly Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-01mb/intel/saddlebrook: Enable Chipset_lockdown coreboot configPraveen Hodagatta Pranesh
This patch enables lockdown configuration for saddlebrook platform BUG=None TEST=Boot to Linux on saddlebrook and verified MRC is restored on warm, cold, resume boot path's. Change-Id: Ia324c118b0c8e72b66a757dee5be43ba79abbeab Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01mb/intel/saddlebrook: Select coreboot MP initPraveen Hodagatta Pranesh
use coreboot MP init for saddlebrook by default. BUG=None TEST=Boot till yocto linux 2.7 on saddlebrook and verified the AP's proper initialization using 'cat /proc/cpuinfo' command. Change-Id: I2db2fe92c8ba0e649dccf95ce804a97ae4a05603 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01soc/skylake/vr_config: fix VR config for KBL-U CPUsMaxim Polyakov
These changes are in accordance with the documentation: [1] page 106, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006 Change-Id: I5232a7a670b97d51ff3b3b71a08f25f961ac1d6f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36058 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01soc/intel/{cnl,icl,skl}: Move ipu.asl into common/block/acpiSubrata Banik
This patch creates a common instance of ipu.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer ipu.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(IMGU) presence after booting to OS. Change-Id: I4d18571008c199fd5c3dbeed8cba9374520359b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/Subrata Banik
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpiSubrata Banik
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and asks specific soc code to refer lpc.asl from common code block. Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather than LPC. TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS. Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01arch/acpi.h: Use the predefined typedef acpi_addr_tHimanshu Sahdev
Use already declared typedef and modify the usage accordingly. Change-Id: Icc8413050bfae896d78605416aaaaa6a52eb39f1 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-01vendorcode/eltan/security: Use vb2 public keyWim Vervoorn
Start using the vb2 public key format and process the signature verification using the vb2 routines. This allows us to use the futility to prepare the keys and eliminates the need for custom tools. BUG=N/A TEST=tested on fbg1701 board Change-Id: Id5d28595bbfb1f5ca5bca0fcfb06134bb1143f25 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01mb/google/kukui: Unselect FATAL_ASSERTElyes HAOUAS
FATAL_ASSERT is used for debugging purpos. Don't select it by default. Change-Id: If4d521827f3d50fb662b89b24d00fb0517e7af2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-01mb/portwell/m107: Remove Intel wifi disableWim Vervoorn
The Intel wifi drivers were disabled by default. This should not be done here as the baseboard defines if this present or not. BUG=N/A TEST=build Change-Id: I364a821f8387d580b1fbfb7cf77b32a3a6dceebb Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36503 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01mb/portwell/m107: Add Kingston memory supportWim Vervoorn
Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01mb/facebook/fbg1701: Disable Intel wifiWim Vervoorn
The facebook fbg1701 never contains Intel wifi functionality so this can be disabled. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: Iab7dd760020cb7a9f7fea24812afb19bf5e62183 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01lib/uuid: Add UUID parsing functionNico Huber
Implement a simple function that parses a canonical UUID string into the common byte representation. Inspired by acpigen_write_uuid(). Change-Id: Ia1bd883c740873699814fde6c6ddc1937a40093e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>'Elyes HAOUAS
Change-Id: Ia15824effc8f846ff1143abe698c5a0546df7868 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36489 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01soc/intel/fsp_baytrail: Remove unused 'barrier()'Elyes HAOUAS
Change-Id: I4330fd9b2ec6ca36beae3213642f7a4ae61f7dbe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-01nb/intel: Remove unused 'barrier()'Elyes HAOUAS
Change-Id: I0c33a1f3f9c33c15a901fe90258ed989e9641701 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-01sc7180: support bitbang UART w/gpioT Michael Turney
Change-Id: I21b149500849eceea663d18a0880c6443ae47d9b Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35498 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01trogdor: Add mainboard gpio supportT Michael Turney
Change-Id: I06cdb8eaaf7f74b47e1d1283dcaa765674ceaa45 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36070 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01sc7180: Add gpio driverTaniya Das
Add support for gpio driver for SC7180 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/30003/25 https://review.coreboot.org/c/coreboot/+/31083/15 Change-Id: I12bdbeb97765b6ae1e015ca35108008bf82801cc Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-31soc/intel/skylake: Remove unused ASL debug optionsSubrata Banik
This patch removes unused TRAP, Port 80 debug options carried from previous platform (BDW). Change-Id: I91ccb24a7f08f9a19f6e3a7609c8f43776700a4e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36466 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/{cnl,icl,skl}: Fix multiple whitespace issueSubrata Banik
Change-Id: I1e3dc1bd36c5de4e58eef6a3ba8ccbde28fba64b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36465 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/{cnl,icl,skl}: Remove unused SMI opregionSubrata Banik
TEST=Able to build and boot Hatch and DE. Change-Id: I6d63c005873fc5d67b4a44f42bb436628d7c1dc3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36462 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31Makefile, Kconfig: Add AMD dependency for amd_blobs repoMarshall Dawson
Add a Kconfig option for indicating agreement to use the contents of amd_blobs. Users should only download the repo after implicitely agreeing to AMD's License text. No formal documented agreement is required. Update Makfile.inc, similar to other submodules, to initialize and checkout the submodule once the Kconfig option is selected. Change-Id: I4ae807659db16756453dc3db2c51848291c681b8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-31mb/google/drallion: Turn off HDMI power when enter s0ix and S5Eric Lai
Turn off HDMI power when enter s0ix and S5. BUG=b:143057255 BRANCH=N/A TEST=Measure the power on GPP_E16 under s0ix and S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I580e6094d48663d5c208fd82c7744485d899bcc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36224 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31ec/google/chromeec: Add EC driver support for software syncTim Wawrzynczak
Quite a few new functions added here in order to support the use-case of performing EC software sync within coreboot. Most of these functions are related to retrieving the EC's hash, and writing a new image into the EC's flash. BUG=b:112198832 BRANCH=none TEST=With whole patch series, successfully performed EC software sync Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-31soc/intel/common: add common function to set LT_LOCK_MEMORYMichael Niewöhner
Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which locks most of the chipset BAR registers in accordance to Intel BWG. Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-31cpu/x86: make set_msr_bit publicly availableMichael Niewöhner
Haswell and model_2065 implement a static set_msr_bit helper which should be publicly available instead. Move it to cpu/x86. Change-Id: I68b314c917f15fc6e5351de1c539d5a3ae646df8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36338 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31mb/asrock/h110m: configure SuperIO Deep SleepMaxim Polyakov
Change-Id: I10766ffda67bdc830ab01436ebd0578c79f1ec70 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-31soc/intel/icelake: adapt FSP GOP param to match the other FSP2.0 platformsMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I5993e64631f86ff0f9ae069e10b89df8bc4cd085 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-31soc/mediatek/mt8183: Disable DRAM DVFS in recovery modeYu-Ping Wu
Currently full calibration with DVFS (which implies tripling memory training time for multiple frequencies) will be run in recovery mode, which takes up to 30 seconds with serial console enabled. However, in recovery mode the system should be running only the recovery programs with minimal services. DVFS should be not needed. In order to improve stability and system boot time, we want to disable DVFS training in recovery mode. BRANCH=kukui BUG=b:142358843 TEST=emerge-kukui coreboot Change-Id: I4f1b1b020eba9bfce21655169bcb31b98d54b010 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36456 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/icelake: Enable caching on SPI memory-mapped boot device ↵Subrata Banik
unconditionally Icelake platform doesn't support booting from any other media (like eMMC on APL/GLK platform) than only booting from SPI device and on IA platform SPI is memory mapped hence enabling temporarily cacheing on memory-mapped spi boot media. Also removed inclusion of unused header in cpu.c file TEST=Able to build and boot ICL DE board. Change-Id: I46d9ec054c4804ca756f2101085a55e91b5cc6f0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36431 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30sb/intel/common: Make linking pmbase.c conditionalArthur Heymans
Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33200 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30sb/intel/common/Makefile: Use 'all' class to link files in all stagesArthur Heymans
This links the reset function, the common pmbase functions and the spi driver in all stages. The RTC code is not included in SMM as it is unused there. Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30mb/google/hatch/variants/helios: Modify DPTF parametersKane Chen
Modify DPTF parameters. Modify TDP PL1 values to 15. Remove TCHG Level 3 - 0.5A. BUG=b:131272830 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30src/southbridge: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30Program loading: Handoff cbmem_top via calling argumentsArthur Heymans
There are a lot of different implementations to pass information from romstage to ramstage. These could all be unified by passing this information via cbmem. Often however these methods exist for that very purpose. This solves this by passing cbmem_top via the programs arguments. Change-Id: Id2031f7bb81ce65fc318313c270eb1fbae3b2114 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36272 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30arch/x86/boot.c: Pass arguments when running programsArthur Heymans
Payloads can use coreboot tables passed on via arguments instead of via a pointer in lower memory. Stages can make use of the argument to pass on information. Change-Id: Ie0f44e9e1992221e02c49d0492cdd2a3d9013560 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36143 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30soc/intel/apollolake: set FSP param to enable or skip GOPMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I3546371dd18120e3fbd1179a79b2bdc0a7436726 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30soc/intel/cannonlake: set FSP param to enable or skip GOPMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I7f7b2c688e46534046dc0976458c4c96614100b0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30soc/intel/common: move common memmap functionality from skl,icl,cnl,aplMichael Niewöhner
This moves common memmap functionality from skl,icl,cnl,apl to the common tree. Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30arch/x86/Makefile.inc: Use the 'all' target to add common sourcesArthur Heymans
Change-Id: Ibbd418656c32f56be2b00481068e8499421b147c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30hatch: refactor gpio table into baseboard, allow empty SPDsPaul Fagerburg
Each variant needed to define variant_early_gpio_table(), even if it didn't need to make any changes. Added a __weak version of the function into baseboard/gpio.c. Certain upcoming Hatch variants will not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Change-Id: Ie946cfd7c071824168faa38fd53bd338a5a451e1 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30mainboard: Add Lenovo ThinkPad T440pIru Cai
The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30commonlib/helpers: Add alloca() macroTim Wawrzynczak
If there is no alloca() macro defined, then define it as __builtin_alloca(), as most compilers support that as an intrinsic instead, if no alloca.h is included. Change-Id: I8730d57ce7c2f323b52e7a5720c598fb7af16b44 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36387 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-29arch/x86/*.S: use defines instead of hardcoded valuesPatrick Rudolph
As preparation for x86_64 clean the assembly code and introduce arch/ram_segs.h similar to existing arch/rom_segs.h. Replace open coded segment values with the defines from the new header. Change-Id: Ib006cd4df59951335506b8153e9347450ec3403e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36321 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-29soc/skylake/vr_config: print mch_id in hexMaxim Polyakov
Change-Id: I89e2bccf3fb99b20dde38745fc124d5dc95feb78 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-29ec/google/chromeec: Clean up ec.[ch]Tim Wawrzynczak
Change all uN integral types to uintN_t. Make the names of host command params/responses consistent. Use static struct initialization to ensure all fields are initialized. BUG=none BRANCH=none TEST=compiles Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-29nb/intel/{nehalem,x4x}: Remove unused 'include <pc80/vga_io.h>'Elyes HAOUAS
Change-Id: If9c743335ab09038c9e22d1f4d3b7411585b2c8c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-29purism/librem_skl: add libgfxinit supportMatt DeVillier
Panel settings taken from KBL FSP sample vbt.bin Test: build/boot librem13v2/15v3 with libgfxinit init, verify both LFB and text modes functional Change-Id: I9582065603417e53704244e95dde51a59f709664 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-28src/soc/intel: skl,cnl,icl: remove unneeded check in cbmem_top()Michael Niewöhner
As stated in CB:36334 cbmem_top() should not be called before memory is initialized. Therefore drop the check to see if MRC finished. Change-Id: I964a20a5e9aa69fdb75413c36a17d34b7ba00098 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28soc/intel/broadwell_de: Implement smbios_cpu_get_maximum_freq_mhz()Andrey Petrov
Determine maximum speed by looking at either turbo flex limit or uncore ratio limit. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I0f3a64a40cb1d28d8eb9380c2071ec748e345b88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28arch/x86: Populate more fields in SMBIOS type 4Andrey Petrov
If CPUID leaf 0x16 is available (Skylake and later) use it to obtain current and maximum speed. Otherwise call weak function that can be provided elsewhere (cpu/soc/mainboard). Also, populate "core enabled" with the same value as "core count". TEST=tested on OCP Monolake with dmidecode -t processor Change-Id: Ie5d88dacae6623dfa0ceb3ca1bb5eeff2adda103 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28arch/x86: Move max cpuid leaf function into arch/x86Andrey Petrov
This cpuid function (0) is same across Intel and AMD so having it in arch/x86 seems like a good idea. Change-Id: I38f1c40bceac38ed6428f74b08bf60b971644f5a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK supportArthur Heymans
The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCKArthur Heymans
With CONFIG_C_ENVIRONMENT_BOOTBLOCK it makes more sense to rely on the size of the bootblock over CONFIG_XIP_ROM_SIZE. To make this work, only powers of 2 are allowed as bootblock size. Change-Id: Ic8104ca9c51e4d2eccdb277e4c2111d2da662f3e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28soc/mediatek/mt8183: Pass MR values as function argumentsYu-Ping Wu
To make data flow more explicit, global variables 'MR01Value' and 'MR13Value' are replaced with local variables, which are passed as function arguments. BRANCH=kukui BUG=none TEST=1. emerge-kukui coreboot 2. Fast calibration succeeded Change-Id: Id21483092c86c3ae7dbb1173a2b943defe41a379 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-28src/cpu: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also: add some missing includes spotted by Jenkins. Including <types.h>, is supposed to provide stdint and stddef. Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28src/southbridge: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also, including <types.h>, is supposed to provide stdint and stddef. Change-Id: I7e1a3483aae0e3f0a7bc2eb2c1862ae7a325fd9c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28mb/lenovo/x200: Correct device tree override logicBill XIE
If a device node should be enabled on some variants, but disabled on others, it had better be declared as disabled (rather than absent) in base device tree (rather than override tree for the variant disabling it), and enabled in override tree for the variant needing it, so that it does not need to be declared once more when adding another variant with such node disabled. Change-Id: I4b28360905ae38149ace9ac5d21cd6d5045b7584 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-28lib/cbfs: Don't load XIP stages from bootblockArthur Heymans
This should improve boot times as it skips unnecessary read and writes. Change-Id: I8cf36613903783e741b2e3bfeeee5bc29ab26d5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-28mb/google/sarien/arcada: Add support for Cirque TouchpadKarthikeyan Ramasubramanian
Add Cirque Touchpad devicetree configuration to export relevant ACPI objects to the kernel. BUG=b:141259109 BRANCH=sarien TEST=Boot to ChromeOS. Ensure that relevant ACPI objects are exported in the SSDT. Change-Id: I91dcb27b86c6a2bed5579f1f6c1102871d55b315 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-28lib/prog_loaders.c: Add prog_locate_hook()Frans Hendriks
There is no posibility to prevent loading images from cbfs at this stage For security features prog_locate_hook() is added. This hook can be used to prevent loading the image. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG-1701 Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-27mb/google/poppy/variant/nocturne: don't invert GPP_D17Nick Vaccaro
This change removes an inversion of GPP_D17 that caused the device to get stuck in a reboot loop because the kernel was crashing within the first couple seconds of kernel boot. BUG=b:142515200 BRANCH=none TEST=Flash and boot nocturne, verify boot is stable and that device doesn't reboot after jumping into kernel, and that it passes the 'tast -verbose run <ip> hardware.SensorRing' test. Change-Id: Ia1408ef6ea92f6b31a9f3eee8720954af3a7c382 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35967 Reviewed-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27Dragonair: Add sku23Wisley Chen
BUG=b:142987639 TEST=emerge-hatch coreboot Change-Id: I0ff1a81d0579d0b328a48bc7d4f867592ec63e8b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-27mb/supermicro/x11-lga1151: use the new Kconfig to hide GOPMichael Niewöhner
The board does not have any graphics port connected to the SoC. Hence, use the new Kconfig to hide GOP initialization. Change-Id: Ia88e062bea243369da27b94608f89f0808257688 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-27device: add Kconfig option to hide GOP initialization optionMichael Niewöhner
There are mainboards that do not have any graphics ports connected to the SoC. It would be senseless to initialize the iGD, thus add a new mainboard Kconfig to hide the GOP option. Change-Id: Ica3b3a7a0c8120c95412369a24d8d669fb59fded Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-27src/soc: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c1228d3f9e7a12fe30c48e3b1f143520fed875c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27src/mainboard: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27mb/supermicro/h8scm_fam10: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Found-by: ACPICA 20191018 Change-Id: I9f6c025a548e60a91d8064b0aeaf4d8530d78305 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/amd/serengeti_cheetah_fam10: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I1650df927aa6d4a1282ed50b2bcbb63d5bd04347 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/msi/ms7721: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ib70b349742fb636e25f1369d54641997e57a2045 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/lippert: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I5761b093b43aa7d97a6b84730a4009a5d163550d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/jetway: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ib454fc76db0b45332326772b8d1f295429107133 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src/[northbridge,security]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-27mb/iei: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I547be16285787ee3578f855111ca177be047ced2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/gigabyte: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ia27308ba17c6b5c836ada6278f7d26631e09c022 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/avalue: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I303023a16f8c913c965995794cb627bb9591560b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/asus: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() keyword is deprecated, use Device() instead. Change-Id: I162304bdef6562fd660c01fb8fc67037ebe8cfa5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/advansus: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() Keyword is deprecated, use Device() instead. Change-Id: I805291716ab3395736d8a70a18468f247d9f4edf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/amd: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ia1d73806b00ec38084fff3989f52227d4c216e65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27cpu/amd/*/*/acpi/: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Found-by: ACPICA 20191018 Change-Id: I4541372a98f05d3e915c74bc28f41309754014e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36258 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27mb/(ich7): Use macro instead of magic numberElyes HAOUAS
Change-Id: Ida291ed9f3a509e9b96a5c254433db6f8028bfb2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src/{device,drivers}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also, including <types.h>, is supposed to provide stdint and stddef. Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src: Use 'include <boot/coreboot_tables.h>' when appropriateElyes HAOUAS
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27cbmem.h: Align comment with the reality of implementationsArthur Heymans
cbmem_top() should simply not be called before memory is initialed, in order for the implementation to return something meaningful. Change-Id: I8fe32844af290626a0f91279143fda4d3442680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2019-10-26drivers/intel/fsp2_0: move die() calls to the functionsMichael Niewöhner
Since there are no calls where we wouldn't die(), move die() calls into the fsp_find_* functions. Change-Id: I750a225999688137421bbc560d9d1f5fdf68fd01 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-26soc/intel: common,skl,cnl,icl: drop reserved mmio memory size calculationMichael Niewöhner
Remove the calculation of the Reserved Intel MMIO Memory size from systemagent and memmap, since it is not needed. The size is used in SA to calculate the space between cbmem_top and TSEG without DPR and Chipset Reserved Memory. Since this will always be equal to 0, the reservation will be skipped and TSEG, DPR and Chipset Reserved Memory will get reserved alltogether. By reading the code and pratical testing we figured out that: - TSEG - DPR - reserved - top_of_memory == 0 - TSEG - DPR - reserved == top_of_memory This means the whole block will never reserve anything because it is always 0. Hence the code can be removed for simplification. Tested successfully on X11SSM-F Change-Id: I0cc730551eb3a79c78a971b40056de8d029f4b82 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-26soc,mb/intel: clean up remaining FSP2.0 socs/boardsMichael Niewöhner
Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26soc/intel/skylake: move/rename files after drop of FSP 1.1Michael Niewöhner
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier. Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26drivers/intel/fsp1_1: remove orphaned functionalityMichael Niewöhner
Remove orphaned functionality from the FSP1.1 driver that only has been used by skylake, which is now FSP2.0-only. Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36266 Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26soc/intel/skylake: drop support for FSP 1.1Michael Niewöhner
This drops support for FSP 1.1 in soc/intel/skylake, after all boards have been migrated to FSP 2.0, which is backwards compatible. Any moving of files happens in a follow-up commit to make review easier. Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26mb/intel/saddlebrook: Enable serial port on SIOPraveen Hodagatta Pranesh
Enable saddlebrook board Serial port on SuperIO by selecting DRIVERS_UART_8250IO. TEST=Build, Boot saddlebrook board and verified serial logs. Change-Id: Ic7b3416f281bfd91416c987c5a720ffac0c89d45 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-10-26mb/intel/saddlebrook: migrate to FSP 2.0Michael Niewöhner
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) TODO: - testing Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923 Reviewed-by: Michael Niewöhner Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25trogdor: Provide initial mainboard supportT Michael Turney
Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 23:27:52 +0000