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2020-12-05soc/amd: Fix X86_RESET_VECTOR location in commentsKyösti Mälkki
Change-Id: I3e4b3cbed8abe3988d9f48c13d01400af75a4776 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48307 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05amd_blobs: Always set default pathsNico Huber
Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This way we get error messages about the missing files when the blobs repos aren't checked out. Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-05mb/prodrive/hermes: Generalise `check_signature` functionAngel Pons
Allow to specify which signature is to be checked. Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-05mb/google/dedede: Create storo variantTao Xia
Create the storo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:174284884 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_STORO Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I5ad41e0b2bc95b44733a2ad3c543267f3f56f9e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-12-05soc/amd/picasso/tsc: fix clock divisor range checkFelix Held
The CPU core clock divisor ID needs to be in the range from 8 to 0x30 including both numbers. TEST=Compared with Picasso's PPR #55570 Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/amd/majolica: add functionality to add EC blob to buildFelix Held
Without the EC blob being present in the SPI flash, the board won't even power up. Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/amd/majolica: add skeleton of Cezanne reference boardFelix Held
This is an adapted copy of mainboard/example/min86 that is currently only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't expected to reach boot block at the moment. It will be extended in future follow-up commits. Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05soc/amd/cezanne: add skeleton for new SoCFelix Held
This is based on the minimal example code in soc/example/min86 and was adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF support. In its current state this won't even reach the boot block, but will pass the build bot. The missing parts for that will be added in future patches. This is an attempt to not go the usual route to create a copy of a previous SoC generation and the make changes to the code to work for the new SoC, but to start from a nearly empty directory and then add the actual code stage by stage and component by component. Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/google/volteer/var/voema: Add MIPI camera supportDavid Wu
1. Add VARIANT_HAS_MIPI_CAMERA to Kconfig.name 2. Add mipi_camera.asl BUG=b:169356808,b:169551066 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47668 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/puff/var/dooly: Update DPTF parametersTony Huang
DPTF paramerters form thermal team. Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W. BUG=b:174514010 BRANCH=puff TEST=build image and verified by thermal team. Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-05mb/google/zork: set APU_EDP_BL_DISABLE to low as defaultChris Wang
set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than APU_DP_BLON. BUG=b:171954512 BRANCH=zork TEST=validate the panel sequence with scope. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-12-05mb/google/volteer: Create copano variantFrankChu
Create the copano variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:174413884 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COPANO Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-12-05drivers/intel/fsp2_0/memory_init: Wrap calls into FSPPatrick Rudolph
Use a wrapper code that does nothing on x86_32, but drops to protected mode to call into FSP when running on x86_64. Tested on Intel Skylake when running in long mode. Successfully run the FSP-M which is compiled for x86_32 and then continued booting in long mode. Change-Id: I9fb37019fb0d04f74d00733ce2e365f484d97d66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48202 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05cpu/x86/64bit: Add code to call function in protected modePatrick Rudolph
This adds a helper function for long mode to call some code in protected mode and return back to long mode. The primary use case is to run binaries that have been compiled for protected mode, like the FSP or MRC binaries. Tested on Intel Skylake. The FSP-M runs and returns without error while coreboot runs in long mode. Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-05mb/google/volteer/variant/lindar: Correct SD card reader power sequenceKevin Chang
According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released. To ensure this, set the power enable signal in the bootblock GPIO table. BUG=b:173676531 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/zork: Replace generic driver with sx9324 driverEric Lai
Use a new driver for the SX9324 proximity detector device. This is first draft settings, will modify it after fine tuning. BUG=b:172397658 BRANCH=zork TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05drivers/i2c/sx9324: Add more registers and reorderEric Lai
Export all registers that driver is looking for. And put in alphabetic order. The missing registers for kernel v5.4 sx93xx are: reg_irq_msk reg_irq_cfg0 reg_irq_cfg2 reg_afe_ph0/1/2/3 BUG=b:172397658 BRANCH=zork TEST=Build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac Reviewed-on: https://review.coreboot.org/c/coreboot/+/47866 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/zork/var/vliboz: Add LTE_RST power sequenceEric Lai
Latest HW schematic add LTE_RST pin to control module power sequence. BUG=b:173490220 BRANCH=zork TEST=measure the waveform is meet the LTE module spec. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-05mb/google/dedede/var/drawcia: Configure Acoustic noise mitigation UPDsMaulik V Vaghela
Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4 which is calibrated value for the board. Other values like PreWake, Rampup and RampDown are 0 by default. BUG=b:162192346 BRANCH=dedede TEST=Correct value is passed to UPD and Acoustic noise test passes. Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-05soc/intel/jasperlake: Add Acoustic noise mitigation configurationMaulik V Vaghela
This patch exposes acoustic noise mitigation related UPDs/configuration to be filled from devicetree. For each variant, we might have different values for various parameters. Filling it from devicetree will allow us to fill separate values for each board/variant. Note that since JasperLake only has one VR, we're only filling index 0 for slew rate and FastPkgCRampDisable. BUG=b:162192346 BRANCH=dedede TEST=code compilation is successful and values from devicetree are getting reflected in UPDs Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-05soc/intel/xeon_sp: Don't use common block acpi.hMarc Jones
Don't use the common block acpi.h when we aren't using the COMMON_ACPI config. Fixes a dependency build issue in an upcoming commit. Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-12-05soc/intel/common/block/usb4: Add the PCI ID for ADLV Sowmya
This patch adds the PCI device ID for Alderlake CPU xHCI. Change-Id: I4074a81aa9be2ef3a0956da08bece32a613415ab Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-05device/pci_id: Add TCSS PCI IDs for AlderlakeV Sowmya
Add the PCI IDs for Alderlake TCSS, * USB xHCI * USB xDCI * TBT DMA * TBT PCIe Change-Id: I28bb310c7b031d2766c9e03dbcbe1c79901a7d87 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48242 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04cbfs: Add more error messages for lookupJulius Werner
The new CBFS stack will log messages for found files but leaves error messages up to the caller. This patch adds appropriate generic error messages to cbfs_lookup(), matching the behavior of the old CBFS stack for not found files. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8cf44026accc03c466105d06683027caf1693ff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-04soc/amd/picassso/acpi: increase MMIO region size of GPIO controllerFelix Held
The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256 bytes each, so increase the reserved size to match the hardware. Also replace the base GPIO address with the corresponding define. Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/google/brya: Initiate device treeEric Lai
Initiate device tree based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04soc/intel/alderlake: Align chipset.cb with pci_devs.hEric Lai
Refer pci_devs.h naming to align chipset.cb. Correct thc0, thc1 and add cnvi_bt. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Add EC smihandlerEric Lai
Add implementation of EC smihandler BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Set UART consoleEric Lai
Follow latest schematic UART_PCH_DBG is UART 0. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04Coachz: change EN_PP3300_DX_EDP from gpio52 to gpio67yuanliding
Coachz rev1 has changed EN_PP3300_DX_EDP from gpio52 to gpio67. BRANCH=none BUG=b:174123578 TEST=emerge-strongbad coreboot chromeos-bootimage. flash coreboot and boot up normally. Signed-off-by: yuanliding <yuanliding@huaqin.corp-partner.google.com> Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-12-04cpu/x86/smm_module_loaderv2: Fix compiling for x86_64Arthur Heymans
Change-Id: I9288ede88f822ff78dd9cb91020451dc935203a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-04soc/amd: move smi_util to common blockFelix Held
The functionality in smi_util applies for all 3 AMD SoCs in tree. This patch additionally drops the HAVE_SMI_HANDLER guards in the common block's Makefile.inc, since all 3 SoCs unconditionally select HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any functionality that is only present when that option is selected. Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/amd/mandolin: Unify devicetree formatting for 00:14 devicesPaul Menzel
To accommodate also `off`, two spaces are used after `on` to align comments. This unifies the devicetree files of the two variants. Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in commentPaul Menzel
This reduces the difference with Cereme’s devicetree file. Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: use more readable size formats in FMAP filesFelix Held
Since the FMD file isn't parsed any more by a shell script in the SoC's Makefile.inc, we can use better human-readable numbers for the section sizes. TEST=Timeless build results in identical image. Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSETFelix Held
TEST=Timeless build results in identical image. Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/emulation/x86: Add optional parallel_mp init supportArthur Heymans
This makes it possible to select both the legacy LAPIC AP init or the newer parallel MP init. Tested on i440fx with -smp 32. Change-Id: I007b052ccd3c34648cd172344d55768232acfd88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04cpu/qemu-x86: Increase MAX_CPUS to have actual AP initArthur Heymans
CONFIG_MAX_CPUS=4 is the maximum supported with SMM_ASEG. TESTED: on q35 and i440fx -smp 4/32. Change-Id: I696856870e34e7a7ad580bc83c6b38f1dfb4511d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04cpu/x86/lapic/secondary.S: Adapt for x86_64Arthur Heymans
Adapt the old lapic init code for x86_64. Change-Id: I5128ed574323025e927137870fb10b23d06bc01d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04cpu/qemu-x86: Add the option to have no SMMArthur Heymans
Qemu i440fx does not support an smihandler at the moment. Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHEArthur Heymans
When FSP-T is used, the first thing done in postcar is to call FSP-M to tear down CAR. This is done before cbmem is initialized, which means CBFS_MCACHE is not accessible, which results in FSP-M not being found, failing the boot. TESTED: ocp/deltalake boots again. Change-Id: Icb41b802c636d42b0ebeb3e3850551813accda91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48282 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04src/soc/intel/alderlake: Enable the PCH HDAV Sowmya
This patch enables the PCH HDA device based on the devicetree configuration. Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48272 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputsMichael Niewöhner
All four SMI/NMI interrupt inputs have an external pull-up resistor and get triggered by pulling the line low. Thus, correct the trigger to active-low. Also document the signals by adding appropriate comments. The pads' connections have been determined by dissecting a dead board. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48093 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/supermicro/x11ssm-f: drop NMI overridesMichael Niewöhner
Drop the NMI overrides, since NMI now gets configured in gpio common code. Also remove the variant init mechanism, which is unused now. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I02e0c679f9aafe33108320a8dfc62dcb278202ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48092 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04soc/intel/{skl,cnl}: add NMI_{EN,STS} registersMichael Niewöhner
Add NMI_EN and NMI_STS registers, so they can be configured for using NMI gpios. References: - CMP-LP: Intel doc# 615146-1.2 - CMP-H: Intel doc# 620855-002 - SPT-H: Intel doc# 332691-003 - SPT-LP: Intel doc# 334659-005 - CNP-H: Intel doc# 337868-002 Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before but now makes the Linux kernel complain about a NMI. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04soc/intel/common/block/gpio: add code for NMI enablingMichael Niewöhner
Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04intel/common/block/gpio: only reset configured SMI instead of allMichael Niewöhner
Currently, when a SMI GPIO gets configured, the whole status register is get written back and thus, all SMIs get reset. Do it right and reset only the correspondig status bit of the GPIO to be configured. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48089 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03mb/google/zork: Set S0IX_SLP_L high in S0, low in S3Martin Roth
This is used as a signal to show the system state. It hadn't been used up to this point as we're not currently using S0i3, but the fingerprint sensor will use it to go into a low power mode, so set it appropriately on Trembyle. Dalboz devices don't use the FPMCU, but set there as well so that the state matches. BUG=b:174695987 TEST=Verify GPIO state in S0 and S3 with the EC BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Vincent Palatin <vpalatin@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03spi/flashconsole: Fix internal buffer overflowNico Huber
Once the console's FMAP region is full, we stop clearing the line buffer and `line_offset` is not reset anymore. Hence, sanity check `line_offset` everytime before writing to the buffer. The issue resulted in boot hangs and potentially a brick if the log was very verbose. Change-Id: I36e9037d7baf8c1ed8b2d0c120bfffa58c089c95 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48074 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03mb/hp/z220_sff_workstation/Kconfig: Select MAINBOARD_USES_IFD_GBE_REGIONAo Zhong
Select MAINBOARD_USES_IFD_GBE_REGION to make CONFIG_HAVE_GBE_BIN (Add gigabit ethernet configuration) selection available. Without that onboard Ethernet won't work. Signed-off-by: Ao Zhong <hacc1225@gmail.com> Change-Id: I9fe138363fc47254285ebaa4a7dbe5b94a0a8784 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48007 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03soc/intel/skylake: Add chipset devicetreeFelix Singer
Set most of the devices to off to keep current behaviour. Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-03cbfs: mcache: Fix end-of-cache checkJulius Werner
After the mcache is copied into CBMEM, it has *just* the right size to fit the final tag with no room to spare. That means the test to check if we walked over the end must be `current + sizeof(tag) <= end`, not `current + sizeof(tag) < end`. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I25a0d774fb3294bb4d15f31f432940bfccc84af0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-03cbfs: Add verification for RO CBFS metadata hashJulius Werner
This patch adds the first stage of the new CONFIG_CBFS_VERIFICATION feature. It's not useful to end-users in this stage so it cannot be selected in menuconfig (and should not be used other than for development) yet. With this patch coreboot can verify the metadata hash of the RO CBFS when it starts booting, but it does not verify individual files yet. Likewise, verifying RW CBFSes with vboot is not yet supported. Verification is bootstrapped from a "metadata hash anchor" structure that is embedded in the bootblock code and marked by a unique magic number. This anchor contains both the CBFS metadata hash and a separate hash for the FMAP which is required to find the primary CBFS. Both are verified on first use in the bootblock (and halt the system on failure). The CONFIG_TOCTOU_SAFETY option is also added for illustrative purposes to show some paths that need to be different when full protection against TOCTOU (time-of-check vs. time-of-use) attacks is desired. For normal verification it is sufficient to check the FMAP and the CBFS metadata hash only once in the bootblock -- for TOCTOU verification we do the same, but we need to be extra careful that we do not re-read the FMAP or any CBFS metadata in later stages. This is mostly achieved by depending on the CBFS metadata cache and FMAP cache features, but we allow for one edge case in case the RW CBFS metadata cache overflows (which may happen during an RW update and could otherwise no longer be fixed because mcache size is defined by RO code). This code is added to demonstrate design intent but won't really matter until RW CBFS verification can be supported. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8930434de55eb938b042fdada9aa90218c0b5a34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-03x86: Put bootblock startup code into .text._start sectionJulius Werner
The initial bootblock assembly code on x86 is just put into the .text section, which just happens to come before all the individual .text.* function sections in the program.ld script. So it tends to be at the start of the image, but if you inserted another linker script section with contents before .text, it would cause a problem. (I'm not sure if it's an architectural requirement for _start16bit to come at the start of the image, but at least its 4K alignment requirement would waste a lot of space if it didn't.) This patch moves the section to .text._start which is the name other architectures use for the code they want in the very front of the image and which is listed first in program.ld. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia84e6e33ec29584d356e226e8fdcb8c9334d49af Reviewed-on: https://review.coreboot.org/c/coreboot/+/46834 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03cbfstool: Use cbfs_serialized.h and standard vboot helpersJulius Werner
This patch reduces some code duplication in cbfstool by switching it to use the CBFS data structure definitions in commonlib rather than its own private copy. In addition, replace a few custom helpers related to hash algorithms with the official vboot APIs of the same purpose. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-12-03cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()Julius Werner
This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39306 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02lib/trace: Remove TRACE supportKyösti Mälkki
Looks like the option is generally not compatible with garbage collections. Nothing gets inlined, for example is_smp_boot() no longer evaluates to constant false and thus the symbols from secondary.S would need to be present for the build to pass even if we set SMP=n. Also the addresses of relocatable ramstage are currently not normalised on the logs, so util/genprof would be unable dress those. Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-02mb/google/brya: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock and ramstage. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add entry stubs of each stageEric Lai
Add entry point stubs of each stage for Brya. More functionalities will be added later. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48063 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/brya: Add flashmap descriptorEric Lai
BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48062 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02drivers/i2c/nct7802y: Move the sensor initialization procedureMaxim Polyakov
The current location for the sensor initialization procedure was chosen by mistake. Move this into a separate function in nct7802y.c . Change-Id: I093ae75db5f0051bff65375b0720c86642b9148a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-02cbfs: Port cbfs_load() and cbfs_map() to new APIJulius Werner
This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API directly, rather than through cbfs_boot_locate(). For cbfs_load() this means that attribute metadata does not need to be read twice. Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Move more stuff into cbfs_boot_lookup()Julius Werner
cbfs_boot_locate() is supposed to be deprecated eventually, after slowly migrating all APIs to bypass it. That means common features (like RO-fallback or measurement) need to be moved to the new cbfs_boot_lookup(). Also export the function externally. Since it is a low-level API and most code should use the higher-level loading or mapping functions instead, put it into a new <cbfs_private.h> to raise the mental barrier for using this API (this will make more sense once cbfs_boot_locate() is removed from <cbfs.h>). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-02soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entryFurquan Shaikh
This change drops the special check added for TGL/JSL platforms and performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later in the boot process to ensure that the memory training parameters are written back to SPI flash before performing a reset for CSE RW jump. With the recent changes in CB:44196 ("mrc_cache: Update mrc_cache data in romstage"), MRC cache is updated right away in romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-12-02soc/amd: factor out common SMI/SCI enums and function prototypesFelix Held
At least a part or the remaining definitions in the soc-specific smi.h files are also common, but those have to be verified more closely. Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd/common/smbus: remove misleading definitionFelix Held
SMBHST_STAT_NOERROR was a redefinition of SMBHST_STAT_INTERRUPT that was used in smbus_wait_until_done. Remove the misleading bit definition that also didn't correspond with the register definitions and replace it with the definition of the actual bit that gets checked. Also add a comment that the code actually checks the IRQ status flag to see if the last command is already completed. Change-Id: I1a58fe0d58d3887dd2e83320e977a57e271685b3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out fch_smbus_initFelix Held
Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out SMBUS controller registers into common headerFelix Held
The patch also rewrites the bit definition using shifts to make them easier to read. The older non-SoC chips can probably also use the new header file, but for this patch the scope is limited to soc/amd, since the older non-SoC chips don't use the SMBUS controller code in soc/amd/common. TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change. Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out common AOAC device enable and status query functionsFelix Held
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is the default value after reset for those bits on both platforms. Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out common AOAC definitionsFelix Held
The register locations and bit definitions are the same for Stoneyridge and Picasso. Since not all devices are present on all SoCs, keep those numbers in the SoC-specific code. Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profileMike Banon
The ability to set up a custom memory profile is useful if you don't like the XMP memory profiles (if they exist) of your RAM sticks, or want to try some overclocking. Read SPD data will be overriden by your custom values. Tested on Crucial BLT8G3D1869DT1TX0 (1866MHz 9-9-9-27). Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-02vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profilesMike Banon
Add XMP memory profiles support that has been tested on f15tn (A88XM-E) and f16kb (AM1I-A) with two Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40488 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/intel/skylake: Fix compilation under x86_64Patrick Rudolph
Change-Id: I37382ab06a8f1760e955d1ec76a6a00958b05999 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48177 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cpu/x86/smm/smm_stub: Fix stack canary on x86_64Patrick Rudolph
On x86_64 the cannary is 8 bytes in size, so write the additional 4 bytes to make SMM handler happy. Tested on Intel Skylake in long mode. No longer dies in SMM. Change-Id: Id805c65717ec22f413803c21928d070602522b2c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48215 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cpu/x86/smm/smm_stub: Fix GDT for x86_64Patrick Rudolph
The previous code was crashing when jumping back to ramstage, now it works. The GDT is now using the same values as the other ones in coreboot. Change-Id: Id00467d9d8a4138ddea73adbda4b39f12def583f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48214 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/volteer: Add fw_config entries for boot deviceDuncan Laurie
Add the fw_config entries for the newly added boot device fields. These are added as separate fields since a board may have more than one selected. BUG=b:173129299 TEST=abuild google/volteer Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/volteer: Add additional SD cards to device listDuncan Laurie
The initial commit only focused on GL9755S and RTS5261, but there were recently other cards added to the fw_config and those also need to be added to the probe lists. BUG=b:173207454 TEST=abuild google/volteer Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02soc/amd/picasso: add FSP binary locationFelix Held
Now that the initial version of the Picasso FSP binaries have finally landed, we can set the default paths to point to them now. Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42472 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/intel/adlrvp: Replace tab by white space in devicetreeMeera Ravindranath
Change-Id: I928b4528fa5b4c378a2e8ff7bb88547da1413df2 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48213 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341Tan, Lean Sheng
The FSP-M/S/T related headers added are generated as per FSP v2341. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I98f738402490b47efa1a346f81db47857e384e13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-02soc/intel/elkhartlake: Update KconfigTan, Lean Sheng
Update Kconfig: 1. use FSP2.1 instead of 2.2 2. remove HECI_DISABLE_USING_SMM config 3. update CAR related stack & ram size 4. update FSP heap size 5. set IED region size = 0 as it is not used 6. update SMM TSEG size 7. update RP & I2C max device #s 8. update UART base address Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45078 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/intel/skylake: Map VBIOS IDsPaul Menzel
The extracted VBIOS Option ROM ships the same ID for several generations, not matching the ID on the hardware resulting in a mismatch, and coreboot does not run the Option ROM. PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Add the appropriate mappings. TEST=coreboot runs the ROM on the TUXEDO Book BU1406. Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43853 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/dedede/var/drawcia: Support VBT for DrawmanKarthikeyan Ramasubramanian
Default VBT supports only integrated Display port. Drawman supports a HDMI port and hence support a separate VBT for Drawman. BUG=b:161190931 BRANCH=dedede TEST=Build and boot to OS in Drawlat and Drawman. Cq-Depend: TBD Change-Id: I8895cc67d87428eddb31328f1e3a90c346b54533 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-12-02mb/google/dedede: Add Daughter-board FW_CONFIG in devicetreeKarthikeyan Ramasubramanian
Add daughter-board ports bit field and mask in devicetree. BUG=b:161190931 BRANCH=dedede TEST=Build and boot to OS in drawlat & drawman. Change-Id: Ibbd86fc8c3e44a7d1703b8ce75c48881226545c9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-12-02vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04Ronak Kanabar
The headers added are generated as per FSP v2385_04. Previous FSP version was 2385_02. Changes Include: - add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and RampDown UPDs in Fsps.h BUG=b:174330941 BRANCH=dedede TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3438485 Change-Id: I477af05c34f767a43990670a711992641eaf6000 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47862 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/zork: Update SPD table for ShubozKane Chen
Add memory table to "mem_parts_used.txt", and command to generate files: go build gen_part_id.go ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/shuboz/spd/ ../../../src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt Shuboz memory table as follow: value Vendor Part number 0x00 MICRON MT40A512M16TB-062E:J 0x01 HYNIX H5AN8G6NCJR-XNC 0x02 MICRON MT40A1G16KD-062E:E 0x03 SAMSUNG K4AAG165WA-BCWE BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-12-02mb/google/dedede/var/lantis: Configure IRQs as level triggered for HID over I2CTony Huang
Config HID-I2C device to level trigger. As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:171546871 TEST=emerge-dedede coreboot Change-Id: If8be25f591715765a99920b79482c862b1cc7079 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-02arch/x86/car.ld: Check for out of bound on no-XIP stagesArthur Heymans
Check that stages running in CAR have their start and end in CAR. Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-02src/acpi/acpigen: Add NULL pointer checkRonak Kanabar
Add NULL pointer check in acpigen_emit_namestring to avoid segmentation fault. Change-Id: I3d01d28e74f202278b5a5a96d2edd45c66f10883 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48148 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01soc/amd/stoneyridge: align AOAC code with PicassoFelix Held
In commit 09d50671e6b43c23853a91ff4d6fb26c1e7e17a1 the AOAC code was reworked for Picasso and this patch ports this back to Stoneyridge to facilitate factoring out the functionality into common code. Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-01soc/amd/picasso/aoac: make aoac_devs array unsignedFelix Held
The numbers in the array are unsigned, so use an unsigned type there. Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-01soc/amd/picasso/aoac: fix typo in commentFelix Held
The power_off_aoac_device function clears the FCH_AOAC_PWR_ON_DEV bit, so the comment should be that it powers off the devices. Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-01soc/intel/common/block/smm/smihandler: Fix compilation under x86_64Patrick Rudolph
Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64Patrick Rudolph
Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 12:26:25 +0000