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Add common device tree used for EGS platform. Also add register
setting shared for all EGS platform.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I812f621ee9d1643fd4fa35df92443d64f7aaabc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This reverts commit 2e6fa8206e0a3bdd2e53542b6377fe2b37e3f26e.
Reason for revert: causing `redefinition` issue.
src/mainboard/google/poppy/variants/nami/gpio.c:527:26: error: redefinition of 'variant_romstage_gpio_table'
const struct pad_config *variant_romstage_gpio_table(size_t *num)
^
src/mainboard/google/poppy/variants/nami/gpio.c:426:26: note: previous definition is here
const struct pad_config *variant_romstage_gpio_table(size_t *num)
^
Change-Id: I107cce8bf3a5bf38edb39b9d46512ee0d467d354
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73210
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The current clock register definition is wrong, which results in wrong
audio sampling rate. Fix it by adjusting the POSTDIV registers of
APLL1-APLL5.
TEST=build pass
BUG=b:250459803, b:250464574
Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0
Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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MT8188 supports port0/port1 download. The hardware needs a trapping pin
to select the port to use. When port1 is selected, the phy of port1 will
be switched to port0. That is, port1 connector will be the physical line
of port0. Since port0 phy isn't initialized in coreboot, switch back to
port1 phy.
BUG=b:269059211
TEST=can detect USB2 devices in depthcharge.
Change-Id: Ic97d0bd9d0233883196b2e73ac2a22cd8ea9466b
Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the
port.
BUG=b:269690930
TEST=kernel can detect a PL2303 USB device
BRANCH=dedede
Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Add functionality such that the FPMCU is power cycled long enough
on boot to ensure proper reset.
This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami.
Confirmed power is off for 150ms seconds on boot.
Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)
Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Phoenix2 VBIOS PCI DID is 15c8 though the VBIOS image uses a different
PCI ID i.e. 0x1205, so we need to implement map_oprom_vendev for the SoC.
Change-Id: I7eef5eb41b781f02abb9dd4098e92a8652a431f5
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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VGA defineds the extended ASCII set based on CP437, but there is a bug
on printing them: in vga_write_at_offset(), we perform a bitwise or
between 'unsigned short' and 'signed char':
```
p[i] = 0x0F00 | string[i];
```
If we want to show an extended ASCII character, string[i] will be
negative and this bitwise operation will fail due to their implicit
casting rule: convert signed char to unsigned short by adding 65536.
To fix this, we need to cast the string to unsigned char manually
somewhere. Since we still want to leverage the built-in string utilities
which only accepts const char*, we still preserve the original
prototypes before, and cast it until we write into the frame buffer.
BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage
and verify drawing characters with code > 127.
Change-Id: I9cd65fe9794e5b0d338147924f28efd27fc8a1e8
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice15f0ce591104a2ace186f9049748219c2bc097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Based on product spec v1.4, update T3 timing from 180 ms to 150 ms.
BRANCH=none
BUG=b:262734395
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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After first recovery request coreboot would get stuck in bootloop with
VB2_RECOVERY_PREAMBLE as recovery reason due to not checking whether
coreboot is alread in recovery mode, and calling failing code.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Idc947a1d150ff6487cf973b36bf4f0af41daa220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Package C state demotion is now disabled for all RPL SoCs from within
soc/intel/alderlake/fsp_params, so no need to duplicate that in the
skolas devicetree.cb.
BUG=268296760
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Change-Id: I1c630e2efbdddd18a5423c79b73269e9b1be79c7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The EFS entry at offset 0x14 can point to either the first level PSP
directory table or to the PSP combo directory structure that was used
before the introduction of the AMD A/B recovery scheme. This scheme is
not to be confused with the VBOOT scheme. The PSP verstage code checks
if the header this entry points to begins with the PSP_COOKIE, which
indicates the entry is a first level PSP directory table. Due to that,
the EFS entry at offset 0x14 is always expected to point to a PSP
directory table, so rename combo_psp_directory to new_psp_directory to
match the actual usage. This EFS entry that points to the PSP directory
table is called new_psp_directory, since the entry at EFS offset 0x10
was used on some early AMD chips to point to the older PSP directory
table and that one is already called psp_directory. amdfwtool uses the
same naming scheme for those two PSP directory table pointers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10f19ee63f8d422433dba64402d84fd6bb9e0f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73083
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive`
so their configurations are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it
is not, it will break S3 exit.
When D3COLD_SUPPORT is not enabled, return `3` (D3Hot).
This fixed S3 exit on both TGL and ADL. Tested on StarBook
Mk V and Mk VI.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72765
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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If BIOS_DONE MSR is supported, set it after ReadyToBoot, because FSP
programs certain registers via Notify phase ReadyToBoot and it cannot
be modified by FSP after coreboot has set BIOS_DONE MSR, therefore we
try to set BIOS_DONE MSR as late as possible to avoid this.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I4f19a7c54818231ebbccd2b6f8b23f47b117eb1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71964
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Add fast_spi_set_vcl() to be called by the SOC lockdown function if SPI
Vendor Specific Component Capabilities are desired.
Change-Id: I6d9b58e90fa16c539b90c6b961862e97e1bf29a2
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72478
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To make MIPI/eDP panel functional on unprovisioned devices, it requires
passing SKU ID and panel ID info to the payload(depthcharge) to load the
corresponded device tree for kernel.
BUG=b:247415660
TEST=cbmem -1 |grep "SKU Code".
Change-Id: Id2254729b7bd621d1e9bc520e8f40916d0f81030
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73076
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch adds enable/disable FSP DisableEnergyReport feature
option to be used in devicetree for power instrument purpose.
BUG=None
Branch=None
Test=Build and boot MTL RVP.
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Change-Id: I58d4aea28ee2561d2ed73260c40cb22ce3fdd135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Replace the magic number with the CPUID_FROM_FMS macro to make it easier
to read.
TEST=Resulting image of timeless build for pcengines/apu2 is identical
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I15480dc883b65b5ffaf0cd38cf4e1f7b2222022e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73069
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of having two entries for two different steppings of the same
family and model combination using the CPUID_EXACT_MATCH_MASK, just have
one entry that uses CPUID_ALL_STEPPINGS_MASK to cover all steppings.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0118bb9b4b0be4d954a657d50789addca08a784e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73068
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The platform supports a discrete LPC TPM module. However, ME firmware
enables PTT by default and descriptor is configured for SPI TPM on the
platform's original firmware. So disabling PTT in ME is not enough,
because it falls back to SPI TPM. Ensure PTT is disabled in ME and SPI
TPM is disabled in descriptor soft straps.
TEST=Boot VP4650 and see LPC TPM is recognized by coreboot.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3764e085f2eb5ae957b9087d150320def7af4fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Based on product spec v1.4, update T3 timing to 150 ms from 300 ms
BRANCH=none
BUG=b:269041202
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
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Some users of MSI Z690-A board reported non-working IGD display
during post using various CPUs. As not all PCI IDs were hooked,
coreboot didn't detect GOP-provided framebuffer nor passed the
framebuffer information to the payload, causing a black screen.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I07584e07182ee56b61b6f751100431589d1cbe83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: Ic46e1663609068439069f666beca17ed76c679f0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69331
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I87e383ce2f28340dbc3c843dbf2ed0e47c00a723
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Duplicated branches found using 'Wduplicated-branches' GCC flag.
Change-Id: I252ea6aefb6d6c85135e640ba8deaa118be38f5e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: Ief8dd9c7f7b82e1cd62de5bc1a361432b0eac4ca
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I3a846d8e4b70ccb3e6fde448c00376cd0088716c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I0cbdcd5a787d99e2579a312a51c63d7fc4120462
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I58a4e4fbd1a43462147daa58a5fda767cfd59c06
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I4035fabd46b1ba7fa5463abb7f780aeccd6a96e0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Add NO_S0IX_SUPPORT for boards that do not support, or do not want
to support S0IX.
As all the boards in the tree that do this, don't support D3Cold,
add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is
selected to disable D3Cold support.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I03378cc7bb76fd65fcec81018e47f6288d437cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Besides crashlog, there's also other errors such as MCA error, which
should be recorded in BERT table. With current code, BERT table is
not generated if crashlog is not enabled. Add if statement for
SOC_INTEL_CRASHLOG so that MCA error can be recorded in BERT table
when crashlog is not supported.
For some server mainboard, crashlog is supported through BMC instead
of host firmware.
Also check if BERT region is generated when crashlog is not enabled.
Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
Enable HDA device and update jack codec HID from ALC5682I-VD to
ALC5682I-VS.
BUG=b:268309238
TEST=kernel detects audio DSP and rt5682s
BRANCH=dedede
Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
pmc_lock_smi() and pmc_lockdown_config() have PCH specific
implementations. Move them from common lockdown.c and pmc.c
into lbg/soc_pmutil.c.
Move sata_lockdown_config() and spi_lockdown_config() to
lbg/lockdown.c.
While here, fix some coding style issues.
Change-Id: I9b357ce877123530dd5c310a730808b6e651712e
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
BUG=b:265611305
TEST=Reboot test 2500 times pass
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
This patch improves `incomplete` debug messages for missing ACPI
name PCI devices.
Additionally, using the proper PCI device B:D:F to locate the device
with the missing ACPI name.
Finally, modify the msg time from Debug to Warning to make it more
purposeful.
TEST=Able to build and boot google/rex.
Without this patch:
```
[DEBUG] dev->path.devfn=10
[DEBUG] dev->path.devfn=a2
[DEBUG] dev->path.devfn=b0
```
With this patch:
```
[WARN] Missing ACPI Name for PCI: 00:02.0
[WARN] Missing ACPI Name for PCI: 00:14.2
[WARN] Missing ACPI Name for PCI: 00:16.0
```
Change-Id: I605e59de8cbec18c9a56eaa6e90a34f36ea4cdd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73072
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch fixes the wrong warning msg around `Unknown min d_state`
with having proper PCI Bus/Device/Function number to help to parse
the log better.
With this patch:
[WARN ] Unknown min d_state for 20
[WARN ] Unknown min d_state for 50
[WARN ] Unknown min d_state for 98
[WARN ] Unknown min d_state for 9a
[WARN ] Unknown min d_state for f9
With this patch:
[WARN ] Unknown min d_state for PCI: 00:04.0
[WARN ] Unknown min d_state for PCI: 00:0a.0
[WARN ] Unknown min d_state for PCI: 00:13.0
[WARN ] Unknown min d_state for PCI: 00:13.2
[WARN ] Unknown min d_state for PCI: 00:1f.1
Change-Id: Iccaf26882ce5998469b2be6cf5bc7082f193cb29
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Update header files for FSP for Meteor Lake platform to
version 2523_80, previous version being 2473_86.
FSPM:
1. Rename DMI UPDs
2. Address offset changes
FSPS:
1. Address offset changes
BUG=b:266499304
Change-Id: Ib4b8478bc3558ef863b6b52e685f981a5891e4a9
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72591
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Yabits is no longer maintained and git repo is archived.
Yabits has not been maintained for a long time,
the project is apparently closed.
Change-Id: Ida0bb79342448510d2c309339fabbe8066eca73c
Signed-off-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
According to the author of the mainboard scaleway/tagada, the mainboard
is not used anymore. Since the mainboard is not publicly available for
purchase and not used anywhere else, the usual deprecation process
of 6 months is not needed.
Thus, to reduce the maintenance overhead for the community, support for
the following components will be removed from the master branch and will
be maintained on the release 4.19 branch. Also, add a note to the 4.20
release notes.
* Mainboard Scaleway Tagada
Change-Id: Ifb83b8f2b1dc40cbef657e52c629948dc466ec6e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72915
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I434c22cd784e24c76bc47aee8728d28255b762db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
`stddef.h` should only provide the definitions defined by ISO or Posix.
The included `commonlib/bsd/helpers.h` provide a lot of non standard
definitions that may interfere with definitions from the application.
Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70116
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in
Mendocino's Kconfig instead of relying on the board's .config files
providing the correct settings. Those settings are per-SoC and not
per-board, so this is valid for all boards using the Mendocino APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I09c537d3801123e7ffc01608171918b0396b7a5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in Cezanne's
Kconfig instead of relying on the board's .config files providing the
correct settings. Those settings are per-SoC and not per-board, so this
is valid for all boards using the Cezanne APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67101d518c6b873ad89932ae39c2deb2ed6a4c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
map_oprom_vendev_rev is implemented in graphics.c in the SoC directory.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0123cb8ff662445fd0a613711d9e1981272b1235
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Add a new baseboard for hades, an Intel RPL based reference design.
Also, add variants for the reference boards hades. This commit is
a stub which only adds the minimum code needed for a successful build.
Need update gpio and memory DQ pins after final shchematic comes out.
BUG=b:269371363
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.
Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic96846d74df2dc279e13b22f2a83b6f893954fe8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73009
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.
Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I26b96966495dc35a8b4a0cb7d5a841f3812f2a70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73007
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.
Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib9fe0f05739fb19da2494629dc1d5aaa0ca6431f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73006
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add target to die when no APCB is found. This is not always a fatal
case, so mainboards can select between this and warn_no_apcb.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5bbc8dd3200c4781677411e67a4b5f1fe8b20286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
BUG=b:269059211
BRANCH=none
TEST=emerge-gralt coreboot
Change-Id: Ia2ec6db332939f1ac629cda9a0784a12c92d91da
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73056
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
|
|
Add Kconfig option for VBOOT_ARMV8_CE_SHA256_ACCELERATION, which will
use ARMv8 Crypto Extension for SHA256[1] instead of software
implementation.
This will speed up firmware verification in verstage.
[1] https://crrev.com/c/4170144
BUG=b:263514393
BRANCH=corsola
TEST='calculating body hash (SHA2)' get 13 msecs improvement on
Tentacruel.
Before:
509:finished calculating body hash (SHA2) 161,548 (14,490)
After:
509:finished calculating body hash (SHA2) 155,101 (1,187)
Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72711
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72422
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
_ON() calls _STA() at the beginning. If _STA() indicates the device is
ON, it exits immediately. The solution is to move this _STA() check
into the ONSK logic. In general cases, ONSK remains '0'.
NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following
by a device reset such as WWAN device. When such device calls its
_RST(), it increments OFSK. When the following _OFF() is called, it
was scheduled to skip, it will also increments ONSK. Similarly, when
the following _ON() is called, it checks if the previous _OFF was
skipped or not. If skipped, it needs to do the same. In normal
suspend/resume cases, these two variables remains '0'. No _OFF() and
_ON() calls are skipped.
entire generated code:
Method (_ON, 0, Serialized) // _ON_: Power On
{
If ((ONSK == Zero))
{
Local0 = \_SB.PCI0.RP01.RTD3._STA ()
If ((Local0 == One))
{
Return (One)
}
Acquire (\_SB.PCI0.R3MX, 0xFFFF)
EMPG = Zero
Local7 = 0x06
While ((Local7 > Zero))
{
If ((AMPG == Zero))
{
Break
}
Sleep (0x10)
Local7--
}
Release (\_SB.PCI0.R3MX)
\_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020,
0x00000020, 0x00000020)
\_SB.PCI0.STXS (0x015E)
If ((NCB7 == One))
{
L23R = One
Local7 = 0x14
While ((Local7 > Zero))
{
If ((L23R == Zero))
{
Break
}
Sleep (0x10)
Local7--
}
NCB7 = Zero
Local7 = 0x08
While ((Local7 > Zero))
{
If ((LASX == One))
{
Break
}
Sleep (0x10)
Local7--
}
}
}
Else
{
ONSK--
}
}
BUG=b:249931687
BUG=b:241850118
TEST=Use above functions and check the generated SSDT table after OS
boot.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72826
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset.
These changes are in accordance with the documentation:
* Intel(R) Emmitsburg Platform Controller Hub External Design
Specification. Document Number: 606161
* Emmitsburg PCH BIOS Specification. Document Number: 631063.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
|
|
When the flash size is over 16M, the absolute address could be lager
than 16M, which can not be taken by CBFS. For the relative address, it
is more flexible.
This is one of series of patches to support 32/64M flash.
BUG=b:255374782
TEST=binary identical test on birman and mayan when
CONFIG_BIRMAN_HAVE_MCHP_FW and CONFIG_MAYAN_HAVE_MCHP_FW are set as
y.
Change-Id: I65be3039cd3449bfb481ad87281b72e88a58bd45
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Select DEBUG_SMI and RUNTIME_CONFIGURABLE_SMM_LOGLEVEL.
Tested=On OCP Delta Lake, SMM log level can be changed via VPD variable.
Change-Id: I73afc944fbd6c21e884397f3049bd363e2c1ce2c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47006
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
|
|
VPD variable 'smm_log_level' can be read and passed to SMM for
overriding SMM log level. By default it's zero therefore it disables
most of the SMM log. When we need to see SMM log we can set this VPD
to a larger value to enable it.
Implement mainboard_set_smm_log_level() that reads VPD variables for SMM
log level.
Change-Id: I90d471d1d070d9a0f1a82ca9da8a2c034c9fd574
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71992
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
|
|
This patch ensures avoiding displaying wrong warning msg as
`Graphics hand-off block not found` during ChromeOS normal mode
booting as FSP is not executing GFX PEIM hence, GFX hand-off HOB
is expected to be missing.
TEST=Able to build and boot google/rex in normal mode w/o having
warning msg.
Change-Id: Ia9192129852195f6183c0c43369cd33b253f9140
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid
prompting wrong dmesg as below.
```
usb usb2-port3: Cannot enable. Maybe the USB cable is bad?
```
Mainboard variants to override the USB ports as per the target
board design.
TEST=Able to build and boot google/rex with all USB ports are
working as expected.
Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Initial Aurash configuration base on moli design.
1. Set up gpio.
2. Add memory config.
3. There is no SD card setting on aurash, remove it from overridetree.
4. Follow moli psys schematic design.
5. Enable BT offload.
BUG=b:269063331
TEST=emerge-brask coreboot.
Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Ia9088cc2937bab72c8c22af592392384a10616a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
|
|
Add a Kconfig RUNTIME_CONFIGURABLE_SMM_LOGLEVEL that enables
mainboard to override mainboard_set_smm_log_level for SMM log level.
This can let SMM have different log level than other stages for
more flexibility.
Another reason is that getting certain data that requires searching
from flash VPD or CMOS is not very ideal to be done in SMM, so in this
change the value can be passed via the member variable in struct
smm_runtime and be referenced directly in SMM.
One example is that mainboard can get the desired SMM log level from
VPD/CMOS, and pass SMM console log level via the variable and in SMM
it can be referenced in get_console_loglevel() override function
directly.
Tested=On OCP Delta Lake, verified SMM log level can be overridden.
Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49460
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
|
|
While executing S0ix tests on Raptor Lake boards, we observed CPU fails
to enter suspend state, causing failure.
As a workaround, disable package C-state demotion, till this issue
is fixed in ucode.
BUG=268296760
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ie50e1024f4118d82d2ad762b54fa722c43990d12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72942
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Change-Id: Iab21376d1887b0c79ea463885520781d042b040d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Some platforms have an onboard speaker which could be used as an
indicator of successful boot or critical error, e.g. in die_notify
function. The function assumes that SPKR GPIO is properly configured
by the platform code.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Per Intel 600 & 700 series PCH EDS (626817), these PCH IDs belongs
to ADL not RPL, though some RPL SoCs are also using ADL PCH.
Hence correct the name reporting to avoid confusion when ADL SoCs
were used.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I61a608e2c99b1d60a99d6ad734b396676f3a2ab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
5) Hynix H58G56BK8BX068
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
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Add support for MTL-P RVP mipi camera functionality
BUG=None
TEST=Build and boot MTL-P RVP to Chrome OS. Verify SSDT entries
related to mipi camera and verify camera working.
Scope (\_SB.PCI0.I2C1)
{
Device (CAM0)
Scope (\_SB.PCI0.I2C0)
{
Device (CAM1)
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I698edd7155fc38477f3416900799e61d3295fd1a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
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This patch adds FW_CONFIG and codec support for MTL-P RVP
BUG=None
TEST=Build and boot MTL-P RVP to Chrome OS. Verify audio codec listed
under aplay -l and audio working with the connected audio card.
localhost ~ # aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: sofrt5682 [sof-rt5682], device 0: Headset (*) []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 1: Speakers (*) []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 5: HDMI1 (*) []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 6: HDMI2 (*) []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 7: HDMI3 (*) []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 8: HDMI4 (*) []
Subdevices: 1/1
Subdevice #0: subdevice #0
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ib29ac3e4105e578e1555076d180b35a8265a99c8
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Built asrock/b75pro3-m with BUILD_TIMELESS=1 and coreboot.rom remains
the same.
Change-Id: I8db6b870f2d4aac35766717866b519921d270f9e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Use the common missing APCB warning when the APCB is missing
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie6303bc3457731bcac322770c4c08712f89fce3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Move missing APCB warning from birman to amd/common so that other
mainboards can utilize the same warnings if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7ae689726ae4f7ccdf6959e47cbb5aee15cdb690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Extend the coverage of the 'ifeq ($(CONFIG_SOC_AMD_COMMON),y)' case to
the entire file. This matches the coverage of the related Kconfig.
Add comments to endif to show which if they are ending.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I369e23e7ee9463ca1ae487d1e2181c760ae1bab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70208
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Configure GPIOs according to schematics
TEST=emerge-brask coreboot
Change-Id: Ib27f1c334cad47b3be57f57b7cc8ca5530118328
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72945
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.
For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.
BUG=b:264704732
TEST=Verified all timings meet spec now
Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The NVPCF DSM subfunction specified a incorrect checksum.
Update this function to the proper checksum of 0xaf.
BUG=b:214581372
TEST=build
Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch enables S0ix for MTL-P RVP platform
BUG=None
TEST=Able to enter low power idle S0 on MTL-P RVP
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
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This reverts commit e30695dbe196ea42864ad03af799706eaae11f02.
for meet thermal criteria, modify PS1/PS2 cutoff to default value
BUG=b:229803757
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72833
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add TPM I2C for aurash to avoid TPM I2C fail.
BUG=b:269050049
TEST=emerge-brask coreboot.
Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: I1947d2e1189f46d8dab01837f75de7cb6e9e0579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since it actually depends on the SoC type whether the old PSP
directory table pointer or the new comboable PSP directory table
pointer is used in EFS, get this information from the SoC ID instead
of passing the comboable flag for the SoCs that need to use the new
comboable PSP directory table pointer.
TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia
Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Create the whiterun variant of the skyrim reference board by
copying the winterhold files to a new directory named for the variant.
BUG=b:265955979
BRANCH=None
TEST=emerge-skyrim coreboot and boot up on Whiterun
Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7
Signed-off-by: Isaac Lee <isaaclee@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a FMAP region to support caching GOP-driver-modified VBIOS tables.
Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP.
Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP.
BUG=b:255812886
TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS
in CBFS, cached VBIOS data is used when not booting in recovery
or developer modes.
Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Commit 45b1da33c80a ("mb/google/hatch: split up hatch and puff
baseboards") moved puff out from under hatch into its own
mainboard dir, but this basebaord include was left behind.
Delete it as it's not needed.
TEST=build hatch variants
Change-Id: I9045c52006fd232552541d68972d831c8b52da27
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Allows Windows/Linux driver to use the proper jack eject debounce time.
Credit to coolstar for identifying the issue.
Change-Id: I32b94b9285f7c85ff1d67b3d78c845835bbf90d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add "SATA" to DSDT as it's referenced by Intel PEP SSDT.
Fixes warning shown in Linux:
ACPI Error: AE_NOT_FOUND, While resolving a named reference
package element - \_SB_.PCI0.SATA (20220331/dspkginit-438)
Change-Id: I65a1d17bce246022859f011cdc4712e1206a98fe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72762
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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The PPCC method should return the package, but is missing the return
statement, leading to DPTF/S0ix to not function properly. Add the
required return statement.
TEST=build/boot Win11 on google/banshee, verify DPTF, S0ix functional.
Change-Id: I051db7d69dd6cdfbb07caf649247ee166c1c74ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72921
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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This patch overrides `SkipExtGfxScan` UPD as the Rex device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.
BUG=b:228002764
TEST=Able to save ~1ms+ boot time on google/rex.
FSP FPDT Data is showing the timestamp between those function calls.
Without this patch:
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131
With this patch:
`CheckOffboardPcieVga` is not getting called.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch allows override to the `SkipExtGfxScan` UPD.
Ideally a platform with an on-board graphics device should skip
scanning external GFX devices aka set this UPD to `1`.
BUG=b:228002764
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00e15b71ed67119df9ca6f98a750ede109ff33fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Follow thermal table to modify setting.
"stapm_time_constant_s" = "200" to "275"
BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7fe05fe1c17258a3323b8d04302212e76a388797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add support for the selective GOP init feature by only running the FSP
GOP driver when necessary: if the FMAP cache is invalid, or if the
board is booted in either recovery or developer mode.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I7ddadc254e05aca0fdd7a9567160a9329cb0e15c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Write the SHA256 hash of the cached VBIOS data when saving to FMAP,
and use it to validate the data read from FMAP on subsequent boots.
Add TPM2 as a dependency to the selection of VBIOS_CACHE_IN_FMAP.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I9c8f23b000b90a1072aeb7a57d3b7b2b2bc626dc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72402
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add methods to store and retrieve the hash of the data stored in the
VBIOS cache FMAP region. Add a dedicated index in TPM NVRAM to store
the hash, and methods to calculate/read/write it.
Modeled after mrc_cache_hash_tpm.{c,h}
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I030017d3bf956b8593bc09073ad6545b80a5b52b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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