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2020-07-01mb/google/octopus/variants/dood: fix disable_xhci_lfps_pm by skuKenneth Chan
due to overridetree.cb set disable_xhci_lfps_pm = 0, need correct condition expression to let function work. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ia047c75611a35aafd15f2481bf64049e13d4a2ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/42860 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01acpi: Avoid freeing a device twiceSimon Glass
The current implementation of acpi_dp_write() frees the node after it has written it. If the structure contains a ACPI_DP_TYPE_CHILD then a recursive call to acpi_dp_write() frees the child and then frees it again when returning from the call. This results in a double free. Split the implementation into two steps, one that ones and one that frees. This is easier to understand and fixes the bug. Note: This likely has no effect in coreboot since it doesn't seem to have a proper free() implementation. But it might gain one one day. BUG=none Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ife3917af10bc35a3c3eee38d8292f927ef15409d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42892 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Clear interrupt and wake status when configuring padsFurquan Shaikh
This change clears interrupt and wake status for a pad when configuring it. This ensures that stale interrupts/wake notifications are flushed out and do not cause spurious wakes in future suspends. BUG=b:159944426 Change-Id: Ia4ebd975312a4136f1d0690d7af7372615e31f0f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Add new helper macro PAD_CFG_STRUCT_FLAGSFurquan Shaikh
`flags` field of soc_amd_gpio structure is set only for SCI and SMI configurations. This change adds a new helper macro PAD_CFG_STRUCT_FLAGS that allows setting of all soc_amd_gpio members including `flags` field. This can be used directly by PAD_SCI and PAD_SMI. For all other pad configurations, PAD_CFG_STRUCT macro uses PAD_CFG_STRUCT_FLAGS with flags set to 0. This allows dropping of redundant parameter 0 for flags for all other pad configurations. BUG=b:159944426 Change-Id: I835b62f5502375ffc4215548b51338a67546d699 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/gpio, mb/{amd,google}: Configure pads using a single entry in GPIO ↵Furquan Shaikh
configuration table Currently, for Stoneyridge and Picasso mainboards, pads that are configured for SCI/SMI/WAKE need to have multiple entries in the configuration table - one for PAD_GPI and other for the special configuration that is required. This requires a very specific ordering of pads within the table and is prone to errors because of conflicting params provided to the different entries for the same pad. This also does not work very well with the concept of override GPIOs where the entry in base table is overridden with the first matched entry from the override table. This change updates the way GPIO configuration is handled for special routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of soc_amd_gpio structure in the macros performing these configurations. Also, program_gpios() is updated to perform a write to GPIO control register instead of read-modify-write. This is because mainboard is expected to provide only a single configuration entry for each pad within a given table. Thus, there is no need to preserve earlier configuration. Mainboards that were providing multiple entries for a single pad are updated accordingly. BUG=b:159944426 Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Use gpio_setbits32()Furquan Shaikh
Some codepaths want to set selected bits of a hardware register to match those of a given variable in memory. Provide a helper function for this purpose and use it in gpio_set(), gpio_input_pulldown() and gpio_input_pullup(). This change also adds GPIO_PULL_MASK and updates GPIO_OUTPUT_MASK to include all bits dealing with pull and output respectively. Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODLFurquan Shaikh
H1 is not a wake source and hence there is no need to configure SCI GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9 i.e. H1_PCH_INT_ODL. BUG=b:159944426 Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30mb/amd/padmelon: Drop SCI configuration for GPIO_137Furquan Shaikh
GPIO_137 does not have any gevent associated with it. This change drops the configuration of GPIO_137 as SCI for padmelon. Change-Id: I0579d05bda4523bbb5e3441d2a3b6e2b33b05cfc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42873 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Add macros for setting fields of soc_amd_gpioFurquan Shaikh
This change adds helper macro PAD_CFG_STRUCT for setting the fields of `soc_amd_gpio`. Additionally, macros are added for different operations i.e. pull, output, trigger, int_enable, event_trigger, wake_enable, debounce, etc. All GPIO configuration macros are updated to use PAD_CFG_STRUCT instead of setting the fields directly. BUG=b:159944426 Change-Id: I03535d2da0c05f72c4163fa30d72f9c6df44908b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42872 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/lpc: Skip SERIRQ setup when using eSPIMarshall Dawson
BUG=b:157984427 TEST=check value of PMx054 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2ca14c137ed784a1a7cfeed969719f46fc8230f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-30soc/amd/common/gpio: Rename GPIO debounce macrosFurquan Shaikh
This change updates the macros for GPIO debounce to add _DEB_ in the name. This is done to make the names consistent with rest of the GPIO control field names. BUG=b:159944426 Change-Id: Ic47678108c871c5f1cd0d512783230f18adf3484 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Update the macros for interrupt and pad filteringFurquan Shaikh
This change renames GPIO macros as follows: 1. Pad filtering macros are renamed to GPIO_TRIGGER_ and GPIO_ACTIVE_. This determines the filtering applied on the input signal at the pad. 2. Interrupt enabling macros are renamed to GPIO_INT_ENABLE_. _INT_ is dropped from pad filtering macros because the filtering applies to the input signal irrespective of how it is routed. It is applied at the pad not only for GPIO interrupts but also for other routes i.e. SCI, SMI, etc. BUG=b:159944426 Change-Id: Id0ad770be77409aaaae4cc135945e2815ce97030 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42870 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Make macro names for GPIO flags consistentFurquan Shaikh
`soc_amd_gpio` structure uses a flag field to store additional information about GPIO configuration that does not end up directly in the GPIO control register. However, the naming for these flags is not consistent across event triggers and special configurations. This change updates the flag names to be consistent (starting with GPIO_FLAG_*) and adds some helper functions for GPIO events. In the following CLs, more changes will be made to drop some of the special flags which are not really required. BUG=b:159944426 Change-Id: Idca795c3e594eb956d297d5ba5d08f75b5563ee5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src/arch/x86: Ensure $(objgenerated) exists before it's usedPatrick Georgi
In some rare cases it seems that make tries to build $(objgenerated)/assembly.inc before the build-dirs target has finished, and so assembly.inc can't be written. Enforce that build-dirs is done before assembly.inc starts. BUG=chromium:1098215 BRANCH=none TEST=none Change-Id: Ib141ea45a43836cfdde0059523c331fe5286b06d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dtEdward O'Callaghan
BUG=b:159187889 BRANCH=none TEST=none Change-Id: I13626a236f1b7385208c4181150f094cbda490ed Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-30soc/intel/cannonlake: Add UWES ASL into xhci.aslEdward O'Callaghan
Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`. This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:159187889 BRANCH=none TEST=none Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30jasperlake: enable tcc_offset functionalitySumeet R Pawnikar
This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset value to new value in devicetree. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I58e4fa362f20efeef84e06e64d70ee7c4f9554d6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30mb/google/volteer: set tcc_offset value to 10Sumeet R Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value Change-Id: I6438547e09a3ff3a1c01addfcc01383e89f5b435 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30tigerlake: enable tcc_offset functionalitySumeet R Pawnikar
This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset to new value in devicetree. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I36b0d6aad4be8a9cbb145dcd66d65235d3f6ac35 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30soc/amd/common/gpio: Drop unused macro GPIO_TRIGGER_INVALIDFurquan Shaikh
This change drops unused macro GPIO_TRIGGER_VALID from gpio_banks.h. BUG=b:159944426 Change-Id: Ie115f37893d9ba190bab56cf8b037febd8b5f4b5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30sb/intel: Add include guards on nvs.hKyösti Mälkki
Change-Id: I110974f3161f2991536df50acdfe32f68bd2cc60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42850 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30Add qc_blobs repositoryJulius Werner
This patch adds a separate blobs repository for Qualcomm blobs, analogous to the existing AMD blobs. Qualcomm's binary licenses allow files to be redistributed and used by anyone, but they explicitly require the user to agree to the license terms when just *downloading* the binary (even if they're not using them to build any firmware). Some community members do not like to have to agree to licenses for files they're not actually using, so we are keeping these files separate from the main blobs repository and adding an extra Kconfig to make sure the user is aware of and must explicitly agree to this before downloading these files. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30Revert "amd/pi/hudson: Add GPIO get function"Kyösti Mälkki
This reverts commit dae95f0dfe9ad94922c940d3c0522d53284b4deb. There is filename conflict with top-level <gpio.h> and incompatibility with it. Only use was AMD_PI_KERN and we have no such platform in the tree anymore. Change-Id: I120b0bfda1501e9941c71315852d87d251f76a5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42743 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu
Add CpuReplacementCheck to chip options to control UPD FSPM SkipCpuReplacementCheck from devicetree. This UPD allows platforms with soldered down SoC to skip CPU replacement check to avoid a forced MRC traning. TEST=boot and verified with volteer Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. Found-by: Coverity CID 1429981 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iea3801585e8c294fb889a8137b534bb932696025 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42836 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src/drivers/intel: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. Found-by: Coverity CID 1429979, 1429982 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If17d12861f562dc0d6c98a5c91a9d3c0360ca2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42835 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src/mb: Use macro for access_sizeElyes HAOUAS
Change-Id: I275c86ef5833d87378cff1e1bd228776e007dad3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30mb/lenovo/x60: Use tabs for aligning the "\"Elyes HAOUAS
Change-Id: Id4ada670d35208c40f2eb07308e6732c2a85dbe1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-30mb/google: Drop aliases for APM_CNT_ACPI_xxKyösti Mälkki
Use defines found in <cpu/x86/smm.h>. Change-Id: Ib75df13021120fb2c056782c252e97d6b036c7da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30mb/intel,samsung: Drop unused static gnvs_Kyösti Mälkki
Change-Id: I920e5e6a3fa92ede4a0b0388962b55208a7dee48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-29soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdtFelix Held
Found-by: Coverity CID 1429980 Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-29mb/amd/mandolin: make mandolin a variant of itselfFelix Held
A follow-up patch will add Cereme which is a Mandolin variant. Beware that the name of the EC firmware image is changed from mchp.bin to EC_mandolin.bin. TEST=Mandolin still boots into Linux live system. Change-Id: Ifee91306756f8a4152a6a0224e172dae7eac8f7a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42785 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/amd/picasso/soc_util: add comment on the silicon and soc typesFelix Held
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-29mb/lenovo/{x230, x230s}: Disable SuperSpeed capabilities for WWAN USBBill XIE
Although on ThinkPads with Panther Point PCH the usb port inside wwan socket is usually wired to XHCI, it has actually no SuperSpeed lines, so maybe it is okay to disable SuperSpeed capabilities, and wire them to EHCI #2 by making use of XUSB2PRM and USB3PRM. This applies to both variants of x230. Change-Id: Ia8d27be84e4dbfa0efed506b9fc010e7f4d6ba23 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41505 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29mainboard/lenovo/x230: Add ThinkPad x230s as a variantBill XIE
The code is based on autoport and that for X230. Major differences are: - Only one DDR3 slot - HM77 PCH - M.2 socket instead of mini PCIe - No docking - No TPM Tested: - CPU i5-3337U - 8GiB SO-DIMM - Camera - PCIe and USB2 on M.2 slot with A key for WLAN - SATA and USB2 (no SuperSpeed components) on M.2 slot with B key for WWAN - On board SDHCI connected to PCIe - USB3 ports - libgfxinit-based graphics init - NVRAM options for North and South bridges - Sound - ThinkPad EC - S3 - Linux 4.9 within Debian GNU/Linux stable, loaded from SeaBIOS. Untested: - Touch screen, which is said to work under ubuntu but not debian. Change-Id: Id59cdc5479aaf70809dd1ca613056263661455eb Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41390 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/amd/common: Refactor GPIO SCI/SMI interruptsKyösti Mälkki
Change-Id: Ib2c7cd70ab38d0d8e745b0a611b780d2b0b8dc5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-29soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enableKyösti Mälkki
There is no GPIO_63 but the register position is used for interrupt controls. Change-Id: I754a2f6bbee12d637f8c99a9d330ab0ac8187247 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42686 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL takes advantage of the property. Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_opsWilliam Wei
pmc_set_acpi_mode() should run after Chrome EC dealt with all host event bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test will fail). BUG=b:153249055 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Change the GBB flag to 0x140 then check SMI mask during depthcharge phase, make sure it's 0x0000000000000001. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt socJonathan Zhang
The previous Intel CPX-SP FSP release was ww20 release. The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end flow of using memory training data to generate FSP_NV_STORAGE HOB and using memory training data passed from bootloader to skip memory training, works now. This saves 8 minutes of boot time (with FSP verbose logging enabled on DeltaLake server). This release also adds UPD parameters to support IIO bifuration. The ww24 release has following updates: a. Removed a number of unnecessary UPD parameters, such as mmiolSize, mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate. b. Added UPD parameters to support PCIe ports configuration. c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit fields, in addition to PCIe resource memory base/limit fields. With ww24 release, the issue with PCIe link training persists. On YV3 config A, the onboard NIC card has x4 connection to port 2D. This NIC device is not recognized by FSP. Corresponding soc/intel/xeon_sp/cpx change is made: * There are changes in PLATFORM_DATA structure, so hob_display.c is updated. * There are changes in UPD parameters, so romstage.c is updated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28soc/amd/common: Allow runtime mapping of ACPIMMIO banksKyösti Mälkki
Future implementation of verstage running on PSP will have access to some of the ACPIMMIO banks, but banks will be mapped runtime at non-deterministic addresses. Provide preprocessor helpers to accomplish this. Change-Id: I8d50de60bb1ea1b3a521ab535a5637c4de8c3559 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-06-28soc/amd/common: Access ACPIMMIO via proper symbolsKyösti Mälkki
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100Kyösti Mälkki
Use the pre-defined constant address directly. Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28mb/google/zork: update DRAM SPD table for berknipKevin Chiu
samsung-K4A8G165WC-BCWE_x1 # 0b0101 micron-MT40A1G16KD-062E-E_x2 # 0b0110 hynix-H5ANAG6NCMR-XNC_x2 # 0b0111 samsung-K4AAG165WA-BCWE_x2 # 0b1000 BUG=b:159418772 BRANCH=master TEST=emerge-zork coreboot Change-Id: I24b632c75d4a0660dc6beb88f135b546860d7079 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42814 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD ↵Johnny Lin
variable If VPD_SMBIOS_VERSION is selected, it would read VPD_RO variable that can override SMBIOS type 0 version. One special scenario of using this feature is to assign a BIOS version to a coreboot image without the need to rebuild from source. VPD_SMBIOS_VERSION default is n. Tested=On OCP Delta Lake, dmidecode -t 0 can see the version being updated from VPD. Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: insomniac <insomniac@slackware.it> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-06-28soc/intel/common: add TCC activation functionalitySumeet R Pawnikar
This enables to configure the Thermal Control Circuit (TCC) activation value to new value as tcc_offset in degree Celcius. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action before CPU temperature reaches maximum operating temperature TjMax value. Also, cleanup local functions from previous intel soc specific code base like for apollolake, broadwell, skylake and cannonlake. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-28mb/google/zork: update telemetry settings for berknipKevin Chiu
update telemetry to improve the performance. BUG=b:154879805 BRANCH=master TEST=emerge-zork coreboot verify by Stardust test Change-Id: Iae5486cf2ee26b3d8e6124edfff4fe2d1fbe211e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42817 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28mb/google/zork: add G2 TS support for berknipKevin Chiu
Add G2 GTCH7503 HID TS support BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Id9ed5fc768459edc4660ddd6fbffb0b1973ce6d1 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-28mb/google/zork: update telemetry settings for morphiusKevin Chiu
update telemetry to improve the performance. BUG=b:154863613 BRANCH=master TEST=emerge-zork coreboot Change-Id: Ia08259e81f360259f23ea0f9c5c128c9d0961322 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28mb/google/zork: update DRAM SPD table for morphiusKevin Chiu
Add Samsung K4A8G165WC-BCWE x2 BUG=b:159418770 BRANCH=master TEST=emerge-zork coreboot Change-Id: I200a1074d3c9fe79a8a2c69f42b0612e745f36f5 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28mb/google/reef/variants/: add Samsung K4F8E3S4HD-MGCL supportKevin Chiu
Add Samsung K4F8E3S4HD-MGCL DRAM support. DRAMID: 0x8 BUG=b:145094527 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ic450c4abebfeaed050a7b8fcae74b87a148dd5cd Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28soc/xeon_sp/cpx: Define MSR PPIN related registersJohnny Lin
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/ Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-28drivers/ipmi: Read more FRU data fields for Product and Board InfoJohnny Lin
Tested on OCP Tioga Pass Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ib05fdb34b2b324b6eb766de15727668ce91d2844 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40522 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28mb/google/faffy: Enable USB2 port6Tim Chen
Due to faffy has PL-2303 connect to USB2 port6(count from port0), needs to enable it. BUG=b:159760559 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-28mb/amd/mandolin: factor out eMMC GPIO pin mux setupFelix Held
This also makes the calling of the eMMC GPIO mux setup function conditional on PICASSO_LPC_IOMUX instead of AMD_LPC_DEBUG_CARD which only makes the selection of PICASSO_LPC_IOMUX user-configurable. Change-Id: Ic49a668f82fbc1b851c07d312b543d2889fe4734 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-28mb/amd/mandolin: factor out port descriptors from mainboard.cFelix Held
Change-Id: Ia2101cc0bae0d68cea1954424d18833aa22670c6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42784 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28soc/amd/picasso/soc_util: rework reduced I/O chip detectionFelix Held
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort connectivity. While Dali can either be fused-down PCO or RV2 silicon, Pollock is always RV2 silicon. Since we have all boards using this code in tree right now, soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku(). Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28gpio_keys: Allow boards to configure different wakeup routesFurquan Shaikh
This change allows mainboard to configure different wakeup routes that can be used by a GPIO key: 1. SCI: This is selected when SCI route is used to wake the system. It results in _PRW property being exposed in ACPI tables. 2. GPIO IRQ: This is selected when GPIO controller wake is used to wake the system. It is typically used when the input signal is not dual routed and the GPIO controller block is not capable of applying filters for IRQ and wake separately. In this case, _PRW is not exposed in ACPI tables for the key device. 3. Disabled: No wakeup supported. Based on these wakeup routes, gpio_keys_add_child_node() is updated to expose _PRW and _DSD properties for wakeup appropriately. Additionally, the change updates mainboards that were already using gpio_keys to set wakeup_route attribute correctly and renames "wake" to "wake_gpe" to make the usage clear. BUG=b:159942427 Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-27sb/intel/i82801jx: Use pmutil.h definitionsAngel Pons
Also drop now-redundant definitions and include headers where needed. Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I2fb46bb04d96df5e8261f49e0fd4d88eedca6084 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42659 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801ix: Use pmutil.h definitionsAngel Pons
Also drop now-redundant definitions and include headers where needed. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801jx: Drop `p_cnt_throttling_supported`Angel Pons
The three mainboards using this southbridge do not support it. Change-Id: I006f1ec26c40f7e2dfc2ddedb017278455368bb9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42655 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801ix/fadt.c: Use pmutil.h definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ib4cdeaaaf75818fff21acb628d198781b07aec80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42654 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801jx/fadt.c: Use pmutil.h definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I572a9da0cba5d23c48c4cb06de4bb75f65f5b0b0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-06-27sb/intel/i82801gx/fadt.c: Align with i82801ixAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: I930de15a6746936fa4a8f6db280b5ac60176c836 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-27sb/intel/i82801gx/fadt.c: Reorder statementsAngel Pons
Change the order of the assignments to match that of i82801ix. This changes the binary but the effective result should be the same. Change-Id: Id720fce40e751295e629585d34017f10af2b5c7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42651 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801gx: Move `acpi_fill_fadt` to fadt.cAngel Pons
At least i82801ix and i82801jx do this. Change-Id: I7ff2459d82eb7933ed80180a69f0f323b8ecd25f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-27sb/intel/i82801jx/fadt.c: Align with i82801ixAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I13b972440459a62777ee2a4688d1d8af147d8921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-27sb/intel/i82801jx/fadt.c: Reorder statementsAngel Pons
Change the order of the assignments to match that of i82801ix. This changes the binary but the effective result should be the same. Change-Id: Ib190781f26f82f339eaf8039de459376ac0e3a5e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-27sb/intel/i82801jx: Move `acpi_fill_fadt` to fadt.cAngel Pons
At least i82801ix does this. Change-Id: Ic555ab17c2eca0399938d2842ca51628899c1544 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42637 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27mb/emulation/qemu-q35: Use common early SPI codeAngel Pons
Tested, it still boots. It is unknown whether this has any effect on emulated hardware, which is most likely not emulating SPI transfers. Change-Id: I44397c46dc0715697ca8680f418888804e4ea7e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27soc/intel/broadwell: Use common early SPI codeAngel Pons
Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/lynxpoint: Use common early SPI codeAngel Pons
Change-Id: I6c6fbed077d2f169736aee77af3783c847cf3a06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/ibexpeak: Use common early SPI codeAngel Pons
Change-Id: Ib8cba1ae4fc269c925418965acf6956c1bfe0f79 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/i82801jx: Use common early SPI codeAngel Pons
Change-Id: If9efbde5939913b67852b377dd84cd4de1ec2718 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/i82801ix: Use common early SPI codeAngel Pons
Change-Id: Iafcf7aecb20b4c8be79fa562ff267fd54f672862 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/i82801gx: Use common early SPI codeAngel Pons
Change-Id: I44de4698d062508dd24f37b37014e09d95726c71 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/bd82x6x: Use common early SPI codeAngel Pons
Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42661 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/common: Add early SPI codeAngel Pons
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash. As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway. Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-26Revert "Mushu: Enable PCIe 1d.4 to enable dgpu"Shelley Chen
This reverts commit 1408798637125f1707ded7215e22461c623a79a8. Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause. BUG=b:159370566 BRANCH=None TEST=boot up device and make sure when kernel is booted, backlight comes up. Change-Id: I643854c6c805d262539bbb482808e8c322059a49 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-06-26soc/rockchip: Use (Q) instead of @Stefan Reinauer
This way make V=1 will tell you what it's actually doing. Change-Id: I096bc2419e47a0b2a2454a792059464b27158cd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42818 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mb/mandolin/devicetree: clarify that Ethernet devices are internal MACsFelix Held
Change-Id: Ib7d696f4cc8f5fdcdf45e271b36664d085eb16d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42834 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mb/amd/mandolin/devicetree: disable unused internal ethernet controllersFelix Held
Change-Id: Id4c7ec02f37b35bbc36d40bb937b962cc6413d17 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42782 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mb/google/zork/Kconfig: remove unused option IRQ_SLOT_COUNTFelix Held
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which it doesn't. Change-Id: Ib5839a42f5133f5f84e1e1e4e587801b916ca571 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-26mb/amd/mandolin/devicetree: add comment about chip behind GPP bridge 3Felix Held
Change-Id: Ie1fcfb18a3ccf08c62210eec07d8965696f11da9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-26mainboard/prodrive/hermes: Enable EIST in DeviceTreeChristian Walter
Enable EIST option in the devicetree in order to make Windows aware of using Intel CPU Turbo Technology. Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-26mb/google/hatch: Set Reset Power Cycle Duration for hatch platformsSridhar Siricilla
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay. Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0 With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0 Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s. Test=Verified on Hatch and Puff boards BUG=b:158634281 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/volteer: Enable HECI interfaceJamie Ryu
This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite. BUG=b:159615125 TEST=Build and boot volteer. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0 Change-Id: I68eb51c6a0af77982c060767993265764a2bc926 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-25mb/amd/mandolin: remove unused option IRQ_SLOT_COUNTFelix Held
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which it doesn't. Change-Id: I76c098c7029ed9d797f6c4fb016eaa18854fadd3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25mb/amd/mandolin: add missing Kconfig type to CBFS_SIZE optionFelix Held
Change-Id: Ia4226537d17bb3732086980fb4e8de6bd1eaedbb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage"Kyösti Mälkki
This reverts commit 4883252912665f56c8e7801fe03a26594a1e9d5d. Almost everything in <amdblocks/acpimmio_map.h> is invalid for PSP as it does not have the same view of memory space. The prototypes xx_set/get_bar() are only valid for PSP as x86 cores will use the constant mapping defined in <amdblocks/acpimmio_map.h> The selected MMIO base address model depends of the architecture the stage is built for and, to current knowledge, nothing else. So the guards should have been with ENV_X86 vs ENV_ARM and not about CONFIG(VERSTAGE_BEFORE_BOOTBLOCK). For the ENV_ARM stage builds, <arch/io.h> file referenced in the previously added mmio_util_psp.c file has not been added to the tree. So there was some out-of-order submitting, which did not get caught as the build-testing of mixed-arch stages has not been incorporated into the tree yet. The previously added file mmio_util_psp.c is also 90% redundant with mmio_util.c. Change-Id: I1d632f52745bc6cd3c3dbddb1ea5ff9ba962c2e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42486 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25Revert "mb/pcengines/apu2: Update GPIO Reads & writes"Kyösti Mälkki
This reverts commit 87f9fc8584c980dc4c73667f4c88d71d0e447a0c. GPIO configuration is supposed to be abstracted using <gpio.h> and the details of ACPMMIO GPIO bank hidden. This commit took it the opposite direction. Change-Id: Iacd80d1ca24c9d187ff2c8e68e57a609213bad08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42684 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/amd/mandolin: Drop empty help textPatrick Georgi
kconfig complains. Change-Id: I281e4faa53cad5677864305feb9162b598ae483e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25mb/amd/mandolin: Quote string in Kconfig that contains /Patrick Georgi
Newer versions of Kconfig require that. Change-Id: I95f889d462ace1b912b5e6c7320973e8a826f3cb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42773 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25soc/intel/cannonlake: Add PchPmPwrCycDur to chip optionsSridhar Siricilla
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur from devicetree. The UPD determines the minimum time a platform will stay in reset during host partition reset with power cycle or global reset. This patch also ensures configured PchPmPwrCycDur value doesn't violate the PCH EDS specification. TEST=Verified on Hatch and Puff boards Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-25sb/intel/i82801ix/Kconfig: Sort options alphabeticallyAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I6f49af457f104dbf73e156f46ce09103ca9dccdb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42647 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25sb/intel/i82801jx/Kconfig: Sort options alphabeticallyAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: Ie5b87726cccf9fb8e45db39a6d6fba8ac4342f5f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42646 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25sb/intel/i82801{gx,jx}/nvs.h: Add include guardsAngel Pons
Change-Id: Ib7eb3469b03fd58afa1f6cb5822f7c6f1cac35e0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42645 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT`Angel Pons
Most other Intel southbridges call those `TPSV` and `TCRT` instead. Change-Id: Id4c30cd53abc544b743eb80696bfafe45929208e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42644 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 23:31:55 +0000