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2013-02-11spi.h: Rename the spi.h to spi-generic.hZheng Bao
Since there are and will be other files in nb/sb folders, we change the general spi.h to a file name which is not easy to be duplicated. Change-Id: I6548a81206caa608369be044747bde31e2b08d1a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2309 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-11AMD/Persimmon: Enable the 2nd COM portDave Frodin
The hardware is there, so turn it on. Change-Id: I40aff1e84a22a05599c62b9f0b20397df0a40b15 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2353 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11Supermicro H8QGI: Substract 1 from MMCONF range limitKonstantin Aladyshev
MMCONF space is defined by two config parameters: MMCONF_BASE_ADDRESS (0xF800 0000) MMCONF_BUS_NUMBER (64) Coreboot allocates 1MB per bus, so MMCONF limit should be: 0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF Current code does not have (-1) component, this makes MMCONF limit equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG lower two bytes of MMIO limit always equal 0xFFFF: MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}. Add (-1) to correct this issue. No functionality change has been experienced. The five times slower RAM speed compared to the proprietary vendor BIOS still remains. Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2193 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11AMD SB900: fix warningsMartin Roth
Add a prototype to a .h file Remove an unused file (GppHp.c) from the build by deleting it from the makefile. I left the file since this is vendorcode. This is the code for PCIe hotplug. Inside GppHp.c, make functions not called from outside static. This obviously isn't important since the file isn't used, but for the sake of the cleanup I thought I'd go ahead with it... This was tested with the torpedo build. This fixes these warnings: src/vendorcode/amd/cimx/sb900/Dispatcher.c: In function 'LocateImage': src/vendorcode/amd/cimx/sb900/Dispatcher.c:193:38: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/cimx/sb900/Usb.c:740:1: warning: no previous prototype for 'XhciA12Fix' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:65:1: warning: no previous prototype for 'sbGppHotPlugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotPlugSmiProcess': src/vendorcode/amd/cimx/sb900/GppHp.c:76:5: warning: implicit declaration of function 'SbStall' [-Wimplicit-function-declaration] src/vendorcode/amd/cimx/sb900/GppHp.c: At top level: src/vendorcode/amd/cimx/sb900/GppHp.c:101:1: warning: no previous prototype for 'sbGppHotUnplugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:134:1: warning: no previous prototype for 'sbGppHotplugSmiCallback' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotplugSmiCallback': src/vendorcode/amd/cimx/sb900/GppHp.c:158:5: warning: implicit declaration of function 'outPort80' [-Wimplicit-function-declaration] Change-Id: I5a1a20eeb81e1f4d59e3e3192f081e11d8506f56 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2349 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11AMD S3: Add missing erasing flash sector for saving MTRR registerZheng Bao
It has worked up to now because the region is already erased the first time the board boots, and every additional boot the same data is being written over the old data.(by Dave Frodin) Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2304 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11AMD S3: Change the hardcoded data size to macros.Zheng Bao
Change-Id: Ieefc4213a6dee9c399826b1daa98bbf4bc10d881 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2303 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11snow: make build script erase 192KB instead of 128KBDavid Hendricks
This will make the build script wipe out more flash memory content. Our image is a bit bigger now that we're testing with payloads, so this is just added paranoia to prevent weird surprises caused by not flashing the full image. Change-Id: I31969922079e96886573d9d802266eb0052277cd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}David Hendricks
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply the same way on ARM platforms. On x86 they refer to the low memory region where coreboot tables reside. However on ARM we don't have such a region which is architecturally defined. So instead we'll use the CPU-defined DRAM base address and the mainboard-defined DRAM size. This also has the pleasant side-effect of fixing the coreboot tables to not clobber ramstage code... Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7/snow: Remove unused modules in bootblock and romstage.Hung-Te Lin
For Exynos/snow, cpu_info and power modules and also some parts of the GPIO API (which require timer and pwm modules) are not used in the current bootblock. Clock init only needs to be used if early console is enabled. Now our bootblock is 22420 bytes with early serial console and 11192 bytes without. Those include the 8KB BL1 region. Change-Id: I9c958dafb9cf522df0dcfbef373ce741aa162544 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2322 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10exynos/snow: move SPI GPIO setup to mainboard bootblock codeDavid Hendricks
This moves GPIO setup from chip-specific SPI code to mainboard- specific bootblock code. This makes exynos_spi_open a bit more generic so it can eventually be used for any SPI channel. This also benefits CBFS since the user can set media->context to to any set of SPI registers. Change-Id: I2bcb9de370df0a79353c14b4d021b471ddebfacd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2347 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10exynos/snow: set SPI clock rate in romstage mainDavid Hendricks
This moves the setting of SPI clock rate into romstage's main, which allows us to eliminate a bunch of dependencies from the bootblock (about 7KB worth). Change-Id: I371499bb4af6a6aa838294bc56f9dbc21864957a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2346 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7/exynos5250: place .id between .start and bootblock mainDavid Hendricks
This places the .id section toward the lower region of the coreboot image, before the bootblock. It's easier for humans to find by dumping the image and it also eliminates ID_SECTION_OFFSET which is currently the upper bound on our image size. Change-Id: I7d737b901dac659ddf9aa437cee5dc32f1080546 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2345 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7: make bootblock linker script more explicitDavid Hendricks
This adds a .bl1 and .start symbol that is placed at the beginning of the .rom section. The goal is to move the .id section in between the reset vector and bootblock_main. Change-Id: Ie732ce656d697c059cc0fa40c844b39f53fc214c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2344 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7/exynos: make BL1_SIZE_KB consistent with numbers used...David Hendricks
The Kconfig variable indicates KB, but the number used was bytes. Let's just assume KB is correct for now. Change-Id: I910c126104f0222fc48b70a18df943f2afddeca3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
In particular: MSR_PMG_CST_CONFIG_CONTROL MSR_PMG_IO_BASE_ADDR MSR_PMG_IO_CAPTURE_ADDR Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2337 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09romcc: Use default romcc flags for most boardsPatrick Georgi
Except for one board, the flags can be derived from CONFIG_MMX and CONFIG_SSE. Change-Id: I64a11135ee7ce8676f3422b2377069a3fa78e24d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09romcc: Don't use user overridable romcc flags for bootblockPatrick Georgi
The bootblock is typically run before fpu/mmx/sse setup, so we can't rely on -mcpu=p4 and the like to increase the register space. bootblock_romccflags does that for SSE, but they're controlled separately. Change-Id: I2b0609ac18b2394a319bf9bbbee1f77d2e758127 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09armv7: update coreboot tables for armv7David Hendricks
This is a first-pass attempt at cleaning up the coreboot tables for ARM. The most noticable difference is that there is no longer both a high and a low table. Change-Id: I5ba87ad57bf9a697b733511182c0326825071617 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09snow: do something useful in ramstage()David Hendricks
This cleans up Snow's trivial ramstage, gives it a coreboot table address and calls hardwaremain(). Change-Id: I84c904bcfd57a5f9eb3969de8a496f01e43bc2f6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7/snow: add BL1_SIZE_KB and get rid of magic constantsDavid Hendricks
This adds a BL1_SIZE_KB config variable so that we can get rid of some magic constants. Change-Id: I9dbcfb407d3f8e367be5d943e95b032ce88b0ad0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2332 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7: include $(obj)/config.h when building bootblockDavid Hendricks
Explicitly including it allows us to get rid of some magic constants in the bootblock linker script. Change-Id: I095899babc997addce6b383f00e5ebf135e99d5e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2331 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09DEBUG_CBFS should not depend on TPMDavid Hendricks
This seemed to have been introduced in fe422184. Change-Id: I4f9ecfbec42aa8c0bb8887675a3add8951645b98 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2327 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09document Intel VMX locking behaviorMike Frysinger
Add a comment explaining that the existing lock bit logic is correct and "as designed" even though the manual states otherwise. This way people don't have to "just know" what is going on. Change-Id: I14e6763abfe339e034037b73db01d4ee634bb34d Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/2326 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-08VBE: Skip graphics mode setting for non-VGA devicesStefan Reinauer
This hit me when running the latest Qemu with coreboot: First the graphics OPROM is running, then an iPXE OPROM. The iPXE OPROM has no int10 support (obviously) so calling vbe_set_graphics() wipes the framebuffer information from the coreboot table. Change-Id: Ie0453c4a908ea4a6216158f663407a3e72ce4d34 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2325 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-08console: Fix using CMOS for optionsPatrick Georgi
Just a tiny mistake, but it made the console driver assume that CMOS data isn't available. Change-Id: I4e6f53e9ed59024de7b09333f82f0ce3235ef8f6 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/2323 Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-08oprom: fix compilation for Qemu target (and possibly others)Stefan Reinauer
Not sure why this didn't bite us earlier.. src/device/oprom/realmode/x86.c: In function 'fill_lb_framebuffer': src/device/oprom/realmode/x86.c:272:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:274:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:275:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:276:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:278:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:280:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:281:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:283:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:284:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:286:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:287:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:289:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:290:13: error: dereferencing pointer to incomplete type Change-Id: Ie3b0f731a7b995e954a26e745b07fc122088ca9f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2321 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08armv7/snow: Move clock initialization from bootblock to romstage.Hung-Te Lin
Exynos system clock can be initialized before RAM init, not necessary to be in the very beginning (boot block). This helps reducing bootblock dependency. Verified to boot on armv7/snow. Note: this patch was originally introduced in 2308, but there were some ordering issues so it was reverted. Change-Id: Ibc91c0e26ea8881751fc088754f5c6161d011b68 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08armv7: Use same console initialization procedure for all ARM stagesHung-Te Lin
Use same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> ... console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08console: Only print romstage messages with EARLY_CONSOLE enabled.Hung-Te Lin
Revise console source file dependency (especially for EARLY_CONSOLE) and interpret printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly stops romstage messages on x86/qemu (armv7/snow needs more changes to work). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2300 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08console: Always allow setting "EARLY_CONSOLE" configuration.Hung-Te Lin
Early console should always be allowed to be turned on / off (for generating production and debug versions), and should not be enforced by "select" Kconfig rule. A new "DEFAULT_EARLY_CONSOLE" is introduced for devices to select if they prefer early console output by default. Verified Kconfig value on qemu/x86 (default y by CACHE_AS_RAM), snow/x86 (default y by EXYNOS5 config), and intel/jarrell (default n). Change-Id: Ib1cc76d4ec115a302b95e7317224f1a40d1ab035 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2307 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08exynos/snow: Configure UART peripheral during console initialization.Hung-Te Lin
For Exynos platforms, the UART component on pinmux must be first selected and configured. This should be done as part of UART console initialization. Note, that the current implementation hard-codes the device index as UART3, while the base port can be assigned to different device in Kconfig. This will be fixed later. Verified to work on armv7/snow. Change-Id: Ie63e76e2dac09fec1132573d1b0027fce55333a1 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2315 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08console: Revise serial console configuration names.Hung-Te Lin
The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08Revert "armv7/snow: Move clock initialization from bootblock to romstage."David Hendricks
This reverts commit 9029f4b63f6d0e29bf1608e666cdb025de45ca24 This patch needs to go at the end of the UART patch set. Sorry 'bout the confusion! Change-Id: I5702c7d6130daf95776f2c15d24e5d253691cefd Reviewed-on: http://review.coreboot.org/2319 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-07armv7/snow: Move clock initialization from bootblock to romstage.Hung-Te Lin
Exynos system clock can be initialized before RAM init, not necessary to be in the very beginning (boot block). This helps reducing bootblock dependency. Verified to boot on armv7/snow. Change-Id: Ic863e222871a157ba4279a673775b1e18c6eac0d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2308 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-07YABEL: use system {in,out}[bwl] on x86Patrick Georgi
The prototypes that were recently defined only work for the internal implementations. Change-Id: Ib34bb75a0b882533da550b9cd17cd777c2463e02 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/2318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07armv7/snow: Remove power_init from bootblock.Hung-Te Lin
The power_init is not required on Exynos 5250 (snow) in bootblock stage. To get a cleaner and faster bootblock, we can remove it. Note, power_init internally calls max77686 and s3c24x0_i2c, so both files are also removed. Verified to boot on armv7/snow. Change-Id: I5b15dfe5ac7bf4650565fea0afefc94a228ece29 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2317 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07armv7/snow: Remove redundant I2C initialization calls in bootblock.Hung-Te Lin
The I2C initialization (on component MAX77688) is already done in power_init, so we should not need an explicit call inside bootblock. Verified to boot on armv7/snow. Change-Id: I68c248a8b5fee4ab838b2fb708649e112559cc41 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2316 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07armv7: Clean up arm/snow bootblock build process.Hung-Te Lin
Remove duplicated / testing code and share more driver for bootblock, romstage and ramstage. The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is executed before RAM is initialized. Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2282 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07cbfs: Fix CBFS max size calculation.Hung-Te Lin
For x86, the old CBFS search behavior was to bypass bootblock and we should keep that. This will speed up searching if a file does not exist in CBFS. For arm, the size in header is correct now so we can remove the hack by CONFIG_ROM_SIZE. Change-Id: I541961bc4dd083a583f8a80b69e293694fb055ef Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2292 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-06armv7: Clean up: remove deprecated SPL.Hung-Te Lin
"SPL" from U-Boot is deprecated by bootblock in coreboot/arm, so we don't need it anymore. Change-Id: Id16877075d0b870839a10160073ad70777a2af0a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2297 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-06snow: remove dead code from bootblockDavid Hendricks
This attempts to clean out some dead code which was copy + pasted into Snow's bootblock.c file, along with some unnecessary headers. Change-Id: If9f157a52395a047c249a2a6385e0e8ddf310e59 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2291 Tested-by: build bot (Jenkins)
2013-02-06armv7: Clean up: replace hang() by hlt().Hung-Te Lin
hang() is the legacy function from U-boot and should be replaced by hlt() in coreboot. Change-Id: I0f390b1b6f9ff71487ea36cf16c462724b66d8ca Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2298 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06AMD Fam14 - Fix warningsMartin Roth
Added casts and a couple of #ifdefs to fix the warnings in the vendorcode/amd/agesa/f14 codebase. This will allow us to re-enable 'all warnings being treated as errors' in boards such as Persimmon that are using this code. That change will follow. These are the warnings that are fixed by this patch: src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToTempRamAtPost': src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:219:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToMainRamAtPost': src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:372:30: warning: comparison between pointer and integer [enabled by default] src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:381:33: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c: In function 'ApUtilSetupIdtForHlt': src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:863:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:872:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c: In function 'LoadMicrocode': src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c:211:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapManagerInit': src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:167:52: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:183:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress': src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:669:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:676:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:683:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:684:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:687:23: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:691:21: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:696:3: warning: return makes pointer from integer without a cast [enabled by default] In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0, from src/northbridge/amd/agesa/family14/northbridge.c:36: src/vendorcode/amd/agesa/f14/AGESA.h:1132:0: warning: "TOP_MEM" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0, from src/northbridge/amd/agesa/family14/northbridge.c:36: src/vendorcode/amd/agesa/f14/AGESA.h:1133:0: warning: "TOP_MEM2" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition Verified on persimmon. Change-Id: I1671b191c72dfc1d63ada41126ae3418bc8f86ae Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2293 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Steven Sherk <steven.sherk@se-eng.com>
2013-02-06bootblock: Reduce register loadPatrick Georgi
The common part of the bootblock resets the nvram data if it's found to be invalid. Since that code is compiled with romcc in i386 mode, there's a shortage on registers. Try to reduce the strain by doing things smarter: cmos_write_inner is the same as cmos_write, just that it doesn't check if the RTC is disabled. Since we just disabled it before, we can assume that it is so. Change-Id: Ic85eb2a5df949d1c1aff654bc1b40d6f2ff71756 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2296 Tested-by: build bot (Jenkins) Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-02-06armv7: Prevent CBFS data overlapping bootblock.Hung-Te Lin
For arm/snow, current bootblock is larger than previously assigned CBFS offset and will fail to boot. To prevent this happening again in future, cbfstool now checks if CBFS will overlap bootblock. A sample error message: E: Bootblock (0x0+0x71d4) overlap CBFS data (0x5000) E: Failed to create build/coreboot.pre1.tmp. arm/snow offset is also enlarged and moved to Kconfig variable. Change-Id: I4556aef27ff716556040312ae8ccb78078abc82d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2295 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06cbfs: Revise debug messages.Hung-Te Lin
Some variables are using incorrect data type in debug messages. Also corrects a typo (extra 'x'). Change-Id: Ia3014ea018f8c1e4733c54a7d9ee196d0437cfbb Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2294 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06replace uchar and uint with standard types in generic i2c headerDavid Hendricks
Change-Id: Ie72985bb5291bcef2e837a2f4f2ec929a0c086ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-06exynos/snow: Move core/memory clock-related and board ID codeDavid Hendricks
This patch moves ARM core and DRAM timing functions around to simplify the dependencies for system_clock_init(). The original code was architected such that the system_clock_init() function called other functions to obtain core and memory timings. Due to the way memory timing information must be obtained on Snow, which entails decoding platform-specific board straps, the bottom- up approach resulted in having the low-level clock init code implicitly depend on board and vendor-specific info: main() ->system_clock_init() -> get_arm_ratios() -> CPU-specific code -> clock_get_mem_timings() -> board_get_revision() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table ...then proceed to init clocks ...come back to main() The new approach gathers all board and vendor-specific info in a more appropriate location and passes it into system_clock_init(): main() -> get_arm_ratios() -> CPU-specific code -> get_mem_timings() -> board_get_config() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table -> system_clock_init() ...back to main() Change-Id: Ie237ebff76fc2d8a4d2f4577a226ac3909e4d4e8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2271 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-06snow: use bootblock build class for I2C codeDavid Hendricks
This gets rid of a bunch of duplicate I2C code in the bootblock. Change-Id: I51f625a0f738cca4ed2453fbcb78092e4110bc7e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2289 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06snow: use bootblock build class for GPIODavid Hendricks
This gets rid of a bunch of copy + pasted GPIO code. Change-Id: I548b2b5d63642a9da185eb7b34f80cbebf9b124f Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2288 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06exynos5250: Move the ID section againDavid Hendricks
Move the ID section again due to bootblock bloat. So long as it's within the first 32K of our address space, we're good. TODO: 1. Place ID section near start of ROM to avoid this issue. 2. Reduce bootblock bloat. 3. Make bootblock debugging a Kconfig option. Change-Id: I3f0764a3345a8cbbafcc15e4d06c38cd6327758c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-05Don't add another Kconfig special case for TianoStefan Reinauer
We don't need a special Kconfig variable anymore because the FV _is_ the payload, unlike with the old tianocoreboot implementation. Change-Id: I349b5a95783e4146e3ab7f926871188cf2021935 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2284 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-02-05snow: use bootblock build class for UART codeDavid Hendricks
This gets rid of a bunch of copy + pasted code from Exynos UART files. Change-Id: I9fbb6d79a40a338c9fdecd495544ff207909fd37 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2286 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-02-05exynos: de-duplicate UART header contentDavid Hendricks
Some header content got duplicated during the initial porting effort. This moves generic UART header stuff to exynos5-common and leaves exynos5250 #defines in the AP-specific UART header. Change-Id: Ifb6289d7b9dc26c76ae4dfcf511590b3885715a3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2285 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05cbfstool: support parsing UEFI firmware volumesStefan Reinauer
This removes the hack implemented in http://review.coreboot.org/#/c/2280 (and should make using 64bit Tiano easier, but that's not yet supported) Change-Id: Ie30129c4102dfbd41584177f39057b31f5a937fd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05cbfstool: Use cbfs_image API for "create" command.Hung-Te Lin
Usage Changes: To support platforms with different memory layout, "create" takes two extra optional parameters: "-b": base address (or offset) for bootblock. When omitted, put bootblock in end of ROM (x86 style). "-H": header offset. When omitted, put header right before bootblock, and update a top-aligned virtual address reference in end of ROM. Example: (can be found in ARM MAkefile): cbfstool coreboot.rom create -m armv7 -s 4096K -B bootblock.bin \ -a 64 -b 0x0000 -H 0x2040 -o 0x5000 Verified to boot on ARM (Snow) and X86 (QEMU). Change-Id: Ida2a9e32f9a459787b577db5e6581550d9d7017b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2214 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05cbfstool: Use cbfs_image API for "locate" command.Hung-Te Lin
To support platforms without top-aligned address mapping like ARM, "locate" command now outputs platform independent ROM offset by default. To retrieve x86 style top-aligned virtual address, add "-T". To test: cbfstool coreboot.rom locate -f stage -n stage -a 0x100000 -T # Example output: 0xffffdc10 Change-Id: I474703c4197b36524b75407a91faab1194edc64d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2213 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04Add MMCONF resource to AMD fam15 PCI_DOMAINSteven Sherk
This is a port of the following: commit d5c998be99709c92f200b3b08aed2ca3fee2d519 The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9 Signed-off-by: Marc Jones <marc.jones@se-eng.com> URL - http://review.coreboot.org/#/c/2167/ Change-Id: I6e585d5cf0d46bd58337a6801fb0690ab2dd000c Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Hook up corebootPkg as Tianocore payloadPatrick Georgi
This unplugs Stefan's PIANO project. Change Tianocore payload configuration to use corebootPkg. As argument you have to give it the COREBOOT.FD generated by the Tianocore build system. It automatically determines base address and entry point. Compression setting is honored (ie. no compression if you don't want), but corebootPkg currently assumes that coreboot is doing it. Loading a 6MB payload into CBFS without compression will fail more often than not. Change-Id: If9c64c9adb4a846a677c8af40f149ce697059ee6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2280 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04AGESA boards: Fix grammar in description of `OemCustomizeInitEarly`Paul Menzel
The following command was used to correct the grammatical mistake. $ git grep -l 'This is the stub function will call' | xargs sed -i s,This is the stub function will call,This stub function will call, '{}' sed: -e Ausdruck #1, Zeichen 6: Nicht beendeter `s'-Befehl As this file seems to have been copied around a lot, it originally seems to have come with the following commit for AMD Persimmon and AMD Inagua. commit 69da1b676cd3f126b27a6fd3c23c557ac1a03961 Author: Frank Vibrans <frank.vibrans@amd.com> Date: Mon Feb 14 19:04:45 2011 +0000 Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. Change-Id: I2e6630a5172738b01e6def7062284f167e5508b1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2268 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04smbios: show CONFIG_LOCALVERSION in DMI bios_versionChristian Gmeiner
If somebody makes use of CONFIG_LOCALVERSION show this user provided config string for DMI bios_version. As requested I have attached example output. CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y ... root@OT:~# cat /sys/class/dmi/id/bios_version 4.0-3360-g5be6673-dirty CONFIG_LOCALVERSION="V1.01.02 Beta" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y ... root@OT:~# cat /sys/class/dmi/id/bios_version V1.01.02 Beta Change-Id: I5640b72b56887ddf85113efa9ff23df9d4c7eb86 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/2279 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 12: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: I3368a831770df1b8449eb0c97ae4bb24f6678efd Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2250 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 15tn: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 10: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Idf479980e427bbf0399bdbc15045d80f402f6dbe Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2249 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Family 15: Update for string portabilityMike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Ie71fec39df5e7703d35d6505dc7d5b55179e2c7e Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2234 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04Add MMCONF resource to AMD fam15tn PCI_DOMAINSteven Sherk
In the process of verifying change it was discovered the MMCONF default base address 0xA0000000 was set below mem_top 0xE0000000 and bus number 256 wasn't a relistic number. The Kconfig defaults were changed to mirror fam15 defaults base address 0xF8000000 and bus number 64. Verified changes with boot to OS. This is a port of the following: commit d5c998be99709c92f200b3b08aed2ca3fee2d519 The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9 Signed-off-by: Marc Jones <marc.jones@se-eng.com URL - http://review.coreboot.org/#/c/2167/ Change-Id: I47660061538f8889f528b9b880a82645074886a7 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2260 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04ASRock 939A785GMH: Align comments of DSDT’s `IndexField`Paul Menzel
Remove superfluous spaces and use tabulators. Change-Id: Ic8b32b10c4e287a058a395e54214b9923ee48bdd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2276 Tested-by: build bot (Jenkins) Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04ASRock 939A785GMH: Align comments in DSDT header with tabsPaul Menzel
Change-Id: Ie64c231188310c4248ad0aaf9cdfcea12666bf2f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2275 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04Use tabs instead of spaces to align comments in DSTD headerPaul Menzel
AOpen DXPL Plus-U and Intel XE7501devkit use »COREBOOT« as OEM Table ID. Unify the DSDT by aligning the comments in the DSDT header with tabs in accordance with the coding style [1]. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I78e6aa8d0318b519b1df5e2178d387dc58e48323 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2278 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04Intel based boards: Use tab instead of spaces to align comment in DSDTPaul Menzel
Mainboards using `COREBOOT` as their OEM Table ID in their DSDT header were copied from the same source and therefore had spaces instead of a tab to align that comment for that header field. These are mostly Intel based boards. Fix that in accordance with the coding style [1]. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I299b955930dbd50b9717e8ff141ce8f3fd534e5f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2277 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04exynos5250: make lowlevel_init_c.c benignDavid Hendricks
This file has mostly (but not entirely) been replaced by coreboot stage files. We'll keep it around for a bit longer as a reference, but in the meantime we'll stop compiling it as to avoid comptilation issues as we change other parts of the code. Change-Id: I669fb1e5a1517f35979590957d581bd33df53d29 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2269 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04exynos/snow: get rid of board-specific arbitration codeDavid Hendricks
Snow's AP, EC, PMU, and smarty battery share a bus. Both the AP and EC can act as a master, so to avoid conflicts an arbitration mechanism consisting of two GPIOs is used. By default, the AP "owns" the bus unless it is off (in which case the EC doesn't monitor the arbitration pins). This means the boot firmware does not need to worry about these lines. The payload may if it needs to communicate with the EC, though. In any case, board-specific bus arbitration logic does not belong in a low-level driver that is supposed to be generic for an entire CPU family. If the payload needs to talk to the EC, we'll deal with it there. Change-Id: I0774d4592af2b21b6ad668441532c5ceab988404 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04exynos/snow: partial clean-up of snow bootblock using build classDavid Hendricks
This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04exynos/s5p: Add helper function for reading a single MVL3 GPIODavid Hendricks
This adds a helper function to read only a single GPIO which uses 3-state logic. Examples of this typically include board straps which are used to provide mainboard-specific information at the hardware- level, such as board revision or configuration options. This is part of a larger clean-up effort for Snow. We may want to genericise this for other CPUs in the future. Change-Id: Ic44f5e589cda89b419a07eca246847e9ce7dcd8d Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2266 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04add gpio.h for generic GPIO-related definitionsDavid Hendricks
This adds /src/include/gpio.h which currently contains generic GPIO enums for type (in/out/alt) and 3-state logic. The header was originally written for another FOSS project (code.google.com/p/mosys) and thus the BSD license. Change-Id: Id1dff69169e8b1ec372107737d356b0fa0d80498 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2265 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-03exynos5250: remove CPU check from samsung_get_base_* macroDavid Hendricks
The cpu_is_exynos5() macro seems broken at the moment, so skip it. The macro is superfluous and will probably be replaced eventually, but at least this will un-break usage sites. Change-Id: Ibd360cbfa18047ad8a3488d4f24c3fc4d7415eba Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2264 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-03armv7: Add 'bootblock' build class.Hung-Te Lin
For ARM platform, the bootblock may need more C source files to initialize UART / SPI for loading romstage. To preventing making complex and implicit dependency by using #include inside bootblock.c, we should add a new build class "bootblock". Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled for boot block. For x86, the bootblock is limited to fewer assembly files so it's not using this class. (Some files shared by x86 and arm in top level or lib are also changed but nothing should be changed in x86 build process.) Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2252 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-01AMD/Persimmon: LVDS assignment was made to wrong DPxDave Frodin
The LVDS is on DP0, not DP1. Change-Id: I724764d0f013e7a10d974a8716e075139982ded2 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2259 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2013-02-01armv7: Fix entry point in ram stage.Hung-Te Lin
Eliminate the warning message: ld: warning: cannot find entry symbol _start; defaulting to 040000000 The "_start" from c_start.S is deprecated so we need to define entry point again in link description file. Change-Id: I174428faa2e7f08cd91fe96a53e6efea9dc3634e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2258 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01clean-up for arch/armv7/Makefile.incDavid Hendricks
This removes a few lines which are obsolete or unneeded. We may want to do something with SMP eventually (can we use it for decompression?) but for now we'll assume non-bootstrap cores are idle until the OS does something with them. Change-Id: Iff6b196e008e803bcfd00e5de07cf471bd2357ea Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2257 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-01snow: make romstage init DRAM controller and call ramstageRonald G. Minnich
This is a first cut at a romstage. It sets up memory, although that needs some work; and finds and loads a ramstage. Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2245 Tested-by: build bot (Jenkins)
2013-02-01exynos5250: hard-code array index for memory timingsDavid Hendricks
Discovering memory timings is a bit complicated due to the need to obtain and decode board config. To make things worse, the imported code makes a mess of dependencies. Hard-code the memory timings for now to get us further along (the instability won't really matter until we're loading depthcharge anyway). Change-Id: I1f341ad597db0c31ed4ae6bc703fc22b6596a803 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2256 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-01exynos5250: #define the dram controller interleaving sizeDavid Hendricks
Change-Id: Iab184aa85be68b6ca5107d278d2fe821e5b2e611 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2255 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-01lib: Prevent unaligned memory access and fix endianess in LZMA decode library.Hung-Te Lin
LZMA decode library used to retrieve output size by: outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); 'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address like src+5, and using that as integer pointer may fail on platforms like ARM. Also this will fail on systems using big-endian (outSize was encoded in little-endian). To fix this, reconstruct outSize in little-endian way. Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2246 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-01Fam15tn: Move SPD read from mainboards into wrapperMartin Roth
Continuing with the mainboard cleanup for F15tn, move the functions to read the SPD from the mainboards for Thatcher and Parmer into the wrapper for the northbridge/amd/agesa/family15tn. Move the SPD address customization for the mainboard into the devicetree.cb file. Unrelated side note - Porting.h has an un-closed #pragma pack(1) that can cause confusing side-effects. AGESA's structures all use this, but coreboot's don't. Be sure to include the coreboot .h files BEFORE Porting.h is included, not after. This fix has been tested. Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2190 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
2013-02-01armv7: unify stage hand-off routinesDavid Hendricks
This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow's ramstage files are also updated to avoid build breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2254 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-31Improve how our printk calls do_div by using constants.Ronald G. Minnich
The do_div code has a nice optimization in it when it is called with constants. The current highly generalized use of it defeats those optimizations and causes trouble on ARM, resulting in a complex and buggy code path. Since we only need to print in bases 8, 10, and 16, do a minor restructuring of the code so that we call do_div with constants. If you need base 2, print in base 16 and do it in your head. :-) This fixes an ongoing problem with ARM, will not harm X86, and will help PPC should we ever want to support it again. Plus, I don't have to ever try to understand the div64 assembly and where it's going wrong :-) Change-Id: I6a480011916eb0834e05c5bb10909d83330fe797 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2235 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-30armv7: don't hang on divide by zeroRonald G. Minnich
People make mistakes. Hanging the box is not a good reason to kill the firmware, esp. since this is probably happening in a printk. The only issue with the recursive call to printk is that we may deadlock if we have locked something. But we can at least try. Hanging is certainly not what we want ... Change-Id: Ib3bc87bc395ae89e115cf6d042f4167856422ca1 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2233 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-01-30Exynos5250: Get DDR3 working by changing what is compiled and add a functionRonald G. Minnich
This is a minor set of changes to get DDR3 going. Move compilation of DDR3 startup to the romstage. Fix a prototype that was missing a void. Remove a function that is overly flexible, and even though it is overly flexible only actually can handle one type of RAM. Mainboards only support one type of DRAM, so create a function to explicitly initialize the type of DDR we have -- DDR3. With these changes, and the previous changes, google snow is ready to run the ramstage. Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-30armv7: Add SPI driver for Exynos.Hung-Te Lin
The SPI flash driver for Exynos chipset. Verified to boot on snow/armv7. Change-Id: I7eef67a9c57f825d09f13ea44c2b59b54345fa7b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2229 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
Summary: Isolate CBFS underlying I/O to board/arch-specific implementations as "media stream", to allow loading and booting romstage on non-x86. CBFS functions now all take a new "media source" parameter; use CBFS_DEFAULT_MEDIA if you simply want to load from main firmware. API Changes: cbfs_find => cbfs_get_file. cbfs_find_file => cbfs_get_file_content. cbfs_get_file => cbfs_get_file_content with correct type. CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM, the ROM may come from USB, UART, or SPI -- any serial devices and not available for memory mapping. To support these devices (and allowing CBFS to read from multiple source at the same time), CBFS operations are now virtual-ized into "cbfs_media". To simplify porting existing code, every media source must support both "reading into pre-allocated memory (read)" and "read and return an allocated buffer (map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*" provides simple memory mapping simulation. Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA is defined for CBFS functions to automatically initialize a per-board default media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS function names relying on memory mapped backend (ex, "cbfs_find" => actually loads files). Now we only have two getters: struct cbfs_file *entry = cbfs_get_file(media, name); void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type); Test results: - Verified to work on x86/qemu. - Compiles on ARM, and follow up commit will provide working SPI driver. Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30Rename family15 pci northbridgeops functions.Steven Sherk
This is a port of the following commit 8a49ac7f808f76821e7d63070420cfd98f707c7c Rename fam14 pci northbridge ops functions. Clarify the northbridge ops function names. original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id7889bf02e2696220081251acdf695327267c796 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2225 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30Rename family15tn pci northbridgeops functions.Steven Sherk
This is a port of the following commit 8a49ac7f808f76821e7d63070420cfd98f707c7c Rename fam14 pci northbridge ops functions. Clarify the northbridge ops function names. original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icda3ec58219baa177af3b1dce729c6ad1f744be8 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/2226 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30Family 14: Update for string portability.Mike Loptien
Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: I6327c9769c2544bbc56155a2f89afd767487faf6 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2227 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-30Project PIANO aka tianocorebootStefan Reinauer
This is a Tiano Core loader payload based on libpayload. It will load a Tiano Core DXE core from an UEFI firmware volume stored in CBFS. Currently Tiano Core dies because it does not find all the UEFI services it needs: coreboot-4.0-3316-gc5c9ff8-dirty Mon Jan 28 15:37:12 PST 2013 starting... [..] Tiano Core Loader v1.0 Copyright (C) 2013 Google Inc. All rights reserved. Memory Map (5 entries): 1. 0000000000000000 - 0000000000000fff [10] 2. 0000000000001000 - 000000000009ffff [01] 3. 00000000000c0000 - 0000000003ebffff [01] 4. 0000000003ec0000 - 0000000003ffffff [10] 5. 00000000ff800000 - 00000000ffffffff [02] DXE code: 03e80000 DXE stack: 03e60000 HOB list: 03d5c000 Found UEFI firmware volume. GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3 length: 0x0000000000260000 Found DXE core at 0xffc14e0c Section 0: .text size=000158a0 rva=00000240 in file=000158a0/00000240 flags=60000020 Section 1: .data size=00006820 rva=00015ae0 in file=00006820/00015ae0 flags=c0000040 Section 2: .reloc size=000010a0 rva=0001c300 in file=000010a0/0001c300 flags=42000040 Jumping to DXE core at 0x3e80000 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 3E96708 HOBLIST address in DXE = 0x3E56010 Memory Allocation 0x00000003 0x3E80000 - 0x3EBFFFF FV Hob 0xFFC14D78 - 0xFFE74D77 InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 3E95EA0 InstallProtocolInterface: EE4E5898-3914-4259-9D6E-DC7BD79403CF 3E9630C Security Arch Protocol not present!! CPU Arch Protocol not present!! Metronome Arch Protocol not present!! Timer Arch Protocol not present!! Bds Arch Protocol not present!! Watchdog Timer Arch Protocol not present!! Runtime Arch Protocol not present!! Variable Arch Protocol not present!! Variable Write Arch Protocol not present!! Capsule Arch Protocol not present!! Monotonic Counter Arch Protocol not present!! Reset Arch Protocol not present!! Real Time Clock Arch Protocol not present!! ASSERT_EFI_ERROR (Status = Not Found) ASSERT /home/reinauer/svn/Tiano/edk2/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c(461): !EFI_ERROR (Status) Change-Id: I14068e9a28ff67ab1bf03105d56dab2e8be7b230 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2154 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30ASRock E350M1: Remove unused variable `reg8` from `romstage.c`Paul Menzel
[…] CC romstage.inc src/mainboard/asrock/e350m1/romstage.c: In function 'cache_as_ram_main': src/mainboard/asrock/e350m1/romstage.c:48:5: warning: unused variable 'reg8' [-Wunused-variable] This change was already done for AMD Persimmon in the following commit. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Change-Id: I8f1ae1a609b87b197583934f0556f66b64e6994d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2230 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-01-29Exynos5250: change all unsigned with no type to 'unsigned int'Ronald G. Minnich
At some point we did a lot of cleanup to replace bare 'unsigned' with 'unsigned int'. Do that work for this imported code as well. At some point, we may find we can shrink these 'int's to something smaller, thought I very much doubt it's worth the trouble. Change-Id: Ic3da491c0188c56c836f8b9c4c8f26a31b4b3573 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2223 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29Exynos5250: add debug prints to DDR3 startup code.Ronald G. Minnich
It can be handy to have debug prints as DRAM is started up, so that in the case of failure (does that ever happen?) you've got some idea where it failed. This patch adds some DEBUG_SPEW prints to the DDR3 code. I am doing this as its own CL because we may find we want to revert it. That's unlikely but it is not impossible if we skew the timing in some way. This code works for some trivial DRAM tests. Change-Id: I57e8d2a2d8df6b8ec8cd0d414681fc513e9999e3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2222 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29Exynos5250: make vendor enums in the timing array more debuggable.Ronald G. Minnich
The timing array is crucial to proper operation of DRAM. Getting a valid pointer to it is hence very important. Unfortunately, the constants chosen for the vendor were '1', and '2', (this in a 32-bit word) which in a debug print makes it almost impossible to tell if you've got a misaligned pointer. Note: coreboot people did not choose them :-) So, give them values which are extremely unlikely to occur elsewhere in the array (or in memory, for that matter). Given the frequency with which this check occurs, i.e. once, I would much prefer strings but I expect I'd get shouted down on that one. Constants in this case are an almost useless optimization but we'll go with them for now. Note no space is saved by not using strings: there's an entire function somewhere devoted to mapping the enum to a string! Debug prints of pointers to structs in this array are now far more useful than they were. See snarky comment in the code (left there to make sure nobody gets tempted to get fancy again). Comment now less snarky. This is tested on google snow to the point that the DRAM works. Change-Id: I30bc44719f321f791fd82ded60e29393399d9e3d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2221 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
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