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2015-03-27rk3288: Add missing #include and use uniform typesDavid Hendricks
This updates timer.h to #include the header necessary for u32, and to change the one instance of uint32_t to u32 to be uniform. BUG=none BRANCH=none TEST=compiled Change-Id: I4d67045206fd94985774b8d46a307bbb2e337f30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ff2629fdf3c69c203fa61ec894bb4895990cb5e Original-Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220612 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27pinky: Add mainboard-specific bootblock initDavid Hendricks
This adds a mainboard-specific bootblock function that will be used to set up some board-specific parameters which are currently set up in the SoC bootblock function. BUG=none BRANCH=none TEST=built and booted on Pinky Change-Id: I86c90f7ade824fb9d6b71ca3349d1ce9eb4772fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 03e0bb2eaca7a54c3df95b21d856ef4114d3c833 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibee7076ebd6080f04b0697067e85ce8b6b2230e4 Original-Reviewed-on: https://chromium-review.googlesource.com/220399 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9050 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27soc/imgtec/pistachio: Add IMGTEC SPI controller driverIonela Voinescu
The Serial Peripheral Flash Interface (SPFI) block allows communication with various devices over the SPI bus. It uses a configurable transaction interface and it clocks the bus according to the configured command, address, gap (aka dummy) and data lengths. This controller requires the SPI_ATOMIC_SEQUENCING flag set (write and read done in the same transaction) as it cannot directly control CS and will assert/de-assert CS at the beginning/end of a transaction itself. Note that the size of any transfer cannot be greater than 64KB - 1, as this is configured in a 16-bit field. The SOC has 2 SPFI interfaces each of them providing 5 slave select lines. SPFI 0 supports single and dual modes, SPFI 1 supports single, dual and quad modes. For SPFI interface 0: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi0clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set - CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim0_d0_txd MFIO_MIPS_10 0 spim0_d1_rxd MFIO_MIPS_9 0 spim0_mclk MFIO_MIPS_8 0 spim0_cs0 MFIO_MIPS_2 1 spim0_cs1 MFIO_MIPS_1 1 spim0_cs2 MFIO_MIPS_55 1 MFIO_MIPS_28 1 spim0_cs3 MFIO_MIPS_56 1 MFIO_MIPS_29 1 spim0_cs4 MFIO_MIPS_57 1 MFIO_MIMPS_30 1 For SPFI interface 1: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi1clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set - CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim1_d0_txd MFIO_MIPS_5 0 spim1_d1_rxd MFIO_MIPS_4 0 spim1_mclk MFIO_MIPS_3 0 spim1_d2 MFIO_MIPS_6 0 spim1_d3 MFIO_MIPS_7 0 spim1_cs0 MFIO_MIPS_0 0 spim1_cs1 MFIO_MIPS_1 0 MFIO_MIPS_58 1 spim1_cs2 MFIO_MIPS_2 0 MFIO_MIPS_55 2 MFIO_MIPS_31 1 spim1_cs3 MFIO_MIPS_56 2 spim1_cs4 MFIO_MIPS_57 2 BUG=chrome-os-partner:31438, chrome-os-partner:32441 TEST=Tested as bare-metal driver on Pistachio FPGA Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91 Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217320 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9049 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27urara: use proper SOC nameVadim Bendebury
Danube has become Pistachio, let's rename all instances where this SOC is mentioned. BUG=none TEST=board urara still builds Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78 Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220401 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/9048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27urara: introduce board skeletonVadim Bendebury
Not much is happening yet, when the board is enabled (in the next patch), all three components build successfully, the map files show them placed where expected and the bopotblock is wrappeed in a BIMG header. BUG=chrome-os-partner:31438 TEST=when config is enabled, emerge-urara coreboot succeeds. more extensive testing to come later Change-Id: Ib7396189f4bee0fdd6a8ce5c9ab1277806cb5dcc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1ca9efe59a7fcb99412410d509a7f9a91b6ef3ec Original-Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214600 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9047 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove soc_secondary_cpu_init()Aaron Durbin
The original purpose of soc_secondary_cpu_init() was to provide a way for the SoC to run code on the secondary processors as they come up. Now that devicetree based bringup is supported there's no need to have this functionality. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP into linux. Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216927 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: support arm64 SMP bringupAaron Durbin
Use the formal devicetree way for bringing up each of the cpus. This includes providing a cpu_driver as well as calling arch_initialize_cpus() with the proper operations to start the cores. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP on ryu. Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216926 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9043 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27armv4: Build in SMP settings with non-SMP armv4 CPUsPatrick Georgi
There are some ARMv8/ARMv4 SoC where the ARMv8 part needs to be SMP aware but the ARMv4 part does not. Until we need real SMP on ARMv4, work around that situation with stub defines. Change-Id: Iec5b4302b19c17fe2b3f677b84a8edf4b4902946 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add devicetree based CPU startupAaron Durbin
This adds SMP bring up support for arm64 cpus. It's reliant on DEVICE_PATH_CPU devices in the devicetree. Then for each enabled device it attempts to start then initialize each CPU. Additionally, there is a cpu_action construct which allows for running actions on an individual cpu. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted both cores on ryu into linux. Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216925 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: split cpu.h headerAaron Durbin
Add a cpu-internal.h for internal prototypes to the architecture specific code. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted. Change-Id: I12a379f86056a9a2007a7c036d65b5e08e558d0e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dcd488326f6496d80eb1fe1ff4414ebba1280e9 Original-Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9041 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add spinlock implementationAaron Durbin
Provide a simple spinlock implentation for arm64. A value of 0 is unlocked and a value of 1 is locked. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup on ryu. Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216923 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9040 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: move spinlock.h to proper placeAaron Durbin
The spinlock header file was not residing in the correct place. It needs to live under 'arch/smp'. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with SMP. spinlock.h found. Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0 Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216922 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9039 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add more barrier supportAaron Durbin
The load-acquire/store-release operations (including exclusive variants) form a basis for atomic operations. Also remove the dmb, dsb, and isb functions from lib_helpers as barrier.h already included these. Lastly, utilize barrier.h. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup using barriers. Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118 Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216921 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9038 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove printk() before console_init()Aaron Durbin
printk() shouldn't be called until the consoles have been initialized. This just so happened to work by luck. Once CONFIG_SMP is enabled that breaks because of spinlock usage in uncached memory. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with CONFIG_SMP and ramstage doesn't hang early. Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0 Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216920 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9037 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: remove printk() before console_init()Aaron Durbin
printk() shouldn't be called until the consoles have been initialized. This just so happened to work by luck. Once CONFIG_SMP is enabled that breaks because of spinlock usage in uncached memory. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with CONFIG_SMP and ramstage doesn't hang early. Change-Id: I4bf5d98e409840cf07a7759e9273d770f3bbf8bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ec672e52eda69f2b5abb747807a496bb973088f Original-Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216429 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9036 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: update cpu.c licenseAaron Durbin
The code should be GPL. Update accordingly. BUG=chrome-os-partner:31761 BRANCH=None TEST=None Change-Id: I051ceb3f12e9938819b513413aae43cbf51d9b86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdff53ebf4c1a1d86d68054c2d25dce45b69ff48 Original-Change-Id: I26a40a239afd851d351dbda0d716ef992b88b6c8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216428 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9035 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: add cpus to device treeAaron Durbin
Add all the CPUs to the device tree. BUG=chrome-os-partner:31761 BRANCH=None TEST=Brought up 2nd core on ryu in kernel. Change-Id: I4cc51f30897e3bd6c1b275a95d5da34ce7ae320e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 485de634a49d606dc6e7168f047eb9365e26415f Original-Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216426 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9034 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Fix clock apisFurquan Shaikh
Instead of directly using the clk_src_id based on enum for clock source, every device needs to have its own set of clk source ids defined. This prevents accidentally selecting a wrong clk source if the ids are different from host1x's. Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for handling the common clock sources based on id to get the proper frequency in software. [pg: integrated a later commit to fix the build] BUG=chrome-os-partner:31821 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5d40fb49b81e8838b2be071d32c466213215e0d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27d5d6a34d1c826c6095c18368efb78c228d4ca8 Original-Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216761 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Commit-Id: 13c30c50a9e8a7f3c48673a2f6c144ba546129b6 Original-Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217342 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9033 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add midr_el1 accessor functionAaron Durbin
Provide access to the MIDR_EL1 register to obtain the main id for determining CPU implementer and part/revision information. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and printed the output of this function on ryu. Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216423 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: remove call to soc_configure_i2c6pad()Aaron Durbin
This function is breaking display bring up in the kernel. While this functionality may be needed it's not until there is a necessity to beep and/or bring up the display in firmware. BUG=chrome-os-partner:31820 BRANCH=None TEST=Sean ran with this patch and the display indeed did come up. Change-Id: I5cf8a6c6e6941ee138991933215f96f5562382be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038bc1d53028409d0640c78fb62c7025ba12dcb9 Original-Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216421 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9031 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: Remove old/unused BCT cfg filesTom Warren
These are not needed/were never really used. SDRAM init will now be done in sdram.c, not the BootROM. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built rush_ryu AOK. Change-Id: Id046592415574badb97026224e1e525c174eece4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7 Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/215863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9030 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add LPDDR3 SDRAM init in coreboot.Tom Warren
Expanded sdram.c to add support for LPDDR3 init. This code can be used with matching BCT .inc files to have LPDDR3 SDRAM initialized by coreboot instead of the T132 BootROM. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built for rush and rush_ryu. Change-Id: I53801d9399dbf67fd86d0a2521174f0668567620 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 60e130c47c1894925a12f251af5b83a1fa144d57 Original-Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: fix power button polarityAaron Durbin
The power button signal is driven from the silego part. It's active high when the button is pressed. BUG=None BRANCH=None TEST=Booted with power button pressed. vboot saw the press and requested a shut down. Change-Id: Ifff1bd8d4340849e0c218812fd401b61c90c5743 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b6bd7c0de38e1078b85f1671493c6d2948d43149 Original-Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214847 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9028 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27rush: use names for gpiosAaron Durbin
Instead of calling out the gpio index and port numbers use real names. It's semantically clearer and there's only one place to adjust the hardware values. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted. Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215542 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9027 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: configure plld for display usageAaron Durbin
The kernel doesn't have the logic for bringing up the plld. Therefore, configure it in the firmware. The clock used is an interim value until the display controller sequencing is fully implemented. BUG=chrome-os-partner:31640 BRANCH=None TEST=Noted configured freq is close to requested. Also, no more plld errors observed from the kernel. Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9026 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: return actual plld frequencyAaron Durbin
Depending on the requested frequency the plld cannot necessarily obtain the exact clock. Therefore provide the closest configured frequency as a return value. This is equivalent to the t124 patch. BUG=chrome-os-partner:31640 BRANCH=None TEST=Built and noted plld actual value close to requested. Change-Id: I9aaba81222fb97d9fbbb4156af3a7476ba654c10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc928db8197b465220e53b4d0ba5896b3c06a863 Original-Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214843 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9025 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: No need for Kconfig variables for stacksFurquan Shaikh
With the latest changes to include stack storage within ramstage, we no longer need to define Kconfig options for ramstage/exception stacks in arm64. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel on ryu Change-Id: I7361d8f567453e775240151fd1180c49025141b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9aaa89115a67606fcb66eb354741043f7f2094bf Original-Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214607 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9023 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove _stack and _estack symbols in linker scriptAaron Durbin
These symbols should have been removed with the stack refactoring. I'm not sure how it was missed. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted into kernel with both cpus. Change-Id: Ia6c2103d7b5e2c9d74cdc5d1b5f42f8954812231 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d9432b5cf0cce3bfdbfd5371fb3280e3cc746a42 Original-Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215541 Reviewed-on: http://review.coreboot.org/9024 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: bring up secondary coreAaron Durbin
Instruct the SoC to bring up the 2nd core. BUG=chrome-os-partner:31545 BRANCH=None TEST=Brought up 2nd core in Linux. Change-Id: I4b31ea5f1466c43abce273b2bfb6a4d06b7faa63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 74c62e62a6790de65e303123abee2be1dfffbee3 Original-Change-Id: I5f5febc4719951188106041f73625231eafe1b08 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214778 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9022 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add spin table supportAaron Durbin
Until PSCI is functional the other core still needs to be brought up in the kernel. The kernel boots these cpus with the spin table which is just an address in memory to monitor a jump location. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up secondary core in linux. Change-Id: Iaa69110f6a647d8fd4149119d97db4fc45d7da00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01ca36685852bc5dd85fd4015c8a1e600e23e7ca Original-Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214777 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add option to bring up and init secondary cpuAaron Durbin
Optionally bring up secondary cpu according to devicetree. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and enabled bringing up second core on ryu. Change-Id: I5ede8b2f1b30a6170520cc11c18e263793cea301 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7da2dcce9be653a3c551c33bbefb3810a6949e9 Original-Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214776 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9020 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: provide API for coordinating secondary CPU bringupAaron Durbin
Provides a minimal API for coordinating with the SoC for bringing up the secondary CPUs. There's no eventloop or dispatcher currently nor does it do anything proper when one of the secondary CPUs are brought up. Those decisions are deferred to the SoC. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up 2nd cpu using this API. Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376 Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214775 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: support GIC secondary cpu supportAaron Durbin
For the secondary CPUs the set of banked registers needs to be initialized. In the boot CPU path all both the CPU's banked registers and the global register set is initialized. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up 2nd cpu in kernel. Change-Id: I3a7bc708f726c4435afca817a251790f536844d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 813b0a8b3faacf2342164d385e5837ebede29b18 Original-Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214774 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9018 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add exception_hwinit()Aaron Durbin
exception_hwinit() provides a path for just setting the hardware state. This allows for other CPUs but the boot CPU for setting up the appropriate vector table. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted to the kernel. Change-Id: Ifd44ab697bce5cd351f05069519785dc80e2b866 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76a1c9cb3df930b28469608ecb5c35be7ccdadd1 Original-Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: make mmu_enable() use previous ttb from mmu_init()Aaron Durbin
No need to pass in the same value for the ttb after just calling mmu_init(). All current users are setting this once and forgetting it. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted on ryu. Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8 Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214772 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add indirection to C entry pointAaron Durbin
To allow setting the entry point for the secondary CPUs provide a pointer, c_entry, which contains the location to branch to after setting up the stack. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted to the kernel on ryu. Change-Id: I03e54b081aa5ff70b90fbd7f1b243fdb4f42c5a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f692c5814ea5c7ff4895576e1db8361ff3b7d9fb Original-Change-Id: Ic2f6c79cde708b24c379345aed1e2cc0760ccad8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214771 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9015 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: move seeding stack to CAaron Durbin
Move the stack seeding out of assembly and into C so the code in stage_entry.S can more easily be used. The seeding of the stack doesn't touch at least 256 bytes to account for current usage at time fo the call. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted into kernel on ryu. Change-Id: Ib9659ec4265652461bde746140567f21533cc265 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f478cfe175aa674cdfdbbd890663eeaad9d82b1f Original-Change-Id: I44004220a02b1ff06d27a0555eb4e96d9e213544 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214770 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9014 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: include stack storage within ramstageAaron Durbin
Instead of defining the stacks by Kconfig options include the stack sizes for all the CPUs including each of their exception stacks. This allows for providing each CPU on startup a stack to work with. Note: this currently inherits CONFIG_STACK_SIZE from x86 because of the Kconfig mess of options not being guarded. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted into the kernel on ryu. Change-Id: Ie5fa1a8b78ed808a14efeb1717b98d6b0dd85eef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6524993f016aac2ac8cd9dba9fbdd9a59260a2b6 Original-Change-Id: Ica09dc256e6ce1dd032433d071894af5f445acdb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214669 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9013 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: refactor stage entryAaron Durbin
Provide a common entry point arm64 cores coming out of reset. Also, take into account CONFIG_ARM64_CPUS_START_IN_ELx to set the correct SCTLR_ELx register. The SCR_EL3 initialization was removed as that can be done in policy code in C later. Part of this refactor allows for greater code reuse for the secure monitor. BUG=chrome-os-partner:31545 BRANCH=None TEST=built and booted to linux on ryu Change-Id: I429f8fd0cdae78318ac171722fa1377924665401 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f92a5a01f07bc370735d75d695aedd8e2ab25608 Original-Change-Id: If16b3f979923ec8add59854db6bad4aaed35e3aa Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214668 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9012 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: select EL3 cpu start up stateAaron Durbin
The armv8 cores in tegra132 start in EL3. Indicate as such. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and noted Kconfig selection. Change-Id: I80f323a7d14c5376c8233c42dcc28f64ef07c9a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8af81929a82e3b686026b2ea648145e5fee98970 Original-Change-Id: I83370a03cfc0f04058ae2b6d87b09b96642df97d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214667 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9011 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add config options for exception level startupAaron Durbin
Depending on the armv8 implementation the cpus could start in EL1, EL2, or EL3. Therefore allow the SoC to select the appropriate mode. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built. Change-Id: I8787fd1bc4e14f03d829e6a5e5af915e29314770 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bb6b092a43e34fbc64d941bb62f19a6b8ac2c5de Original-Change-Id: Id063681ef7691097e528c105fffac5d467585e4e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214666 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9010 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: implement cpu_info() correctlyAaron Durbin
There are 2 things wrong with the current implementation: 1. the stack isn't guaranteed to be aligned to CONFIG_STACK_SIZE. 2. the stack isn't necessarily CONFIG_STACK_SIZE bytes. Utilize the smp_processor_id() function to obtain the correct cpu_info structure to obtain the correct index. BUG=chrome-os-partner:31545 BRANC=None TEST=Built and booted. Change-Id: I43d4a2baa26e48147bc0dbdb3e9e13ad023f0690 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2c32b1a46ac8dc1364ed03c195322c0bf28dd7f Original-Change-Id: I2825118e2313dbbf13712a4afdfa05a2e38ee3a4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214665 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9009 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: implement smp_processor_id()Aaron Durbin
Implement smp_processor_id() for the arm64 cores. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built. Change-Id: Id2fca068f92cdc816b02b5e7ce1229517787684a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c68329631ce0fc3cebef1c2422aa44ac192d Original-Change-Id: I7a1cd2f94ba4ae1854450cc60ef8a62f2457aabb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214664 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9008 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add smp_processor_id() declarationAaron Durbin
In order to accomodate MP on arm64 one needs to be able to determine the current logical processor id. Because it depends on the SoC implementation the SoC needs to provide this implementation. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built. Change-Id: I2f09df9bf7d4f829d8f45471bf7281a4ddba2fc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6033e73d70c3b8296b36ff36b4b848b176917e12 Original-Change-Id: I9511b54b5a1ab340b0f1309b0d9976be68b50903 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214663 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: increase MAX_CPUS to 2Aaron Durbin
There are 2 cores visible to the OS and both need to be brought up. Therefore, provide the proper number of cores. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and noted CONFIG_MAX_CPUS=2. Change-Id: I8a99891506af0fb3aa0284475c3c4be8bb69268b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: efa6c0343521dd98b86eacc94737f3497b721f95 Original-Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214661 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: clean up ramstage.ldAaron Durbin
This just removes some unneeded symbols and comments. Additionally, moved most of the absolute symbols into the individual sections. Also, aligned data sections to 64 bytes (typical cache line size). BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted through coreboot normally on ryu. Change-Id: I8ceed5a48078f70911122d304f2953795af0b421 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0524d4769613dc4a762e0a8e1bc1d2549d2df743 Original-Change-Id: I304e3702247a06507f5f4e23f8776331a3562c68 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214662 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: normalize board idAaron Durbin
Instead of relying on the encoding of gpio_get_in_tristate_values() normalize the ids. BUG=chrome-os-partner:31602 BRANCH=None TEST=Built and noted correct output w/ coresponding correct device tree selected in depthcharge. Change-Id: I6fc712aceb56d701725759503b9cfa1061ed25d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1037d473f35613bf39a4b27a9c1ade718b852c0d Original-Change-Id: I7d5449bc14e776fd9faa86af0f80690c3d9ae92d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214840 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Increase TrustZone Carveout Region sizeFurquan Shaikh
Increase TZ carveout region size to 4MiB. TTB lives in the first 1MiB of the trust zone. Rest of the TZ memory can be used by el3 monitor. BUG=chrome-os-partner:31615 BRANCH=None TEST=Compiles successfully and boots to kernel Change-Id: I448574860186815992c15a358a1481faecf224bd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de0f3f8016a4e566a2bacb967ef92213648d8257 Original-Change-Id: I1f25b7b119037cba7055a1bd61997f020a0b1010 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214370 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: initialize LTE modemBen Chan
BUG=chrome-os-partner:30748 TEST=Verify that LTE modem appears on USB during kernel boots on Ryu. Change-Id: I5b73a632ab827abe9c064a097e04d2c9030f9b46 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 070538e60b384d17e17ba3544881ef642c3f33ba Original-Change-Id: I8ec1f94c9aec5b4895a01cdfd3b86f88cd6bb877 Original-Signed-off-by: Ben Chan <benchan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214020 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: refactor cpu startup codeAaron Durbin
In order to more easily bring up the 2nd core refactor the cpu startup logic. A common 32bit_entry.S is compiled both for romstage and ramstage to provide the common 32-bit entry point. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted ryu to the kernel. Also, can get the 2nd core up out of reset. Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5 Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213850 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31515 BRANCH=None TEST=test_exception generates a page fault which is handled by the exception handler and execution continues after eret from the exception Change-Id: Ie550492d2ed21b2c3009b5627f1e1a37429e6af0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e29fe77745d10e840c02498e54a0c53835530e5e Original-Change-Id: I29b7dabaece9b11a04ee3628d83513d30eb07b1d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213661 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: Initialize exception stackFurquan Shaikh
Initialize the exception stack on stage_entry BUG=chrome-os-partner:31515 BRANCH=None TEST=Exception handling works fine Change-Id: I66b4e73e77ad746e891cb2ae6662fbf0531f9d8a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a21d0a432e1742fd8b36b3f8fc7748152f7d74d2 Original-Change-Id: I0b6fb95c660c68fb47a30e905acb910b0e2eafea Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213673 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add exception stack top addressFurquan Shaikh
BUG=chrome-os-partner:31515 BRANCH=None TEST=Exception handling for ryu works fine Change-Id: Ibeac161428c77718a640aa11361fb8d822b4a343 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 131f9fca0995a8d07972a5bc5ec76bfea0f1cb42 Original-Change-Id: I5b109d9eb692b9e4ef4bc1f6cf267420f50764da Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213674 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: use named bus numbers instead of literalsAaron Durbin
Use the bus number enumerations from funit to make the pad names and bus numbers consistent and clearer. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted to kernel. Change-Id: If84ed825537f598c033dcacbcba759e0fe4e90ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4375a8e47f572d618044f65603fb9288832f936 Original-Change-Id: I817a56e879ecc96474128d624dc46c12ebc5c7a8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213492 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add enums for bus namesAaron Durbin
Instead of requiring the mainboards to know the magic literals for the bus numbers provide an easier name to number to handle all the weird ordering. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted on ryu. Change-Id: I4a90f5f5f3ed1d936e2eee23f4726069adc49cc7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b028e90650384c947a3d0ee84c6d1346a22b22b9 Original-Change-Id: Id4d773d3049a43b186711900c61935ba7f3562ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213491 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: initialize GICAaron Durbin
This provides are barebones initialization for tegra132 GIC on CPU0. It routes all interrupts to CPU0, moves them all into group 1, and attempts to allow non-secure access for all registers (doesn't appear to be implemented, though). BUG=chrome-os-partner:31449 BRANCH=None TEST=Built and booted past smp init in the kernel. Timers appear to be flowing now since jiffies are updated. Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212795 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: move page tables to trustzone regionAaron Durbin
In order to access secure device register space the cpu needs to have the page tables marked as secure memory. In addition the page tables need to live within secure memory otherwise the accesses default to non-secure. Therefore move the page tables to the trustzone region. Remove the TTB_* config options as well as removing the TTB reservations from coreboot's resource list. BUG=chrome-os-partner:31355 BUG=chrome-os-partner:31356 BRANCH=None CQ-DEPEND=CL:213140 TEST=Built and booted into kernel. Change-Id: I1fc8dda932c36935f8523792bc1147f6b0743d11 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1522a83bb57e33749843d5b3ea5545ded97a3953 Original-Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213141 Reviewed-on: http://review.coreboot.org/8994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: Add pad/funit init for i2c6 (audio codec, etc.)Tom Warren
BUG=none BRANCH=none TEST=built ryu, booted to recovery mode OK Ran TegraShell and could r/w I2C6 regs OK Change-Id: I7dca131ab5bd4dac50891937f792ac70b1bb532f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 29591a97fbb8fc42143ff6c7838c9935834ca516 Original-Change-Id: Ic74e3518ab69ec7b1bc3bc4f637b7b38b85734c9 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212926 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add special I2C6 initTom Warren
I2C6 has a special mux in the SOR/DC domain, so there's a ton of devices that need to be clocked, SOR unpowergated, and then the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register. BUG=none BRANCH=none TEST=none, built rush/ryu AOK Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35 Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212887 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: separate/refactor clock enable/reset codeTom Warren
Added distinct functions for clock_enable and clock_clear_reset, and rewrote clock_enable_clear_reset() to use them. Useful when unpowergating SOR partition, for instance, where we need to enable a bunch of periph clocks, unclamp SOR, then take all of those periphs out of reset. BUG=none BRANCH=none TEST=none, built rush/ryu OK. Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2 Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212916 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: never recover cbmem from romstageAaron Durbin
Tegra132 has 2 different paths for booting and resuming from sleep. The boot path uses the typical bootblock, romstage, and ramstage. However, the resume path is completely orthogonal. cbmem_initialize() attempts to recover the cbmem area, but that functionality should not be used from romstage because tegra132 is by definition in a fresh boot if it is executing romstage. Therefore, use cbmem_initialize_empty() so that cbmem is always initialized from scratch on each boot. BUG=chrome-os-partner:31239 BRANCH=None TEST=Built and ran on ryu. Was able to enter recovery and stay in recovery without entering a reboot loop. Change-Id: I0453c15e57a873a7ce7a63190dceafb75e4c9342 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 28ebc092e6721552c18db03e7578424c23a64b64 Original-Change-Id: I2016146fdc3aea493a78bab31ea8c8cbd78935c5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211424 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27samus: Update SPD with correct geometry and timingsDuncan Laurie
This memory is also x16 and needs slight tweak to tRFCmin in order to be functional. BUG=chrome-os-partner:31833 BRANCH=None TEST=build and boot on EVT unit with this config Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6 Reviewed-on: http://review.coreboot.org/8972 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-27broadwell: Fix some errors in selftestKane Chen
1. Fixed some errors in selftest compare to reference. 2. Some WA steps for xhci in sleep trap is only for lpt. BUG=chrome-os-partner:28234 TEST=compile ok, run selftest on auron to verify boot to OS BRANCH=None Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131 Original-Reviewed-on: https://chromium-review.googlesource.com/215646 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Original-Tested-by: Kane Chen <kane.chen@intel.com> (cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf Reviewed-on: http://review.coreboot.org/8971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27samus: Add PD MCU ACPI device and unmask host eventShawn Nematbakhsh
Samus has a PD MCU, and should handle PD MCU host events. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Verify that ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214860 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit d0752be013f66313d4218338e62372d0f5975097) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I08eb51eceeb7d2835d55e7e861126b137de72bf6 Reviewed-on: http://review.coreboot.org/8969 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27chromeec: Add ACPI device for PD MCU and handle related EC host eventShawn Nematbakhsh
Add ACPI device for PD MCU, if present. Call Notify routine when the corresponding EC host event is received. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Enable EC_ENABLE_PD_MCU_DEVICE, unmask PD MCU host event, and verify ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: I6db61031e434d7ecb211802a4caeaba051e22a28 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214809 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit 226b349e40ed8eacce20d0a8063877382f707c69) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iecff6c06f1b37651ff61e36d6085d397d66f861c Reviewed-on: http://review.coreboot.org/8968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Apply pcie updates from 2.1.0 ref codeKane Chen
some clock gating and pcie settings are missed in original code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214568 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093 Reviewed-on: http://review.coreboot.org/8967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Read and save HSIO version from ME in romstageDuncan Laurie
This can be used to know if HSIO registers need updating in ramstage but it is not possible to query the ME for HSIO version after sending the DRAM-init-done message. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus, check for HSIO version messages in log Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13 Reviewed-on: http://review.coreboot.org/8966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix GPE register addressesDuncan Laurie
This macro is incorrect and should be counting by dword instead of byte. The effects of this were subtle: incorrect events in ELOG and hanging when waking from USB input because PME_B0 was not disabled properly. BUG=chrome-os-partner:31611 BRANCH=none TEST=test wake from suspend with USB keyboard Original-Change-Id: I7caf1d46283071787550a9765703897181774957 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214258 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b Reviewed-on: http://review.coreboot.org/8965 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Changes from 2.2.0 ref codeDuncan Laurie
- The SATA CAP register setup was moved outside the refcode blob we run so it needs to be set up by coreboot again... - Slight tweak to fast ramp voltage for broadwell CPU BUG=chrome-os-partner:25491 BRANCH=None TEST=Build and boot on samus Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173 Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/214024 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1 Reviewed-on: http://review.coreboot.org/8964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Updates for EVT boardDuncan Laurie
- Remove NFC GPIOs - Change EC wake to GPIO27 - Enable wake on HOTWORD_DET_L_3V3 - Add new Hynix memory SKU BUG=chrome-os-partner:31549 BRANCH=none TEST=emerge-samus coreboot, cannot fully test until EVT Original-Change-Id: Ia25fc39f0b67c53305b3fd9150117d6a7867eb3a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213796 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 740ac0bb7eaa9ae35fce8a04825f9c5ecf7cab79) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1c194eae2ebc53291f078c00ba04f82e10b0c1 Reviewed-on: http://review.coreboot.org/8963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Switch to using broadwell platform ASLDuncan Laurie
Instead of providing a local copy use the chipset provided one. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus Original-Change-Id: I60dd9bbeefbf4298511abec54635c515fc9b1621 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9dc8e7ae61f0337aa145b7d99acc23852d1cfc9a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I259be321e01e2047666b4be106dea59a5578d9d3 Reviewed-on: http://review.coreboot.org/8962 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add broadwell specific platform ASLDuncan Laurie
This can be shared between mainboards, they are still free to override if needed. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/213792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e40cb804e7a95ce2183ebb3ef5d86820aef61b5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: fixed power gating enable for disabled sata portKane Chen
The original code won't set power gating for disabled port correctly, due to it must be set before Lock BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify bit 24, 26 is set in RCBA(0x3a84) for samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab Original-Reviewed-on: https://chromium-review.googlesource.com/213561 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 066c8c81df8be9ae9ab7b33342a93b0b3ea7b240) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic7c87b04863f93de5665d72e0f95b4105b1d4d3b Reviewed-on: http://review.coreboot.org/8960 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: sata updates from 2.1.0 ref codeKane Chen
fixed a coding error and sync sata configuration with ref code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213137 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa Reviewed-on: http://review.coreboot.org/8959 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix devslp enable to use correct registerDuncan Laurie
This was a merge error when I was pulling in some of the code into this file I put it after the read of CAP2 but before it is modified and written back. In the end the DEVSLP bits are getting set/cleared that need to but the other bits in the register may be wrong. Also when enabling devslp set the devslp-present bit in each enabled port. Also remove much of the 0:1f.2@0x98 setup and the attempt to write (the write once) CAP register that is already being written in the reference code. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212308 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77 Reviewed-on: http://review.coreboot.org/8958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add small delay before Flex Ratio rebootDuncan Laurie
In order to prevent possible TPM lockout due to PLTRST assertion shortly after powering up add a small delay before the reset. This will affect cold power up only, reboot/resume/warmboot will all have the flex ratio locked already so this reset is unneeded. BUG=chrome-os-partner:29859 BRANCH=None TEST=build and boot on samus. I tried unsuccessfully to trigger the TPM lockout, but I was not able to do that consistently without this patch so it is unknown yet whether this is 100% effective. Original-Change-Id: Ief8c9261c0268b0f90a3022213ebd2b06633b481 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 20413f2eafa144f5f381eb6f92d8b959415ca049) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I665e9ed1faa65e88d988660a24bdad40a4c5ab7e Reviewed-on: http://review.coreboot.org/8957 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix TCO register size and event reportingDuncan Laurie
TCO registers are 16bit not 32bit. Also do not log the TCO reset event in S3 resume path to avoid it being logged when TCO is not actually tripping. BUG=chrome-os-partner:28234 BRANCH=None TEST=manual: 1) build and boot on samus 2) modify kernel command line with nmi_watchdog=0 3) while sleep 1 ; do echo -n V ; done > /dev/watchdog & 4) fg 1 5) ctrl-Z 6) wait for reboot 7) check event log for TCO event 8) check suspend/resume path to ensure no TCO event logged Original-Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211840 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5952fe4672d07bd39e345f2048c2bfc510bf9f2a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6cdeffb8b50c5001d714edd3a1264cf117cd1ad6 Reviewed-on: http://review.coreboot.org/8954 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Enable WLAN wake GPIO in _PRWDuncan Laurie
Add ACPI device for WLAN and enable GPIO 10 as wake source in _PRW. BUG=chrome-os-partner:28234,chrome-os-partner:30671 BRANCH=None TEST=boot on samus, check for WLAN in /proc/acpi/wakeup Original-Change-Id: I09b6eeae5bd88ee9d7e0b7e735ed871e8ae6963a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211820 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c65ce028e64aebffb99648b2c34c4ff0e7c4e70f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If192564ddd10c7fe758a4d7266394a30e7d966d4 Reviewed-on: http://review.coreboot.org/8953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Misc updates from 2.1.0 ref codeDuncan Laurie
- ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211611 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99 Reviewed-on: http://review.coreboot.org/8952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Fix some SPD geometry againDuncan Laurie
I was using the wrong datasheet for these parts. Revert to the previous geometry settings so they work again. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Ibc4a864d458e5ee5ef69aa4f1db5efe14076422a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211610 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f8591e1579d205609a959082d8047d407b4f6a5a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I52ed3609c9686fef13711578597065ca4e907df4 Reviewed-on: http://review.coreboot.org/8951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Disable CMDPWR on broadwellKane Chen
Workaround for auto shutdown issue on broadwell SKU. Now we can see C7 transition, and MRC fastboot BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build ok and boot on samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e Original-Reviewed-on: https://chromium-review.googlesource.com/210870 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a Reviewed-on: http://review.coreboot.org/8950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Tweak GFXPAUSE settings based on revisionDuncan Laurie
Changes from 2.1.0 reference code release. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I6110a9bdb2973f1a134d8105c37659bf43f61d34 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210607 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ef660ddc6c17a003f06b8995e821c7642c49a56e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibb41cd7369cfc7b9b86b61460650a56415b3d8fb Reviewed-on: http://review.coreboot.org/8949 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Update SPDDuncan Laurie
- geometry was incorrect for 8GB modules, should be x32, so refactor the rest of the geometry to match - some of the timing values were off, calcualte new values from the datasheet BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I645f354ef21c5032ab73c66e1ad843136ec93eff Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8b2ce5c58442e039f5f6e0e053c0072fdec76e9c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29daa9e0ad1bf32be914c0d998f188b9827344a1 Reviewed-on: http://review.coreboot.org/8948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add config option to disable DSP power gating in D3Duncan Laurie
This is useful for debug and testing. BUG=chrome-os-partner:29649 BRANCH=None TEST=build and boot on samus Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210599 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e Reviewed-on: http://review.coreboot.org/8947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-26timer: remove rela_time typeAaron Durbin
Current usage doesn't require rela_time. Remove it. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I25dcc1912f5db903a0523428ed1c0307db088eaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26a13d4c615473407f401af4330199bbfe0dd2b1 Original-Change-Id: I487ea81ffb586110e9a1c3c2629d4af749482177 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219714 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rk3288: switch to stopwatch APIAaron Durbin
Instead of using rela_time use the stopwatch API as the semantics fit perfectly with the expiration usage. BUG=None BRANCH=None TEST=None, but similar usage tested on tegra132. Change-Id: I91ef59212a2dd1b48640b1aaaab6acacf4e9b3e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1dd8380f04641f4f73caa3441f349d9eca6be05 Original-Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219713 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26cbfs: support concurrent media channels properlyVadim Bendebury
Coreboot generic CBFS media API does not support multiple media access instances, but it should. With this fix the CBFS context (memory cache for SPI accesses) is shared among all open media access streams. A better memory management scheme might be required, but for now this fix allows to support booting deptcharge and accessing VPD through two independent CBFS media streams. BUG=chrome-os-partner:32152 TEST=no exception is thrown when the second stream is opened Change-Id: I62889089b4832c9e9760ef24ecc517220d8f3ec4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 691f9794805d04beff349f1bc60ac9d7530d7cbf Original-Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219441 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: Remove CHROMEOS defaultPatrick Georgi
We don't set these by default in upstream. Change-Id: Ida7aa498e0fe291c6cf3cf31d6516530a9d136d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-26Chrome OS vendorcode: Fix vboot_reference compilationStefan Reinauer
Includes moved into $(CPPFLAGS_*), so add that to VBOOT_CFLAGS. Shift vboot build parameters from the environment to be make parameters, and use $(MAKE) instead of make to fix non-Linux build systems. Change-Id: I5aee9935ab36ad571fbcf9f6fa8d8ace2bac16b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-26tegra132: allow mainboards to insert memory regions in address mapAaron Durbin
Depending on the needs of the mainboard certain regions of the address map may need to be adjusted. Allow for that. BUG=chrome-os-partner:31293 BRANCH=None TEST=With ryu patches able to insert a non-cacheable memory region. Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9 Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212161 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26arm64: Seed the stack at stage_entryFurquan Shaikh
Seed the stack in order to avoid boot process from complaining false stack overflow. BUG=chrome-os-partner:30824 BRANCH=None TEST=Compiles successfully for rush and stack overflow error fixed in boot flow Change-Id: I5d29d24eb5270d38a35a32171881b1aab8bf32e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26e53568e82ad8418c20c2410f0cbc5c444c9917 Original-Change-Id: Ie51e1bcd263e3b886feb2e0e9c7d544f23c3444e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210594 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8942 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: Initialize CNTFRQFurquan Shaikh
BUG=chrome-os-partner:31356 BRANCH=None TEST=Kernel boots with the changes required in depthcharge Change-Id: I061305e0ab8f6145c0dc74b2ff958a667ff7276a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ff2fc86c1c6e6b592fa3faffd360a3a8c6351a9 Original-Change-Id: If1c5850607174ab0f485ef41d47016056d9832cd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212730 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8941 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add I2C6 controller to funit libraryTom Warren
BUG=None BRANCH=None TEST=Built rush and ryu, ran on rush into recovery mode. I2C6 is in the SOR domain, so a lot of further init is needed before it can be used. A follow-on patch will do this. Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46 Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212671 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8940 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: enable external usb 2.0 portAaron Durbin
BUG=chrome-os-partner:31293 BRANCH=None TEST=Able to get sporadic USB communication in depthcharge on ryu. Change-Id: I6bf6559d167a6ea94523d2500b54c1c7854330f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5412cfc149902298f2ebeb3030d8f09f27e5ee8 Original-Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212333 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add usb initialization support to funitAaron Durbin
Continuing down the path of easing mainboard maintenance provide a way to bring up the USB 2.0 ports through funit. BUG=chrome-os-partner:31251 BRANCH=None TEST=With ryu patch was able to get same sporadic USB communication. Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212332 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8938 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: Add usb support for rush in corebootFurquan Shaikh
BUG=chrome-os-partner:31293 BRANCH=None TEST=With non-cacheable memory region and dma range addition, booting from usb reaches the same point as mmc. Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211039 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: include what is actually usedAaron Durbin
The clk_rst.h file wasn't including files that had functionality it was using resulting in broken builds if just this file was included. BUG=None BRANCH=None TEST=Built with just this file included -> no more errors. Change-Id: I229cb3890f1320edc3bc3e82469b301cbaff0f72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 03b455aa9da64d6e110690206db65939ca023c27 Original-Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212331 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: provide more robust array bounds checkingAaron Durbin
Make sure the array size matches the number of supported FUNITs. Also remove the FUNIT_NONE enumeration so that there isn't an empty slot in the array at index 0. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built when array wasn't large enough. Compiler threw an error. Change-Id: I1b83ddff799a56ea39efa23a91dca1a9e0f10862 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4cbe74905bbeb815e9f20bcc0fad3751a3133b04 Original-Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212330 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8935 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add base addresses to funit structuresAaron Durbin
To provide easier access to the base addresses of the controllers by funit identifier add the base addresses to the data structure. BUG=chrome-os-partner:31251 BUG=chrome-os-partner:31106 BRANCH=None TEST=Built. Change-Id: I427d432beef36e6342c188d607c0e33b3845c0e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8f09e61e3dbfbc96980b98ad25e09554fd49a8d Original-Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212169 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8934 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add more base addresses to address mapAaron Durbin
Provide consistently named base address enumerations as well as provide some that were missing. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built. Change-Id: I2551bbaa83d1d2c158b87d239098c22fba4d3961 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07954a231f3c11c4102f9db0a2d35654abda208f Original-Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212168 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 07:01:36 +0000