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2018-11-16src: Remove unneeded include <cbfs.h>Elyes HAOUAS
Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29303 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mainboard: Add ASRock H81M-HDSTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. The file `data.vbt` matches the VBT in the latest stable version of the vendor firmware (version 2.20). Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-16sb/intel/lynxpoint: Generate the ACPI FADT with a common functionTristan Corrick
The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x. Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux 4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel log. System reset, poweroff, and S3 suspend/resume continue to work. General improvements -------------------- - `fadt->preferred_pm_profile` is set based on the value of `CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded. - Constants are used instead of magic values in more locations. - `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set appropriately depending on whether the system uses Lynx Point LP or not. - Boards can indicate docking support in the FADT via the devicetree. Changes to existing Lynx Point boards ------------------------------------- - `header->asl_compiler_revision` changes from 1 to 0. - `fadt->model` is left at 0 instead of being set to 1. This field is only needed for ACPI 1.0 compatibility. - `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is because their values are ignored, since `ACPI_FADT_WBINVD` is set in `fadt->flags`. - `fadt->duty_offset` is set to 0 instead of 1. None of the existing boards indicate support for changing the processor duty cycle (as `fadt->duty_width` is set to 0), so `fadt->duty_offset` does not currently need to be set. - Access sizes of registers are set. - On mb/intel/baskingridge, the pmbase is now read using the common function `get_pmbase()` instead of `pci_read_config16(...)`. - On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width` changes from 64 to 128. The correct value should be 128 (bits), to match `fadt->gpe0_blk_len`, which is set to 16 (bytes). - On Lynx Point LP systems, the unused extended address `fadt->x_gpe0_blk` sets its address space ID to be consistent with other unused extended addresses. Such a change should not alter the interpretation of the registers as being unused. Why not set them all to zero? Simply because the existing practice, in both coreboot and some other vendors' firmware, has them set in such a case. A diff of the FADT from a Google Peppy board is below: --- pre/facp.dsl 2018-10-30 20:14:52.676570798 +1300 +++ post/facp.dsl 2018-10-30 20:15:06.904381436 +1300 @@ -1,179 +1,179 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * - * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018 + * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : 61 +[009h 0009 1] Checksum : 6E [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" -[020h 0032 4] Asl Compiler Revision : 00000001 +[020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] FACS Address : 7BF46240 [028h 0040 4] DSDT Address : 7BF46280 -[02Ch 0044 1] Model : 01 +[02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 02 [Mobile] [02Eh 0046 2] SCI Interrupt : 0009 [030h 0048 4] SMI Command Port : 000000B2 [034h 0052 1] ACPI Enable Value : E1 [035h 0053 1] ACPI Disable Value : 1E [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 [038h 0056 4] PM1A Event Block Address : 00001000 [03Ch 0060 4] PM1B Event Block Address : 00000000 [040h 0064 4] PM1A Control Block Address : 00001004 [044h 0068 4] PM1B Control Block Address : 00000000 [048h 0072 4] PM2 Control Block Address : 00001050 [04Ch 0076 4] PM Timer Block Address : 00001008 [050h 0080 4] GPE0 Block Address : 00001080 [054h 0084 4] GPE1 Block Address : 00000000 [058h 0088 1] PM1 Event Block Length : 04 [059h 0089 1] PM1 Control Block Length : 02 [05Ah 0090 1] PM2 Control Block Length : 01 [05Bh 0091 1] PM Timer Block Length : 04 [05Ch 0092 1] GPE0 Block Length : 20 [05Dh 0093 1] GPE1 Block Length : 00 [05Eh 0094 1] GPE1 Base Offset : 00 [05Fh 0095 1] _CST Support : 00 [060h 0096 2] C2 Latency : 0001 [062h 0098 2] C3 Latency : 0057 -[064h 0100 2] CPU Cache Size : 0400 -[066h 0102 2] Cache Flush Stride : 0010 -[068h 0104 1] Duty Cycle Offset : 01 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 [069h 0105 1] Duty Cycle Width : 00 [06Ah 0106 1] RTC Day Alarm Index : 0D [06Bh 0107 1] RTC Month Alarm Index : 00 [06Ch 0108 1] RTC Century Index : 00 [06Dh 0109 2] Boot Flags (decoded below) : 0003 Legacy Devices Supported (V2) : 1 8042 Present on ports 60/64 (V2) : 1 VGA Not Present (V4) : 0 MSI Not Supported (V4) : 0 PCIe ASPM Not Supported (V4) : 0 CMOS RTC Not Present (V5) : 0 [06Fh 0111 1] Reserved : 00 [070h 0112 4] Flags (decoded below) : 00008CAD WBINVD instruction is operational (V1) : 1 WBINVD flushes all caches (V1) : 0 All CPUs support C1 (V1) : 1 C2 works on MP system (V1) : 1 Control Method Power Button (V1) : 0 Control Method Sleep Button (V1) : 1 RTC wake not in fixed reg space (V1) : 0 RTC can wake system from S4 (V1) : 1 32-bit PM Timer (V1) : 0 Docking Supported (V1) : 0 Reset Register Supported (V2) : 1 Sealed Case (V3) : 1 Headless - No Video (V3) : 0 Use native instr after SLP_TYPx (V3) : 0 PCIEXP_WAK Bits Supported (V4) : 0 Use Platform Timer (V4) : 1 RTC_STS valid on S4 wake (V4) : 0 Remote Power-on capable (V4) : 0 Use APIC Cluster Model (V4) : 0 Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 0 Low Power S0 Idle (V5) : 0 [074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 01 [SystemIO] [075h 0117 1] Bit Width : 08 [076h 0118 1] Bit Offset : 00 -[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[077h 0119 1] Encoded Access Width : 01 [Byte Access:8] [078h 0120 8] Address : 0000000000000CF9 [080h 0128 1] Value to cause reset : 06 [081h 0129 2] ARM Flags (decoded below) : 0000 PSCI Compliant : 0 Must use HVC for PSCI : 0 [083h 0131 1] FADT Minor Revision : 00 [084h 0132 8] FACS Address : 000000007BF46240 [08Ch 0140 8] DSDT Address : 000000007BF46280 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 01 [SystemIO] [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 -[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[097h 0151 1] Encoded Access Width : 02 [Word Access:16] [098h 0152 8] Address : 0000000000001000 [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 01 [SystemIO] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000 [0ACh 0172 12] PM1A Control Block : [Generic Address Structure] [0ACh 0172 1] Space ID : 01 [SystemIO] [0ADh 0173 1] Bit Width : 10 [0AEh 0174 1] Bit Offset : 00 -[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16] [0B0h 0176 8] Address : 0000000000001004 [0B8h 0184 12] PM1B Control Block : [Generic Address Structure] [0B8h 0184 1] Space ID : 01 [SystemIO] [0B9h 0185 1] Bit Width : 00 [0BAh 0186 1] Bit Offset : 00 [0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] [0BCh 0188 8] Address : 0000000000000000 [0C4h 0196 12] PM2 Control Block : [Generic Address Structure] [0C4h 0196 1] Space ID : 01 [SystemIO] [0C5h 0197 1] Bit Width : 08 [0C6h 0198 1] Bit Offset : 00 -[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8] [0C8h 0200 8] Address : 0000000000001050 [0D0h 0208 12] PM Timer Block : [Generic Address Structure] [0D0h 0208 1] Space ID : 01 [SystemIO] [0D1h 0209 1] Bit Width : 20 [0D2h 0210 1] Bit Offset : 00 -[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32] [0D4h 0212 8] Address : 0000000000001008 [0DCh 0220 12] GPE0 Block : [Generic Address Structure] -[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DCh 0220 1] Space ID : 01 [SystemIO] [0DDh 0221 1] Bit Width : 00 [0DEh 0222 1] Bit Offset : 00 [0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] [0E0h 0224 8] Address : 0000000000000000 [0E8h 0232 12] GPE1 Block : [Generic Address Structure] [0E8h 0232 1] Space ID : 01 [SystemIO] [0E9h 0233 1] Bit Width : 00 [0EAh 0234 1] Bit Offset : 00 [0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] [0ECh 0236 8] Address : 0000000000000000 Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29387 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHzCaveh Jalali
With this change, coreboot thinks we're running at 1MHz: DW I2C bus 2 at 0xd1133000 (1000 KHz) Elan eKT3644 IC Specification (trackpad) requires: Low Time larger than 500ns (61 * 8.3ns = 506ns). High Time larger than 260ns (32 * 8.3ns = 265ns), Data Hold_time larger than 0ns. Start Condition Hold time larger than 250ns. Rise/Fall time of less than 120ns. HCNT controls both High Time and Start Condition Hold time. LCNT controls Low Time. SDA_HOLD controls Data Hold Time. P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned using resistors on the board and must be considered when adjusting any of the parameters since these times are all measured at 30 or 70% of base and peak voltages (0v/1.8v). The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20 which yields the SCL at around 950KHz - suboptimal but compliant. Lower LCNT or HCNT results in "lost arbitration" errors or not complying with eKT3644 requirements. Verified by gaggery.tsai@intel.corp-partner.google.com. Scope shots posted here: https://b.corp.google.com/issues/78601949#comment177 BUG=b:78601949 BRANCH=none TEST=Farzam provided test points on track pad for SCL/SDA/GND. Waveforms measured with oscilloscope and screen shots attached to bug (comment #177, #155, #100). Operate trackpad/touchscreen Review dmesg (kernel) output for correct speed, parameters, and no errors (e.g. "lost arbitration" or "host controller timeout") Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38 Signed-off-by: Caveh Jalali <caveh@chromium.org> Signed-off-by: Grant Grundler <grundler@chromium.org> Tested-by: gaggery.tsai@intel.corp-partner.google.com Tested-by: grundler@chromium.org Reviewed-on: https://review.coreboot.org/29553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-11-16mb/intel/whlrvp: Enable HDA controller driverLijian Zhao
Enable HDA controller coreboot driver for Whiskey Lake RVP platform on top of common code. BUG=N/A TEST=Build and boot up on whiskey lake rvp board, comfirm audio playback is working. Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/28781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-11-16soc/intel/denverton_ns/Kconfig: Remove unused HSUART_FUNCElyes HAOUAS
Change-Id: I1ec6f0687083c17314588c85af289b4b27c5441c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29598 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16amd/{nb/amdfam10,cpu/pi}/Kconfig: Remove unused symbolsElyes HAOUAS
Change-Id: I7019d70b7e6f8ae041a12d6bab83127e9e70868c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16soc/intel/common/Kconfig: Remove unused SOC_INTEL_COMMON_SMIElyes HAOUAS
Change-Id: Ic4ea1d681d2677880b155713c34152ac0861146b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16mb/intel/cougar_canyon2: Fix SMBIOS_ENCLOSURE_TYPE symbolElyes HAOUAS
Change-Id: I9f4640ef040dc6a1d39ecb8b3378266e4dd5cec9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16soc/qualcomm/ipq{40xx,806x}/Kconfig: Remove unused MBN_ENCAPSULATIONElyes HAOUAS
Change-Id: I4cf5cd1d3bed7188590e4f143d8f14dc9e58b183 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16soc/intel/{broadwell,skylake}: Remove unused SERIAL_CPU_INITElyes HAOUAS
Change-Id: I2296ab3c53a82ee990649e35e1370e1dd304e392 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16mb/msi/ms9652_fam10: Remove unused VAR_MTRR_HOLEElyes HAOUAS
Change-Id: Ibbc010c9550c0a50b1e913e198f9b575107572fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16mb/{google/cyan,intel/strago}: Remove unused DYNAMIC_VNN_SUPPORTElyes HAOUAS
Change-Id: I4d0df30255d006c0399dde1b3ba8ee513d98dc0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src/drivers/vpd: Remove unused VPD_DEBUGElyes HAOUAS
Change-Id: Iba838309f8055d364c5f846ce29e628067d7b5f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"Elyes HAOUAS
Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macroPeter Lemenkov
This macro is no longer used since commit dd2bc3f8 with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
2018-11-16mb/google/kalista: Disable EC-EFSDaisuke Nojiri
Only input from the BJ port is wired to VSYS on Kalista. VBUS from USB-C is for output only. In other words, Kalista is a source only device from a USB/PD perspective. This patch disables EC-EFS, which would be needed for the EC to jump to RW to get PD power before the AP boots. Kalista will be always supplied enough power to boot the AP through the BJ port. CQ-DEPEND=CL:1330171 BUG=b:118386511 BRANCH=none TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work. Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/29564 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mediatek: Refactor PMIC wrapper code among similar SoCsTristan Shieh
Refactor PMIC wrapper code which will be reused among similar SoCs. Move reusable code into the common folder. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16soc/intel/braswell: add vmx support via CPU_INTEL_COMMONMatt DeVillier
Braswell allready supported vmx, but offered no mechanism to unset it, nor to set the lock bit required for Windows to recognize virtualization. Enable this functionality by adding CPU_INTEL_COMMON config. Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows virtualization as enabled. Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/29570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU onlySeunghwan Kim
GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0 for only 2nd SKU. BUG=none BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/29631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16mb/google/poppy/variant/nocturne: Configure GPP_E1 for WLAN_WAKE_LNick Vaccaro
The GPP_E1 gpio was incorrectly being defined as a no-connect. Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic. BUG=b:119508897 TEST=Build and flash nocturne, boot nocturne and 1) Verify nocturne can successfully suspend/resume from S3 and S0ix. 2) Verify wake from wlan wakes device from S3 and S0ix. To do so, a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT b) connect DUT to mobile hotspot c) sleep device via "powerd_dbus_suspend" d) turn off hotspot, verify DUT wakes from S0ix e) enable hotspot again f) connect DUT to hotspot g) sleep DUT via "sudo echo mem > /sys/power/state" h) turn off hotspot, verify DUT wakes from S3 Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16src: Remove unneeded include <pc80/keyboard.h>Elyes HAOUAS
Change-Id: I0dcdfb1fa782c7936a19de11adcf17387f49d9db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16sb/amd/cs5536: Remove unneeded include <cpu/x86/bist.h>Elyes HAOUAS
Change-Id: Ifae9d67bbba57b30ee9a2f31c448efcb27981c57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16fsp_broadwell_de: Switch to common SPI controller driverWerner Zeh
The common SPI controller driver in src/southbridge/intel/common does match the SPI controller included in the PCH of Broadwell-DE SoC. Switch to the usage of this driver and delete the dedicated one for the FSP based Broadwell-DE implementation. TEST: Boot mc_bdx1 with SPI driver active in romstage Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/29633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16mb/*/*/Kconfig: Don't specify devicetree path if default val usedPeter Lemenkov
Change-Id: I3d77a625c5ece7b7ea5476fe0bd42829d1fc72c4 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29625 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16mb/cavium/cn8100_sff_evb: adjust fmapMarcello Sylvester Bauer
Adjust the default fmap description file. Tested on real hardware. Change-Id: I46165eb27314a500187bcd24e3e201cf6a3175e7 Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com> Reviewed-on: https://review.coreboot.org/29596 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/lenovo/x60/dsdt: Remove unused includePeter Lemenkov
Tested - builds fine with this patch. Change-Id: I4666a8c9dd0e03ee32770844019dfc032e07e460 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
2018-11-16soc/amd: Convert from AMD units to coreboot unitsRichard Spiegel
There are several files under soc/amd that use units defined by file porting.h. These units use upper case, and are not recognized by checkpatch, thus causing problems when defining a pointer (request to use space before and after the star symbol). These are the definitions from porting.h showing the units that this patch will change and their coreboot definitions (not all are actually used): typedef uintptr_t UINTN; typedef int64_t INT64; typedef uint64_t UINT64; typedef int32_t INT32; typedef uint32_t UINT32; typedef int16_t INT16; typedef uint16_t UINT16; typedef int8_t INT8; typedef uint8_t UINT8; typedef char CHAR8; typedef unsigned short CHAR16; typedef unsigned char BOOLEAN; typedef void VOID; BUG=b:118775313 TEST=Build and boot grunt. Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16soc/amd/common: Remove unused variables of write_pci_cfg_irqs()Richard Spiegel
Function write_pci_cfg_irqs() has "no function" variables. One variable is set and never used, the other is only used to control a print. Remove them. BUG=b:117950052 TEST=Build grunt. Change-Id: Icd98db3e794e609b112f15979a3a00a2977a0fdb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16sb/amd: Remove dead assignment in SPI driverPaul Menzel
Value stored to 'cmd' is never read Change-Id: I794b6e12f5af272705cd996f7ca5099e9b9dbfc7 Found-by: scan-build from clang 6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/29568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16sb/amd: Fix grammar in commentPaul Menzel
Change-Id: I478a59534ec997947855eb0ff228a0dd9e15a5a5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/29567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16siemens/mc_apl4: Clean up ramstageMario Scheithauer
Currently, there is nothing for this mainboard to do in ramstage. Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer
This mainboard is equipped with LPDDR4 modules. The corresponding memory swizzle data must be set for this purpose. Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16mb/google/octopus: override smbios manufacturer name from CBIWisley Chen
BUG=b:118798180 TEST=emerge-octopus Change-Id: I241a76e3b55ad721c6c0176462c310bcca6b3c5d Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29503 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16ec/google/chromeec: add support for retrieving OEM nameWisley Chen
OEM name can be stored in CBI. This change can support for fetching the OEM name from CBI. BUG=b:118798180 TEST=Verified to get data from CBI Change-Id: I4938c4d60fcad9e1f43ef69cc4441d1653de7e24 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-11-15soc/intel/skylake/acpi/dptf: Add support for Multi-DPTF ProfileKarthikeyan Ramasubramanian
Currently mode-aware DPTF depends on Tablet Mode Switch to load the right table. This does not scale well with device types and configuration. This change helps to decouple the mode-aware DPTF from Tablet Mode Switch. This change allows ACPI to load the appropriate DPTF table based on the profile number as detected by EC. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes(base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: Ibffe9c58f970aec37aa74a040170c4cf559bab33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29249 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-15google/chromeec/acpi/ec: Add support for Device DPTF Profile NumberKarthikeyan Ramasubramanian
In order to support Multi-DPTF profile, Device DPTF Profile Number is introduced into EC_ACPI_MEM_DEVICE_ORIENTATION ACPI Space at offset 0x09. This bit field stays along with Tablet Mode Device flag. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes(base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: Ie14916ac16c50cbe0990021e2eb03d5121cd0e07 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-15ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES since it aligns with the use-case. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes (base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-15src/mainboard/google: Remove defining EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Remove defining EC_ENABLE_TABLET_EVENT configuration from the boards where it is not required. BUG=b:118149364 BRANCH=None TEST=Build Change-Id: Iee70192916ac6c53bb27b7f73f3ad6d069afd030 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-15drivers/elog: Add support for early elogKarthikeyan Ramasubramanian
Add support to log events during the preram stages. BUG=b:117884485 BRANCH=None TEST=Add an event log from romstage, boot to ChromeOS Change-Id: Ia69515961da3bc72740f9b048a53d91af79c5b0d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-15soc/intel/cannonlake: Make static IRQ mapping for PIC modeSubrata Banik
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC. Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29629 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-15soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devicesSubrata Banik
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call due to PCH requirement change from CNP PCH onwards, hence making static IRQ mapping for pci_irqs.asl and pcie.asl Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/ Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-15drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATAElyes HAOUAS
Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-15src/cpu: Remove dead sourced linesElyes HAOUAS
Change-Id: I836ff09da17373d47daf21c98e5ab975836cd47e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-15oc/intel/quark/Kconfig: Remove unused MMCOMF_SUPPORT_DEFAULTElyes HAOUAS
Change-Id: I24596b7b4f3e7caef7f42e4317a786caa42c5c2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-14mb/emulation/qemu-i440fx|q35: Fix stack sizePatrick Rudolph
Current implementation works by luck as DCACHE area is actually RAM and stack can grow and use that RAM outside of the area. * Set DCACHE_BSP_STACK_SIZE to 0x4000. * Add an assert to make sure it is set to a sane value on all platforms. Change-Id: I71f9d74d89e4129cdc4a850acc4fc1ac90e5f628 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29611 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-13google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part NumberKevin Chiu
Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD". BUG=b:119400832 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage mosys memory spd print all 0 | DDR4 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD 0 | 4096 | 1 | 64 0 | DDR4-1333, DDR4-1600, DDR4-2400 Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/29557 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-13google/grunt/aleena: Update H1/TP/TS i2c timingsLucas Chen
After adjustment on aleena EVT Audio: 390.0 KHz H1: 390.0 KHz TP: 399.8 KHz TS: 399.8 kHz BUG=b:116306959 BRANCH=master TEST=emerge-grunt coreboot, scope measuring. Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-13mb/google/sarien: Enable EC _PTS/_WAK methodsDuncan Laurie
Enable the option to have the system level _PTS/_WAK methods call the EC provided methods when they are invoked by the OS. Verified on sarien board by inspecting dsdt.dsl: Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep { DBG0 = 0x96 \_SB.PCI0.LPCB.EC0.PTS (Arg0) } Method (_WAK, 1, NotSerialized) // _WAK: Wake { DBG0 = 0x97 \_SB.PCI0.LPCB.EC0.WAK (Arg0) Return (Package (0x02) { Zero, Zero }) } Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-13drivers/elog: Add Ramstage helper to add boot countKarthikeyan Ramasubramanian
Add a helper function specific to ramstage to add the boot count information into event log at ramstage. BUG=b:117884485 BRANCH=None TEST=Add an event log from romstage, boot to ChromeOS Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29542 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-13drivers/elog: Group event log state informationKarthikeyan Ramasubramanian
Group event log state information together to manage them better during different stages of coreboot. BUG=b:117884485 BRANCH=None TEST=Add an event log from romstage, boot to ChromeOS Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-13soc/intel/cannonlake: Remove SmbusEnableDuncan Laurie
Remove the SmbusEnable config option from devicetree and instead use the state of the PCI device to determine if it should be enabled or disabled. Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-13mb/cannonlake: Remove SmbusEnable from devicetreeDuncan Laurie
Remove the SmbusEnable parameter from all Cannon Lake mainboards. Instead this will be determined by the enable state of the SMBUS PCI device. Change-Id: I7ece6768da4c517747af12a07012583575816ae1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-13soc/intel/icelake: Update GPIOs for Icelake SOCAamir Bohra
This implementation updates the GPIO pins, communities and group mapping. Change details: 1. Update 5 GPIO community includes 11 GPIO groups GPIO COM 0 GPP_G, GPP_B, GPP_A GPIO COM 1 GPP_H, GPP_D, GPP_F GPIO COM 2 GPD GPIO COM 4 GPP_C, GPP_E GPIO COM 5 GPP_R, GPP_S 2. Update GPIO IRQ routing. 3. Add GPIO configuration for iclrvp board. Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-11-13mb/opencellular/rotundu: Remove unused CACHE_ROM_SIZE_OVERRIDEElyes HAOUAS
Change-Id: If77c23fc5d440fe9181e4aae72ffff8ddaa716b6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-13soc/intel/common: Add option to call EC _PTS/_WAK methodsDuncan Laurie
Some embedded controllers expect to be sent a command when the OS calls the ACPI \_PTS and \_WAK methods. For example see the code in ec/google/wilco/acpi/platform.asl that tells the EC when the methods have been executed by the OS. Not all ECs may define these methods so this change requires also setting a Kconfig option to enable it. Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-12mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggeredFurquan Shaikh
This change updates the configuration of EC_SYNC IRQ to be level triggered to match the EC behavior. Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-11-12mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCKPatrick Rudolph
Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like VBOOT with separate verstage. Changes: * Use symbols to set up CAR and STACK * Zero CAR area * Move BIST failure checking to cpu folder * Rename functions where necessary Tested: * qemu-2.11.2 machine pc * qemu-2.11.2 machine q35 Test result: * BIST error reporting is still working. * Console starts in bootblock * SeaBios 1.11.2 as payload is still working Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12mb/emulation/qemu-i440fx|q35: Get rid of unused headersPatrick Rudolph
Change-Id: I3cf0e4ef5b090d15ad823747fcf9219644e130fc Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-12mb/*/*: Harmonise FD and devicetree on boards featuring ICH7Arthur Heymans
On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-12intel/i945: Factor out ram init time stampsPaul Menzel
Instead of having the code for the RAM init time stamps in each mainboard’s `romstage.c`, factor it out to the northbridge code, done in commit 771328f7 (intel/i945: add timestamps in romstage). Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17994 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file"Elyes HAOUAS
Change-Id: I79e9b95059f16c53767c89cfaef1e89182be9c62 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29583 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12siemens/mc_apl4: Enable SDCARDMario Scheithauer
This mainboard also has a SD slot. Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer
This mainboard also has an external RTC chip, but not on this bus. The topic is currently in clarification and will be published with a later patch. In a first step we enable all I2C busses. Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer
Enable all PCIe root ports for this mainboard. Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
This mainboard provides customer hardware reset button. A feature of this button is that it holds the APL in reset state as long as the reset button is pressed. After releasing the reset button the APL should restart again without the need for a power cycle. When Bit 3 in Reset Control Register (I/O port CF9h) is set to 1 and then the reset button is pressed the PCH will drive SLP_S3 active (low). Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
For this mainboard the correction of transmit voltage swing from SATA interface is not necessary. Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 2 and 3 over two lanes (Device 13.0 and 13.1). The following routing is required: INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC# Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29513 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12mb/google/octopus/variants/fleex: Set up tcc offset for fleexJohn Su
Change tcc offset from 0 to 10 for fleex. Refer to b:117789732#1 BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-12ec/google/chromeec: Configure EC_SYNC_IRQ as level triggeredFurquan Shaikh
EC_SYNC_IRQ from EC to host is level-triggered in practice and configuring it as edge-triggered on the host results in host missing events if there are multiple events queued on the EC side. This is because Linux kernel driver reads one event per irq and the EC does not de-assert the interrupt line until all events are drained out. This results in event queue being filled up completely on the EC and the host failing to see any of those events. This change configures EC_SYNC_IRQ as level triggered to allow the host to read events from the the EC as long as the line is asserted. BUG=b:118949877 Change-Id: Id3fcfa0445f83865d57975a7bbc179dca047ba4c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2018-11-11mb/emulation/qemu-i440fx|q35: Link memory.cPatrick Rudolph
Link memory.c instead of including it. Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-10mb/lenovo/t400: Improve docking codePatrick Rudolph
* Remove dead code * Add support for types 2504 and 2505 * Print dock info at romstage entry * Improve dock disconnect for type 2505 * Move defines into dock.h for future ACPI code * Reduce timeouts according to spec to decrease boot time on error * Fix no docking detection (reduces boot time by 1 second) * Configure GPIO LDN before reading GPIOs * Use Kconfig values instead of fixed defines * Add documentation Tested on Lenovo T500 with docking 2504 and 2505. Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-09soc/intel/apollolake: Disable HECI1 before jumping to OSFurquan Shaikh
This change disables HECI1 device at the end of boot sequence. It uses the P2SB messaging to disable HECI1 device before hiding P2SB and dropping privilege level. BUG=b:119074978 BRANCH=None TEST=Verified that HECI1 device is not visible in lspci on octopus. Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-09arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATIONFurquan Shaikh
Change 76ab2b7 ("arch/x86: allow global .bss objects without CAR_GLOBAL") allowed use of global .bss objects and hence moved around the macros resulting in car_active returning 0 even for those boards where CAR is actually active but do not require global migration. This resulted in boards getting stuck when doing a reset in verstage because the code flow incorrectly assumed that there was no CAR active and hence triggered a cache invalidate. This change fixes the above issue by returning 1 for car_active if ENV_CACHE_AS_RAM is set even if global migration is not required. BUG=b:109717603 TEST=Verified that board reset does not trigger cache invalidate in verstage and does not result in board hang. Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Nick Chen <nickchen@ami.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-09drivers/*/tpm: Add postcar targetPhilipp Deppenwiese
Now postcar is a standalone stage, add it as target to all TPM bus drivers. This is a required for a measured boot. Change-Id: I758185daf3941a29883c2256b900360e112275e1 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/29546 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-09include/program_loading: Add POSTCAR prog typePhilipp Deppenwiese
Now postcar is a standalone stage give it a proper type. Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/29545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-09intel/i945: add timestamps in romstagePatrick Georgi
It is able to do so if timestamps are initialized. Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/27330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-09mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 msChris Wang
Add 20ms adjust timing for edp panel in devicetree. BUG=b:118011567 TEST=verify panel sequences by ODM. Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29473 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-09mb/google/kahlee: Tune eDP panel initialization timeChris Wang
1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-09mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/icelake Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-11-08mb/google/sarien: Set runtime IRQs to reset on PLTRSTDuncan Laurie
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ strom after S3 resume. For sarien/arcada these are all runtime IRQs only, not wake capable. Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/sarien: Disable eSPI when ACPI is enabledDuncan Laurie
Select the option to disable eSPI when ACPI is enabled so the EC is unable to assert an SMI when booted into the OS. There is a kernel driver that implements the same mailbox interface so it cannot also be used by the SMI handler. Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08soc/intel/common: Add option to disable eSPI SMI at runtimeDuncan Laurie
Add an option that will disable eSPI SMI when ACPI mode is enabled, and re-enable eSPI SMI when ACPI mode is disabled. Additionally it ensures eSPI SMI is disabled on the ACPI OS resume path. This allows a mainboard to ensure that the Embedded Controller will not be able to assert SMI at runtime when booted into an ACPI aware operating system. This was tested on a Sarien board with the Wilco EC to ensure that the eSPI SMI enable bit is clear when booted into the OS, and remains clear after resume. Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mediatek/mt8183: Add DDR driver of write leveling partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-08mediatek/mt8183: Add DDR driver of cmd bus training partHuayang Duan
BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-08mediatek/mt8183: Add DDR driver of pre-calibration partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28838 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08security/vboot: Add selection for firmware slots used by VBOOTPhilipp Deppenwiese
Make the firmware slot configuration in VBOOT selectable. The following three modes are available: -RO only -RO + RW_A -RO + RW_A + RW_B The mode "RO only" is the lowest mode with no safety during update. You can select either RW_A or RW_AB via Kconfig which will add the selected parttions to the final image. Change-Id: I278fc060522b13048b00090b8e5261c14496f56e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/27714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-08nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macrosElyes HAOUAS
Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-08src: Replace common MSR addresses with macrosElyes HAOUAS
Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-11-08nb/intel/gm45: Use macro instead of magic numberElyes HAOUAS
Change-Id: I5caa6163e5471feda170600c21320821f4286c65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-08soc/intel/skylake: Add PCH sku id's supported for KBLPraveen hodagatta pranesh
This patch also add new SKL PCH-H device id's in soc platform reporting and common lpc driver. BUG=None TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id in serial logs. Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 00:05:15 +0000