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2023-01-17soc/intel/meteorlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. BUG=b:261800015 Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found' lists all stages. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6a49f88aff07841d105cd3916086aa9e496654c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71921 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17mb/google/marasov: Skip MBP HOB creation to save boot timeSubrata Banik
This change skips the MBP HOB creation since coreboot doesn't use it and also helps to reduce the boot time by ~10msec. Boot time data: Before: * 955:returning from FspSiliconInit 897,278 (33,603) After: * 955:returning from FspSiliconInit 864,543 (21,273) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia97cca560869fcfd55e65c2e1719cceec6f3ab7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71873 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-17mb/starlabs/starbook/adl: Fix alignmentSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-16soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file and use this definition in the mainboard code, so port this back to Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-16Revert "mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD"Martin L Roth
This reverts commit 0e945a3426782e3c054a920ff8be3cd865f697ba. Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the register that this patch enables Signed-off-by: Martin L Roth <gaumless@gmail.com> Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-16mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-16commonlib/storage: Add common eMMC functionsShelley Chen
Now that multiple platforms are trying to initialize eMMC in coreboot instead of depthcharge, lets move common functionality into commonlib instead of copying the same functionality between multiple platforms. Note for consistency, changed name of set_early_mmc_wake_status() to mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function for retrieving the Operating Conditions Register (OCR) contents. BUG=b:218406702 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage flash onto villager device and make sure still boots ChromeOS Change-Id: Id00535b05bbd379081712601ef10e762c1831747 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15mb/bostentech: Update name in KconfigMartin Roth
The Bostentech mainboard appears out of order - this can be fixed either by renaming the mainboard to start with S, or by the simpler method used here by putting the mainboard directory name as the main name, then noting that the full name is "Shenzhen Bostrontium Teng Technology". Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I31b4c663b68cdcde2d175f080f011f2998e56074 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-15soc/intel/apollolake/pmutil.c: Fix smi_sts_bits[HSMBUS_SMI_STS_BIT]Elyes Haouas
Found using -Woverride-init command option. Change-Id: I9f0755de9fae678fc5d78a709453fd1098d70e50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-15soc/intel/xeon_sp/Kconfig: set up HPET_MIN_TICKSTim Chu
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3256c3c6a4ea331efae00d78192355a1fd78d6d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-15soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOADTim Chu
MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL MSR at a late BS_PAYLOAD_LOAD boot state. This MSR is in platform scope and must only be locked once on each socket. Add a spinlock to do so. Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-15soc/amd/mendocino: PSP_INCLUDES_HSPKarthikeyan Ramasubramanian
Select HSP config to indicate that the SoC includes Hardware Security Processor. This will allow PSP verstage to get and report the HSP state. BUG=None TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify that HSP is reported during the boot sequence. Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15soc/amd/common/psp_verstage: Report HSP Secure StateKarthikeyan Ramasubramanian
Get Hardware Security Processor(HSP) state in PSP Verstage through the SVC call and report it in cbmem logs. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Change-Id: Ic4875d1732f22783a90434329188192b106168f4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure StateKarthikeyan Ramasubramanian
Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15soc/amd/mendocino/include/acpi,lpc: remove TODO after reviewFelix Held
Remove TODO comment after checking against Mendocino PPR #57243, rev 3.02. BUG=b:263563246 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e35f4c68ec09304eb892888759c7e5ef3dd0ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/71911 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15mb/google/skyrim/var/winterhold: Update USB port A0 settingEricKY Cheng
Update USB port Type-A Port A0 setting. BUG=b:261650602 TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command. Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-01-15mb/google/brya/var/marasov: Update Aux settingsFrank Chu
Follow hardware design to correct aux setting on USB-C ports to fix DP monitor can not output data through type-C port 0 USB-C port 0 did not have retimer. USB-C port 1 have retimer. USB-C port 0 AUX_DC_P connect to GPP_E22. USB-C port 0 AUX_DC_N connect to GPP_E23. BUG=b:263212450 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage DP monitor display normally Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15mb/google/skyrim/var/winterhold: Update I2C bus0 settingsDtrain Hsu
Update settings for touchpad I2C frequency and data hold time. I2C frequency and data hold time need to meet touchpad spec. - I2C frequency: 380kHz - 400kHz - Data hold time: 0.3us - 0.9us BUG=b:262320419 TEST=On winterhold, touchpad i2c measurement from vendor, Frequencies: 395 kHz, Data hold time: 0.66 us Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15drivers/uart/acpi: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. This mirrors the change made for drivers/i2c/generic. TEST=untested, as no boards selected this option. Change-Id: Icb60502a4a7c5e7a1fcf1ee60e23c77e00d6de7b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71851 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15drivers/spi/acpi: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. This mirrors the change made for drivers/i2c/generic. TEST=untested, as no boards selected this option. Change-Id: I4f95d0e453d89b7e1978d3efac304518304495d1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71850 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15soc/intel/common: Use 'enum cb_error' valuesSridhar Siricilla
The patch uses 'enum cb_error' values as return values for below functions: 1. cse_get_rw_rdev() 2. cse_erase_rw_region() 3. cse_write_rw_region() 4. cse_locate_area_as_rdev_rw() 5. cse_get_target_rdev() 6. cse_copy_rw TEST=Build, boot and perform CSE downgrade test on the Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9c664430a5015d37b9c329f85886f8622deaa497 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/common: Use 'enum cb_err' valuesSridhar Siricilla
The patch uses cb_err enum values as return values for function cse_get_boot_performance_data() instead of true/false. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I0153d5496c96fb0c2a576eef1fe2fa7fa0db8415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/common: Use enum cb_err valuesSridhar Siricilla
The patch uses cb_err enum values as return values for below functions: 1. cse_hmrfpo_enable() 2. cse_boot_to_ro() 3. cse_prep_for_rw_update() 4. cse_sub_part_get_target_rdev() 5. cse_get_sub_part_fw_version() 6. cse_prep_for_component_update() Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I1bdb7d6b2051a69f1021673d464bfad63dd39431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-14drivers/intel/i210/Makefile.inc: Fix "No such file or directory" errorElyes Haouas
Fix: cc1: error: src/drivers/intel/i210: No such file or directory [-Werror=missing-include-dirs] Change-Id: I94b0f99353ed3a582ea590cbc6b12dec6294c75d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-14commonlib/storage: fix int-to-pointer-cast errorShelley Chen
When pulling in commonlib/storage/pci_sdhci.c into herobrine, am seeing an "error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]", so fixing that. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Make sure that we can build without errors Change-Id: Ib1718f156708a619f7eeb181e19b1a8c620de1f8 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71828 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-13vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3503.00Bora Guvendik
The headers added are generated as per FSP v3503.00 BUG=b:261159242 BRANCH=firmware-brya-14505.B TEST=Boot to OS Cq-Depend: chrome-internal:5318308, chrome-internal:5318129 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2023-01-13soc/amd/phoenix: update mmconf base address and sizeRitul Guru
0xF8000000 was taken from old platform during phoenix porting, updating it to 0xE0000000 to make room for 256 pci busses which is required for usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256 busses are used. Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/glinda: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I62b15d59cc4a5f214e45c3995f651228b1ae6ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71900 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/phoenix: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/mendocino: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief1e9c6d6fa0889b947863837bedb2fbdf3120c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71878 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/cezanne: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9f1b71a5f8b2776c8b338351b2cca723d00598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71877 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/picasso: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedd99cfb64809c4e111e0931c2260981f465035b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd: introduce common SMU S3/4/5 entry message codeFelix Held
The smu_sx_entry function is identical for all AMD SoCs, so introduce it as common code that can be selected to be included in the build via the SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific difference in this function is the ID of the SMC_MSG_S3ENTRY message which is defined in each SoC's soc/smu.h include file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13mb/google/skyrim: remove morthal variantMartin Roth
Morthal has been overcome by events. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13soc/amd/glinda: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/phoenix: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13mb/lenovo/t520: Disable SATA2 and Thermal on W520Angel Pons
If a discoverable device (e.g. a PCI device) does not appear in the devicetree (typically because it is removable), coreboot enables it by default. Disable the SATA2 (device for SATA ports 4 and 5, which is not used in AHCI mode) and Thermal devices on W520 as well. Both devices were only disabled on the T520. Tested, this change fixes a long boot time when using MrChromebox's edk2 payload on the W520, likely related to the following errors: AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 0 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 1 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 2 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 3 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 4 Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13mb/lenovo/t520: Also disable PCI bridge on W520Angel Pons
As per Kendo3-WS schematics, the conventional PCI bridge is not used. Change-Id: Ic3aa11cc3a3028c31b06ad8f74875db8c5626a89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71856 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-13soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-13vc/siemens/hwilib/Makefile.inc: Fix "No such file or directory" errorElyes Haouas
Fix: cc1: error: src/vendorcode/siemens/hwilib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I0e805ead90dddbee3ba3577d119e465f669231ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-13drivers/i2c/pca9538/Makefile.inc: Remove unused pathElyes Haouas
Change-Id: I435837381a966b61081d023447a6e7fdfd9a9348 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13mb/system76/adl-p: Enable AER on CPU PCIe RPTim Crawford
Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - Drive is functional and has no unrecoverable errors on boot - Drive is functional and has no unrecoverable errors after S0ix Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-13mb/system76/adl-p: Add CPU PCIe RP RTD3 configsTim Crawford
Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - System still asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` still increases after suspend Change-Id: I919d75cb2a88c0d623c46e44c506ec2d85567995 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-13drivers/intel/i210.h: Remove 'extern' from declarationArthur Heymans
"extern" is always implied with function declarations. Also remove the comment as the linker will just tell you the same if a definition is missing. Change-Id: I53679ab57981790f82affb46a006281b348af574 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71869 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-13mb/msi/ms7d25: Add support for DDR5 variantMichał Żygowski
The DDR5 board is almost identical to the DDR4 one. The only major difference is the board's DDR5 memory design. TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory: Crucial CT8G48C40U5.M4A1 in all 4 slots. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-01-13security/vboot: Check RW_NVRAM at buildtimeArthur Heymans
This avoids runtime failures of lacking a RW_NVRAM section in fmap or one having a size too small. Change-Id: I3415bd719428a23b21210eb2176dbe15fa44eb9c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71868 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-01-13soc/intel : Use 'enum cb_err' valuesSridhar Siricilla
Use 'enum cb_err' values for below cse lite functions instead of true or false. Functions whose return values updated in this patch: 1. cse_set_next_boot_partition() 2. cse_data_clear_request() 3. cse_set_and_boot_from_next_bp() 4. cse_boot_to_rw() 5. cse_fix_data_failure_err() TEST= Do boot test on Gimble. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7fec530aeb617bab87304aae85ed248e51a6966b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13soc/intel: Use 'enum cb_err' instead of boolSridhar Siricilla
The patch uses 'enum cb_err' values as return values for cse_get_bp_info() function. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I900e40b699de344f497e61d974bca3fee7f6ecbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13mb/google/brya/var/omnigul: Update GPIO settingsjamie_chen
Configure GPIOs based from EE. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I5cfaa8fce6df7f09b744fb3e0b7b1d5b6acdc79b Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-12soc/amd/mendocino: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/cezanne: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/common/fsp: Introduce SOC_AMD_COMMON_FSP_PRELOAD_FSPSFred Reitberger
The function to start preloading the fsp-s is identical in cezanne and newer socs, so move it to common with a new Kconfig option to enable it. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia572c99928f4a60896b7a861ab6fb3f1257ac1cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino/include/soc/southbridge.h: Use BIT macro for consistencyFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2dd17774b79c5adb64c2575ac55dec476c434842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71843 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id517ce6e5f5bee5deffe509d748b16be0eefca96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-01-12soc/amd/mendocino/include/platform_descriptors: remove TODO after reviewFelix Held
This header file is correct for Mendocino, so remove the TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85b47491863bff731b86cf0523253cb547dbb76a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71794 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/mediatek/common/mcu.c: Use 'enum cb_err' instead of 'int'Elyes Haouas
mtk_init_mcu() function already returns enum cb_err. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I562bfbdc5c917a17ce1aa656046b69eb56dce48c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-12soc/intel/common: Use enum csme_failure_reasonSridhar Siricilla
The patch updates return type for below functions as they uses 'enum csme_failure_reason' type return values. 1. cse_sub_part_trigger_update() 2. handle_cse_sub_part_fw_update_rv() 3. cse_sub_part_fw_update() TEST=Build coreboot code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43bc2d518a275894860e4d3c930c3c4d9685fb3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71792 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/skylake/Makefile.inc: Remove path to non-existent directoriesElyes Haouas
Fix: cc1: error: 3rdparty/blobs/mainboard/asrock/h110m: No such file or directory [-Werror=missing-include-dirs] cc1: error: 3rdparty/blobs/mainboard/acer/aspire_vn7_572g: No such file or directory [-Werror=missing-include-dirs] ... Change-Id: Icc43e40514a12944fa180197ffe3230ff9800de9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12soc/intel/braswell/Makefile.inc: Remove path to non-existent directoriesElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I420b60341dfd0119b14e8492722af62e49fceff8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12vc/eltan/security/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/intel/jasperlake_rvp/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I5fee0053ab0281b713c33dbc5862c1d4587e854e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/intel/elkhartlake_crb/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1c6f6d99cfb3bc08966d662282c023e22e111f90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12treewide: Remove unused <cpu/x86/smm.h>Elyes Haouas
Change-Id: Iba5b39c6189d3224ba209c7985153701fe8896fb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12treewide: Remove unused <cpu/amd/mtrr.h>Elyes Haouas
Change-Id: Ibff33c08a1d583b19b205a66d5a4267df65ced75 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/google/skyrim/var/markarth: Update devicetree settingJohn Su
Update devicetree based on the schematic_20230105. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-123rdparty/amd_blobs:Advance submodule pointerJason Glenesk
This picks up the following changes: acf73954 phoenix: rename morgana to phoenix a2c15297 mendocino: Upgrade SMU to 90.35.166 28983855 Update Picasso FSP binaries This also updates the phoenix fw.cfg file that points to the submodule. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block/early_graphics: Introduce a 200 ms delayJeremy Compostella
It has been reported that the PEIM graphics driver may temporarily fail communication with the display if the time between libgfxinit turning off the displays and the PEIM driver initialization is too short. 200 ms has been identified as a safe delay. This is a temporary workaround and an investigation is in progress to come up with a better and long term solution. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is systematically seen Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/alderlake: Inform user of memory trainingJeremy Compostella
If memory training is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. Memory training can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On screen text message during MRC training observed on skolas Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
2023-01-12soc/intel/alderlake: Add romstage early graphics supportJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Verify that VGA text mode is functional in romstage Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12drivers/intel/gma: Enable Alder Lake libgfxinit supportJeremy Compostella
This CL requires the following libgfxinit patches: - https://review.coreboot.org/c/libgfxinit/+/65087 - https://review.coreboot.org/c/libgfxinit/+/65178 - https://review.coreboot.org/c/libgfxinit/+/67489 - https://review.coreboot.org/c/libgfxinit/+/65140 - https://review.coreboot.org/c/libgfxinit/+/67490 - https://review.coreboot.org/c/libgfxinit/+/67491 - https://review.coreboot.org/c/libgfxinit/+/67492 - https://review.coreboot.org/c/libgfxinit/+/67493 - https://review.coreboot.org/c/libgfxinit/+/67494 - https://review.coreboot.org/c/libgfxinit/+/67495 - https://review.coreboot.org/c/libgfxinit/+/67496 - https://review.coreboot.org/c/libgfxinit/+/67497 - https://review.coreboot.org/c/libgfxinit/+/67498 - https://review.coreboot.org/c/libgfxinit/+/67499 - https://review.coreboot.org/c/libgfxinit/+/67500 - https://review.coreboot.org/c/libgfxinit/+/67800 - https://review.coreboot.org/c/libgfxinit/+/67801 - https://review.coreboot.org/c/libgfxinit/+/67802 - https://review.coreboot.org/c/libgfxinit/+/69341 BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit is compiled with the Alder Lake configuration Change-Id: I2de94556f8105447788aaa02340ad669fb68ca0c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70301 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block: Add Intel VGA early graphics supportJeremy Compostella
This patch introduces an early graphics driver which can be used in romstage in cache-as-ram mode. The implementation relies on `libgfxinit' and provide VGA text mode support. SoCs wanting to take advantage of this driver must implement the `early_graphics_soc_panel_init' function to set the panel power sequence timing parameters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Graphics bring up observed on skolas with extra patches Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/brya: Enable eNEM support for Tanik and SkolasSubrata Banik
TEST=Able to build and boot Google/Tanik and Skolas to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a21122dbc324d3a396e8934e21d42f471cdb0bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11mb/siemens/mc_ehl1: Enable real-time tuningWerner Zeh
Enable the real-time tuning to improve performance in the real-time environment for this mainboard. Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11soc/intel/elkhartlake: Provide a way to enable real-time tuningWerner Zeh
Intel provides a Real-Time Tuning Guide for Elkhart Lake to improve real-time behaviour of the SoC (see Intel doc #640979). It describes, amongst knobs for the OS, a couple of firmware settings that need to be set properly to reduce latencies in all the subsystems. Things like clock and power gating as well as low power states for peripherals and buses are disabled in this scenario. This patch takes the mentioned UEFI parameters from the guide and translates them to FSP-M and FSP-S parameters. In addition, a chip config switch guards this tuning which can be selected on mainboard level if needed. When this real-time tuning is enabled, the overall system performance in a real-time environment can be increased by 2-3%. Change-Id: Ib524ddd675fb3ea270bacf8cd06cb628e895b4b6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-11soc/intel/meteorlake: Move ME firmware status register structures toDinesh Gehlot
pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/rex Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib3dafd6c030c0c848aa82b03bb336cc8fad14de3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71627 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11soc/intel/alderlake: Move ME firmware status register structures toDinesh Gehlot
pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic14305b0479a8c57531d9930946eded7ac518b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71625 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11src/sbom/Makefile.inc: Remove quotes on CONFIG_SBOM_ pathsMaximilian Brune
Make will not find the build targets unless quotes are removed. Change-Id: Iddf4e0cd8a11eaf327d6f55baf38a30c566d0f28 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71519 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11device/Kconfig: Fix selection of software connection managerMartin Roth
The patch that introduced the selection of software connection manager, CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM) added a default to enable the software configuration manager directly in the choice. This leads to warnings when running make menuconfig: src/soc/intel/alderlake/Kconfig:439: warning: defaults for choice values not supported src/soc/intel/meteorlake/Kconfig:337: warning: defaults for choice values not supported src/soc/intel/tigerlake/Kconfig:299: warning: defaults for choice values not supported I'm not sure why the Kconfig linter didn't catch this, but this issue is currently breaking the build for me. This patch fixes it so that instead of setting the default directly, a new Kconfig value is selected that then sets the default correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I674046a93af8f7c2f3003900804deefa89dae295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-11ec/google/chromeec: Add retimer flag for mux devicePrashant Malani
Not all ports have retimers. Add a property to denote that a particular port has a retimer (instead of assuming that all ports have retimers). BUG=b:263964979 TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when device tree is updated accordingly. Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71663 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11security/tpm/tspi/log.c: fix strncpy() usageSergii Dmytruk
Change-Id: Ib24129829bef3764a8ba1e2c0d92bc42c5cfbc8d Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11security/tpm: make tspi/crtm.c agnostic to log formatSergii Dmytruk
Change-Id: I3013bd5f29f1412fbe646dc74d8946704b750a66 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11mb/google/geralt: Use BOE_TV110C9M_LL0 as default mipi panelBo-Chen Chen
We will use BOE_TV110C9M_LL0 for geralt proto board, so update the panel setting. BUG=none TEST=emerge-geralt coreboot; see panel-BOE_TV110C9M_LL0 in coreboot.rom Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I28e9dd87350b55fdc609dd2c562c5a2ad578187c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71786 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/geralt: Keep booting even if MIPI panel not foundBo-Chen Chen
We should keep booting even failed to get the MIPI panel. BUG=none TEST=emerge-geralt coreboot; Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I39d9e04e5908f669ae2a1a8ce8858b93cae20654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71785 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 389 kHz Change-Id: Ie9efd4e597e2701c98064185e5b39a6e256a5f1c Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71772 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-01-11drivers/ocp/vpd: add get_cxl_mode_from_vpd()Johnny Lin
cxl_mode VPD variable supports 3 modes: CXL_DISABLED, CXL_SYSTEM_MEMORY and CXL_SPM. Change-Id: Ib3bf85fbe687680db3c11efa908c4fb351be9c44 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11soc/intel/xeon_sp: Setup DPR for all VT-d devicesJonathan Zhang
The Data Protected Range (DPR) needs to be set for all DPR devices, not only the root device. Separate the setup from the memory resource map reservation. Change-Id: I7e49db23960e3938e8e158082be3c5ecf3cf95f3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11soc/intel/{alderlake,tigerlake}: Fix typo in gpio_defs.hJakub Czapiga
Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ define name. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-11drivers/intel/gma: Hook up libgfxinit in romstageJeremy Compostella
A mainboard port needs to: - select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage (and ramstage) for the graphic device. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit compiles in romstage. libgfxinit successfully executes in romstage and ramstage using the requested MMIO setting on skolas. Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11soc/intel/meteorlake: Define SA_DEV_IGD for common codeJeremy Compostella
SA_DEV_IGD is used by the early graphics feature implemented by the Intel common block. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Compilation Change-Id: Ic9f0fe1683d55a53c705ae717fe9e40fd8873d1f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11soc/intel/elkhartlake/chip.h: Include types.h instead of stdint.hWerner Zeh
As the used 'bool' type is defined in stdbool.h, include types.h (instead of stdint.h) which includes all needed header files. Change-Id: I3f75776575a7a5f70484411b9f3458530f706ec4 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71790 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/intel/mtlrvp: Configure USB devices for MTL-RVPHarsha B R
This patch adds OC configuration of USB devices for MTL-RVP as per MTL-RVP design specification, USB 2.0 usb2_ports0 -> OC0 usb2_ports1 -> OC0 usb2_ports2 -> OC0 usb2_ports3 -> OC0 usb2_ports4 -> OC0 usb2_ports5 -> OC0 usb2_ports6 -> OC_SKIP usb2_ports7 -> OC_SKIP usb2_ports8 -> OC_SKIP usb2_ports9 -> OC_SKIP USB 3.2 Gen 2x1 usb3_ports0 -> OC0 usb3_ports1 -> OC0 TCPx tcss_ports0 -> OC0 tcss_ports1 -> OC0 tcss_ports2 -> OC0 tcss_ports3 -> OC0 BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS (on top of CB: 66190). Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-11mb/google/nissa/var/craask: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:263920313 TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned fw_config and fw_config set correctly. Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/nissa/var/yaviks: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:251055188 TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned fw_config and fw_config set correctly. On UFS SKU with fw_config set, eMMC no longer shows up in lspci. (On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan so there's no change in behaviour.) Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/brya/var/omnigul: Add memory parts supportAmanda Huang
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) Samsung K3KL8L80CM-MGCT 2) Hynix H58G56BK7BX068 3) Micron MT62F1G32D2DS-026 WT:B 4) Micron MT62F512M32D2DR-031 WT:B BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I699070596a77c975254660a1ba74b0f40026186d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 13:01:07 +0000