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2023-02-13soc/qualcomm/sc7280: Add support to configure 6bit color depthVinod Polimera
Some of the eDp panels use 6bit color depth as default. Set the default color depth configuration to 6 bit when there is no match with the supported color depths. BUG=b:255870643 TEST=Validated on sc7280 Zombie development board Change-Id: I2cea10ad417a05f020e4c418f15212fee06a2369 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72744 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/qualcomm/sc7280: update intf timing parameter calcualtion for eDPVinod Polimera
Correct the interface timing parameter calculation for eDP interface to avoid writing into the blanking region. BUG=b:255870643 TEST=Validated on sc7280 Zombie development board Change-Id: I069ca351d8c60d071debb23a5e48840701441977 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72743 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOCJonathan Zhang
Some FSPs (such as SPR-SP FSP) support SOC_INTEL_PCIE_64BIT_ALLOC. In such case, is_pci64bit_alloc() return 1. Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72441 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-12drivers/smmstore: Expose region devicePatrick Rudolph
Allow other drivers to use the SMMSTORE region device. Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-11soc/amd/*/Makefile.inc: remove command line soc-nameZheng Bao
The function has already moved to fw.cfg. 4/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Idf9e491ed46ae574ccd17f24925e3e5c595039fa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-11soc/amd/*: Add SOC_NAME in fw.cfg(s)Zheng Bao
2/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: I18f73462a3995038fe93750320dfc053fec969ba Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-10acpi/acpigen: use acpigen_write_store_* in acpigen_write_romFelix Held
Use existing functions instead of open-coding the same functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie35c7e0fd3caa25b0d3d02443609e54dd2fdcb7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-10acpi/acpigen: add acpigen_write_store_namestr_to_namestrFelix Held
acpigen_write_rom open-codes this functionality, so add a function for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief25dd854d1639a295c021e9d02c05b4cc61109c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-10acpi/acpigen: use acpigen_write_if_lgreater_* in acpigen_write_romFelix Held
Use existing functions instead of open-coding the same functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I660bd5d357eb86c19a5a7847925f6176c3fb4425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-10mb/google/brya/var/brya0: add RPL 28W dptf settingsSumeet Pawnikar
Add Raptor Lake (RPL) 28W dptf settings for Brya0 BUG=b:235311241 BRANCH=firmware-brya-14505.B TEST=Built and tested on brya Change-Id: I5d06c1ace5b481012ea39f2a57570eb6330479cb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/skolas: add RPL 28W dptf settingsSumeet Pawnikar
Add Raptor Lake (RPL) 28W dptf settings for Skolas BUG=b:235311241 BRANCH=firmware-brya-14505.B TEST=Built and tested on skolas Change-Id: I4364ca6a50906c2a6dd0e754238264c680e7ebd0 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-10mb/google/brya/var/brya0: update PL1 minimum valueSumeet Pawnikar
Update Power Limit1 (PL1) minimum value to 15W based on the Brya design. BRANCH=firmware-brya-14505.B BUG=b:235311241 TEST=Built and tested on Brya system Change-Id: Ifd5256221b82eae2cfe8009918f8ff4791751b4d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72868 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/skolas: update PL1 minimum valueSumeet Pawnikar
Update Power Limit1 (PL1) minimum value to 15W based on the skolas design. BRANCH=firmware-brya-14505.B BUG=b:235311241 TEST=Built and tested on Skolas system Change-Id: I1027ca2bf2323ac959474ee6c38e47fa530113da Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72727 Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/brya0: update dptf thermal settingsSumeet Pawnikar
Update dptf thermal settings as per suggested by thermal team. Control fan based on TSR sensors, not based on CPU sensor temperature which changes too fast. BRANCH=firmware-brya-14505.B BUG=b:235311241, b:261749371 TEST=Built and tested on Brya system Change-Id: I58bc7132086b0776ee191a242bd1302554f3854f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72867 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/brya/var/skolas: update dptf thermal settingsSumeet Pawnikar
Update dptf thermal settings as per suggested by thermal team. Control fan based on TSR sensors, not based on CPU sensor temperature which changes too fast. This change is based on the discussion on bug:235311241 comment#7. BRANCH=firmware-brya-14505.B BUG=b:235311241, b:261749371 TEST=Built and tested on Skolas system Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71692 Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-02-10mb/google/skyrim: Disable keyboard resetMartin Roth
The keyboard reset is not being used on this board, so disable the functionality. BUG=None TEST=Check register values Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4a9f8f254dfefcb32a77f558f984bcdd6004d34b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72913 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10soc/amd(MDN/PHX/Glinda): Update DISABLE_KEYBOARD_RESET_PIN helpMartin Roth
For MDN, PHX, & Glinda platforms, the Keyboard Reset functionality has been moved from GPIO 129 to GPIO 21. Additionally, the issue where the system would reset when the KBDRST_L pin went low even when not configured for Keyboard reset seems to have been fixed, so remove that text. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iefe7e00d63777577b59ee98cb974b07afea1fd12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72912 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10soc/amd/common/gfx: add support for VBIOS caching, selective GOP initMatt DeVillier
One of the main functions performed by the FSP GOP driver is to modify the ATOMBIOS tables (part of the VBIOS) in memory based on the display output configuration. This device-specific modified VBIOS can be cached in a FMAP region specific for that purpose, then loaded into memory instead of the "generic" VBIOS, saving the ~130ms execution time of the GOP driver. As this approach only works when no pre-OS display output is needed, limit its use to ChromeOS builds, with the GOP driver enabled, and not booting in either recovery or developer modes. SoCs supporting this feature will need to selectively run the FSP GOP driver as needed, using the same criteria used here to determine whether to load the VBIOS from CBFS or from the FMAP cache. Boards utilizing this feature will need to add a dedicated FMAP region with the appropriate name/size, and select the required Kconfig options. BUG=b:255812886 TEST=tested with rest of patch train Change-Id: Ib9cfd192500d411655a3c8fa436098897428109e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-02-10soc/intel/common/block/fast_spi: Add SPI BIOS decode lockTim Chu
The SPI BIOS decode lock bit needs to be set, according to Intel EBG EDS dodcumentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3366817b42a5878f16575698ebc546fa7852e285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-10soc/intel/{common, meteorlake}: Add support for new MCHSridhar Siricilla
The patch adds support for new Meteor Lake MCH (ID:0x7d16). TEST=Build and boot the system having MCH ID:0x7d16. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-10mb/intel/mtlrvp: Enable DPTF functionality for mtlrvp boardSumeet Pawnikar
Enable DPTF functionality for Meteor Lake based mtlrvp board BRANCH=None BUG=None TEST=Built and booted on mtlrvp board Change-Id: I8d3e1cd43cf67c3f2081be339589a6da358b668c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10drivers/fsp2: Don't print garbage if the FSP signature doesn't matchFred Reitberger
Using a &uint64_t as a string argument does not include the required NULL character termination. Update the format string to only print the 8 desired characters and not continue printing stack memory until a NULL is found. Before: [EMERG] Invalid UPD signature! FSP provided "AMD_01_M;....`", expected was "CEZANE_MAMD_01_M;....`". After: [EMERG] Invalid UPD signature! FSP provided "AMD_01_M", expected was "CEZANE_M". Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib334daa8518a92e0cf3d22c4d95908f4c84afe04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72911 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-10mb/google/poppy/rammus: Fix NHLT initMatt DeVillier
Commit bf3c648fa7f6 ("soc/intel/skl; mb/google/eve,poppy: Update NHLT methods") contained a copy/paste error for rammus, swapping the max98373 entry for the correct max98927 one. Change it back. TEST=build/boot Windows on rammus, verify audio functional with coolstar's AVS audio drivers. Change-Id: Ibcd4b752e01866a3dd54997f1d2a6c079b07b7a3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/volteer/drobit: Add missing TBT devicetree entriesMatt DeVillier
Commit ae20d4c78f9f ("mb/google/volteer: Fix USB4 enabling for volteer family") reworked the USB4/TBT config for volteer, but drobit variant was missed for some reason. Add the missing USB4/TBT entries. TEST=build/boot Windows on drobit, verify USB4/TBT functional. Change-Id: I43d771eeaf29b4e141b222ccb05af5cb7ceedc6f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/hatch/kohaku: Fix touchscreen power sequencingMatt DeVillier
Commit 525c61f74e94 ("mb/google/hatch: Implement touchscreen power sequencing") contained a copy/paste error; KOHAKU's enable GPIO is set twice in ramstage, and the reset GPIO not at all, leading the touchscreen to not be detected. Correct the copy/paste error by replacing the 2nd instance of GPP_C12 with GPP_D15. TEST=build/boot Windows/Linux on KOHAKU, verify touchscreen works. Change-Id: I08d35f1e2a951cdaa463daa34df2134fdc8c65c8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/drallion: Add VBT, ACPI brightness controlsMatt DeVillier
Enables display backlight control under Windows. VBT extracted from stock ChromeOS firmware Google_Drallion.12930.543.0. TEST=build/boot Win11 on drallion, verify OS backlight control available and functional. Change-Id: I85065f22b825a7616fa4ac632c42ae7972091e24 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10mb/google/volteer/eldrid: Fix touchscreen under WindowsMatt DeVillier
Under Win11, a longer delay after asserting reset is needed for the Goodix touchscreen to init properly. Increase the reset delay to match that used for the Goodix touchscreen by other volteer variants (120ms). TEST=build/boot Win11, Linux on eldrid variant with Goodix touchscreen, verify functional. Change-Id: I489f037f0bbade9567aad2ad64404a5ac66965d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10drivers/vpd: Demote FMAP not found printk from error to warnMatt DeVillier
Not all firmware which uses VPD uses both RO and RW regions, so either one not existing is not necessarily an error. Change-Id: I50f43a25ee24a642c39e2f0b52de2d4fef023f3b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72476 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10drivers/net/r8168: Demote MAC lookup printk from error to warnMatt DeVillier
Some older devices use the vpd key 'ethernet_mac' vs 'ethernet_mac0' for the first/only LAN NIC, so don't treat the key lookup as an error. If no MAC is able to be found, another error will be printed later in the driver init. TEST=build/boot google/fizz, dump cbmem log, verify 'ethernet_mac0' lookup failure printk output at warning level. Change-Id: If5226f4686a819a7020fd14f130181420ee1462b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10mb/google/brya/var/constitution: Add SOLDERDOWN supportMorris Hsu
Constitution will use SOLDERDOWN. Add memory.c to override baseboard. Add mem_parts_used.txt and generate dram_id.generated.txt and Makefile.inc Memory: SAMSUNG K4U6E3S4AB-MGCL MICRON MT53E1G32D2NP-046 WT:B BUG=b:267539938 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72775 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10mb/google/brask: Add EC_HOST_EVENT_USB_MUX S0ix wake eventDerek Huang
Add EC_HOST_EVENT_USB_MUX to MAINBOARD_EC_S0IX_WAKE_EVENTS for brask. Without it EC won't send host event to wake AP when USB MUX is changed during S0ix. It's there for brya but missing for brask. BUG=b:267573651 TEST=emerge-brask coreboot Signed-off-by: Derek Huang <derekhuang@google.com> Change-Id: Id08d9aec9ab3566176369f2ca25cd00b9f0a0ca5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-02-10Revert "mb/google/skyrim: Update ASPM settings for the NVMe device"Martin Roth
This reverts commit 8e1bb93fb88bc9cc20aab33a1fe09fb4c0c652a0. Reason: Enabling L.2 breaks some devices on this bridge. Reverting until a workaround is found and additional testing is done. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9f721178244e7764e9b08e419db8a8c05ecc29a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72916 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-02-09nb/intel/haswell: Add 9-series PCH IDsAngel Pons
Change-Id: I5b7b1c218a0e8c8ba713b370622fbc37a1e57097 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-09sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHsAngel Pons
The desktop 9 series PCHs should be the same as the 8 series PCHs. Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-09mb/prodrive/hermes: Hook up wake on USB optionAngel Pons
Hook up the `wake_on_usb` EEPROM setting so that it works as intended. TEST=Keysmash on a USB keyboard, verify Hermes does not wake from S3. Change-Id: I81531b90abae6a62754ea66c47e934e1f440bda2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72906 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09mb/google/skyrim: Configure GPIO 67 as an unused GPIOMartin Roth
GPIO 67 is not currently used on skyrim, so set it as no-connect. Since it's now free for other purposes, make sure that the SPI-ROM-SHARING functionality is disabled. BUG=b:268330591 TEST=Examine registers after change Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id083baf41d25920eca09795453a01aac1d00d0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09mb/google/skyrim: Set system type to laptopMartin Roth
BUG=None TEST=Verify that DMI type 3 - Chassis Information Type field has changed from Desktop to Laptop Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I76c8970fe3fdc2ea322a07f114ad03a0373e152c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72907 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09mb/amd/birman: Improve missing APCB warningFred Reitberger
Move the missing APCB warning to the end of the build and make it stand out better. Prior to this patch, the warning would appear as one of the first build messages and easily be missed due to the rest of the build messages. TEST=build with and without proper APCBs being found, warning message appears only when APCB is not found and stands out more Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iabe32636b8e31fe781519533a329a08535bd661a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held
Instead of having a magic entry in the CPU device ID table list to tell find_cpu_driver that it has reached the end of the list, introduce and use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID instead of the 0 in the CPU_TABLE_END definition. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09src/acpi: add function gen: if_lgreater_ and namestr assignmentCliff Huang
1. add functions to generate if greater than conditions: acpigen_write_if_lgreater_op_op: if (op1 > op2) acpigen_write_if_lgreater_op_int: if (op > val) acpigen_write_if_lgreater_namestr_int: if (namestr > val) 2. add function to assignal value to a namestr acpigen_write_store_namestr_to_op: namestr = val TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72825 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09src/soc/intel/common/block/pcie/rtd3: Fix root port _STA logicCliff Huang
When enable_gpio is used as active low output, the _STA returns incorrect value. Also, simply the logic for _STA method. When enable pin is used for _STA: | polarity | tx value| get_tx_gpio() | State | | active high | 0 | 0 | 0 | | active high | 1 | 1(active) | 1 | | active low | 0 | 1(active) | 1 | | active low | 1 | 0 | 0 | When reset pin is used for _STA: | polarity | tx value| get_tx_gpio() | State | | active high | 0 | 0 | 1 | | active high | 1 | 1(active) | 0 | | active low | 0 | 1(active) | 0 | | active low | 1 | 0 | 1 | Generated _STA method: Ex: for using active low power enable GPIO pin GPPC_H17: Method (_STA, 0, NotSerialized) // _STA: Status { Local0 = \_SB.PCI0.GTXS (0x5C) Local0 ^= One Return (Local0) } TEST=Check the SSDT when booted to OS. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ie6f1e7a5b3e9fd0ea00e1e5b54058a14c6e9e09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72421 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09mb/dell: Add Latitude E6400Nicholas Chin
Mainboard name is Compal JBL00. This is based on the GM45/ICH9M chipset and uses DDR2 RAM. The EC is a SMSC MEC5035 which has internal flash, so there's no issue about making sure to include the EC firmware in the BIOS region. This only supports the variant with integrated graphics only, the version with a discrete Nvidia Quadro NVS 160M is not supported. This port was based on the Lenovo T400 port. Working: - USB EHCI debug (lower USB port on right side) - Keyboard - Touchpad/trackpoint - VGA - Displayport - ExpressCard - Audio - Ethernet - mPCIe WiFi - mPCIe Bluetooth (uses USB) Not working: - Brightness hotkeys - Physical Wireless switch - SD card slot: Linux outputs an "irq 18: nobody cared" message when inserting a card, after which it disables the IRQ Unknown/untested: - Dock - Smartcard (slot and contactless) - Firewire - eSATA - TPM - Battery (my battery is at the end of its lifespan) Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: I516ebbf4390a3f6d242050da8d35dc267b8b3a28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-09amdfwtool: Add SOC family definition for CarrizoZheng Bao
For Carrizo, the soc name was set as UNKNOWN. The change is supposed to be binary unmodified, except the SPI settings. According to the spec, the Stoneyridge and Carrizo have the same definition of SPI setting in EFS. Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09treewide: Remove repeated wordsElyes Haouas
Found by linter Change-Id: I7a49cce0b56cf83d0e4490733f9190284a314c4a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09soc/amd/picasso/soc_util.c: Remove unneeded "break"Elyes Haouas
"break" is useless after "return". Change-Id: I84bc506a3d50e937797f42659299bf90ce392e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09soc/intel/common/block/gpio/gpio.c: Remove unnecessary line continuationElyes Haouas
Also remove unnecessary whitespace before "\n" Change-Id: Ia2c8fcb82658ed3e247759535d3112270d46e65d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09console: Add SimNow console loggingFred Reitberger
The AMD SimNow tool supports fast logging through an IO port. Add a new console to support SimNow logging through port 80. TEST=observe significant speed improvements on SimNow console log Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I42a431f48ea14ba4adacbd4a32e15abe7c5e4951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09mb/google/geralt: Add power-on sequence for BOE_TV110C9M_LL0Rex-BC Chen
For Geralt, we use BOE_TV110C9M_LL0 as MIPI firmware display, so add the power-on sequence for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72749 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-09mb/google/geralt: Init MT6359P only once in ramstageLiju-Clr Chen
The regulator MT6359P is needed by both firmware display and SD card. To avoid duplicate initialization in ramstage, publicize init_pmif_arb() as mt6359p_init_pmif_arb() and call it from mainboard_init(). This would save 13 ms for boot time on Geralt. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72839 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09soc/intel/meteorlake: Remove unsupported hybrid_storage_mode configSridhar Siricilla
The patch removes hybrid_storage_mode variable from soc_intel_meteorlake_config struct since hybrid storage is no longer supported on Meteor Lake platform. TEST=Verify the build for Rex board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/herobrine: Enable early eMMC init in corebootShelley Chen
Move eMMC init from depthcharge into coreboot to remove it from the critical boot path. Doing so saves us almost 35ms on villager: before change: finished storage device initialization 50,783 after change: finished storage device initialization 16,255 BUG=b:254092907,b:218406702 BRANCH=None TEST=flash new FW onto villager and make sure can boot from eMMC Change-Id: I1af1ec162029120332e7f531f75c3780266d322b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/intel/emeraldlake2: Remove unused VBOOT optionYu-Ping Wu
Remove the commented VBOOT_VBNV_CMOS Kconfig option as well as VBOOT for emeraldlake2. BUG=b:235293589 TEST=none Change-Id: Ie583dcf615573784c657b9d220ad417b05704150 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/hp/z220_series: Enable VBOOT_VBNV_FLASHYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for z220_series. [1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1 BUG=b:235293589 TEST=./util/abuild/abuild -t HP_Z220_CMT_WORKSTATION -a \ # with VBOOT enabled and a custom FMDFILE with RW_NVRAM region Change-Id: I1c60a44fb12fd093f45cf54ef2f9e0e02afc80bd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"Felix Singer
This reverts commit d6e04aa00bc5a8912a041a569eb57f6962d1119a. Reason for revert: Breaks master. Change-Id: If7daeaaffe3f9ae9f5e2fbecef5817b9b62827d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72917 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-09mb/google/dedede/var/dibbi: Update gpio tableAmanda Huang
Config GPP_B9 as LAN_CLKREQ_ODL based on latest schematic BUG=265021899 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/brya/var/omnigul: Add SOC I2C configJamie Chen
Add SoC config and .early_init = 1 in I2C1 BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-02-09mb/google/brya/var/omnigul: Modify NVMe and UFS Storage supportJamie Chen
1. Add fw_config:STORAGE_UFS & STORAGE_NVME to switch storage. 2. rp11 off change to on. BUG:b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72090 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/skyrim/var/markarth: Override SPI flash bus speedJohn Su
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz for starting next phase. BUG=b:267539952 TEST=None Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Id46201351780bb5bc05422ff36dad6972285690e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-09mb/google/brya: Create aurash variantZoey Wu
Create the aurash variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263691099 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AURASH Change-Id: I595102778071f822c5cf69ceadeed174e5ea4836 Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72837 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORTSean Rhodes
Add NO_S0IX_SUPPORT for boards that do not support, or do not want to support S0IX. As all the boards in the tree that do this, don't support D3Cold, add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is selected to disable D3Cold support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-08ec/dell: Add support for the SMSC MEC5035Nicholas Chin
This is required to prevent the EC from shutting down the system after about 15 seconds after being turned on. If the EC doesn't receive a command meaning "CPU OK" it assumes that the processor has failed and flashes a diagnostic code on the keyboard LEDs to indicate this. This also enables the keyboard and trackpad/trackpoint interfaces. Parts of this code were derived from yet-to-be merged code in CB:44975 (ec: Add support for MEC5055 for Dell laptops) written by Iru Cai. Tested on a Dell Latitude E6400 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: Ia420cd51e9a64be5eee4af2c0d113618575522b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59703 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08ec/google/chromeec: Update ec_commands.hCaveh Jalali
Update ec_commands.h from the EC repo at: "8b6f7de2a7 fan: update fan stalled value reporting" This is an exact copy of the EC repo's ec_commands.h with the exception of updating the copyright message. BUG=b:258110734 BRANCH=none TEST=built coreboot for brya Change-Id: I4ce15e1af40cc54a6cf2ebd6f5d5adf8953dee60 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08ec/google/chromeec: clang-format ec_commands.hCaveh Jalali
This is a format-only change: Reformat ec_commands.h using clang-format according to the EC repo's current formatting style. The command is: clang-format --style=file:$EC/.clang-format -i ec_commands.h where $EC points to the chromeos EC repo. The EC repo has recently adpoted the practice of formatting all files through clang-format using its own style. So, run ec_commands.h through the EC's clang-format so future updates don't get overwhelmed by inconsequential style changes. BUG=b:258110734 BRANCH=none TEST=built coreboot for brya Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08drivers/ocp, mb/ocp/deltalake: move get_loglevel_from_vpd functionJohnny Lin
Move get_loglevel_from_vpd from mb/ocp/deltalake to driver drivers/ocp/vpd/loglevel_vpd.c. Change-Id: I70af1051f63c527fd8150f5ecbe4765b4aaacd20 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71936 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-08mb/intel/mtlrvp: Enable PCIE Advanced Error ReportingHarsha B R
This patch enables PCI Express Advanced Error Reporting Capability for WWAN, WLAN, and SSD root ports. On enabling PCIE_RP_AER, PCIE device will automatically report (if any error) about the error nature to the corresponding PCIe root port. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Iab8619818e2219b41287b895513eb04b0464401e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-08soc/qualcomm/sc7280: init eMMCShelley Chen
Use common sdhci driver in coreboot to initialize eMMC for sc7280. This should allow us to initialize eMMC earlier in the boot process, taking it out of the critical path. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage Change-Id: Ifa88da500e82b44d7523f2e68763e01399c89f4d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71829 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/qualcomm/common: Add sdhci_msm_init functionShelley Chen
Porting from depthcharge changes for supporting eMMC driver functionality with standard SDHC controller on Qualcomm chipsets. sdhci_msm_init() needs to be run before the standard sdhci_mem_controller initiailzation. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72634 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08commonlib/storage: Add attach callback to sdhci_ctrlrShelley Chen
Adding a attach callback function pointer in case a platform needs to execute anything before the standard initialization of the sdhci mem controller. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I0f37ec09d083922cad5ecd3c47b184cf3311fe2d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2023-02-08soc/amd: use CPUID_FROM_FMS macro instead of magic numbersFelix Held
Port over the remaining AMD SoCs to use CPUID_FROM_FMS. The Glinda CPUID still needs to be updated to the actual CPUID, but for now just change it to use CPUID_FROM_FMS. TEST=Resulting image of timeless build for Gardenia (Stoneyridge), Majolica (Cezanne), Chausie (Mendocino), Mayan (Phoenix) and Birman (Glinda) don't change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia508f857d06f3c15e3ac9f813302471348ce3d89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72862 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/phoenix/soc_util: add get_soc_typeFelix Held
Implement a get_soc_type function to determine if the silicon the code is running on is Phoenix or Phoenix 2. This will for example be needed to provide the correct DXIO descriptor table for the SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f2b668b83432426b04e7f1354b694ddd6c300d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72861 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/picasso/soc_util: use cpuid_matchFelix Held
Now that there is a cpuid_match function, we can use it instead of doing basically the same thing manually. In the functions is_fam17_1x and is_fam17_2x both the stepping number and the lower nibble of the model number are masked out. To avoid having magic constants in the code, introduce the CPUID_ALL_STEPPINGS_AND_BASE_MODELS_MASK definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I758f9564c08c62c747cc4f93a8d6b540a1834a62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72860 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08arch/x86/cpu: move cpuid_match to corresponding header fileFelix Held
Since the functionality of cpuid_match is also useful outside of arch/x86/cpu.c and it's a relatively simple function, move its definition as inline function to the header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic96746b33b01781543f60cf91904af35418e572d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72859 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815Ron Lee
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. This patch add usb_lpm_incapable config for the following variants with PS8815 retimer: - kinox MLB: C0 - volmar DB: C1 - osiris MLB: C0/C1 - mithrax DB: C1 - felwinter DB: C1 - taeko DB: C1 - gimble DB: C1 - gimble4es DB: C1 - taniks DB: C1 - marasov DB: C2 - gaelin MLB: C0/C1 - skolas DB: C1 - skolas4es DB: C1 - brya0 DB: C1 BUG=b:253402457 TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u2 disabled Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Signed-off-by: Ron Lee <ron.lee@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-08mb/google/geralt: Add support for VM18 in regulator.cSen Chu
Add regulator VM18 support to supply power for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I13bafbe10a18a18e253575fd107c9b415f28ef01 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72748 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/mediatek: Add support for regulator VM18Sen Chu
To provide power to MIPI panel BOE_TV110C9M_LL0, add support for regulator VM18. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: Ib8c3b2df1157b23b37492b1e9b1716903ea67799 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72747 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08soc/mediatek: Remove unnecessary !! for boolean variableLiju-Clr Chen
Enable is already a boolean, so the !! is not needed. BUG=None TEST=build pass. Change-Id: I25a7cec632f21a258b8364c82e25b59e55ab7453 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72869 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08mb/google/corsola: Use function to get regulator IDsLiju-Clr Chen
There might be inconsistence between regulator_id[] and `enum mtk_regulator` when we need to add new regulator IDs for Geralt. Therefore, we implement get_mt6366_regulator_id() to get regulator IDs. BUG=None TEST=build pass. Change-Id: I3d28ebf2affe4e9464b1a7c1fb2bbb9e31d64a5e Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72838 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08soc/amd/picasso: use CPUID_FROM_FMS macro instead of magic numbersFelix Held
TEST=Resulting image of timeless build for Mandolin doesn't change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44cb7759206e9e1ce79fd57f62b9a844e52f7394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72857 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08arch/x86/include/cpu: introduce CPUID_FROM_FMS macroFelix Held
Introduce a macro to get the raw CPUID leaf 1 EAX value from a given set of CPU family, model and stepping. The processor type in bits 12 and 13 is assumed to be always be zero; at least this is the case for all CPUIDs that are currently in the coreboot tree. This can be used to make the device values in the CPU device ID tables easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idab77453712b14983b1d02ca365f7924239fc2bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72856 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/stoneyridge/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all family 15h model 60h and 70h steppings. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id05f849d59c04efa9f38dd66892f3cb99d94e3ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/72855 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08cpu/intel/model_206ax/model_206ax_init: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK to only need one CPU device ID table entry per family & model combination and not one per stepping. TEST=Thinkpad x230 with Ivy Bridge stepping 9 CPU still boots with this patch applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46020d5b1b1fba8449c3823fac1369e5670d91c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08soc/amd/phoenix/include/cpu: add Phoenix CPUIDFelix Held
There are multiple Phoenix steppings, but that is now covered by using CPUID_ALL_STEPPINGS_MASK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4eb3502dec5ebdfdbba263b15b34621952d0554 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/glinda/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Glinda steppings once GLINDA_A0_CPUID is updated. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9b8cbb2dc925a8258db6a4eb0d1b00b2745637f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72852 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/phoenix/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Phoenix 2 steppings that might be available in the future. Right now it shouldn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If9878b4687360250cac4cfe1409d5dbad7147cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72851 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/mendocino/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Mendocino steppings that might be available in the future. Right now it shouldn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77ea8c6162667e0a318176e62078b1f57726c10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72850 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/cezanne: use CPUID_ALL_STEPPINGS_MASK to support all steppingsFelix Held
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Cezanne steppings. This adds support for Cezanne stepping A1 and possible future steppings. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb020052685d9369109f391797fdd8f8790a91d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72849 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/amd/picasso/cpu: use CPUID_ALL_STEPPINGS_MASKFelix Held
Use CPUID_ALL_STEPPINGS_MASK to only need one CPU device ID table entry per family & model combination and not one per stepping. TEST=Mandolin with a Picasso APU with PICASSO_B1_CPUID (0x00810f81) still finished mpinit and boots successfully even though now only PICASSO_B0_CPUID (0x00810f80) with CPUID_ALL_STEPPINGS_MASK specified as device match mask. When commenting out the line with PICASSO_B0_CPUID as a negative test, mpinit fails as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I00ba43834ad86ecffa09d60599b17d122acd0b99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72848 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08arch/x86/cpu: introduce and use device_match_maskFelix Held
Instead of always doing exact matches between the CPUID read in identify_cpu and the device entries of the CPU device ID table, offer the possibility to use a bit mask in the CPUID matching. This allows covering all steppings of a CPU family/model with one entry and avoids that case of a missing new stepping causing the CPUs not being properly initialized. Some of the CPU device ID tables can now be deduplicated using the CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72847 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08arch/x86/include/cpu: retype device field in cpu_device_idFelix Held
Use a more specific type in preparation for using bit masks on this field in the next patch. Since uint32_t is a typedef of unsigned int, this won't change behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic54f73dcd3496a5ad85291b9b9586bc740b734d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72846 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabledSean Rhodes
Both Alder Lake and Tiger Lake have Kconfig options for S3, which disables support for D3Cold. Unify these so that they are easier to compare. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/amd/mayan: update EC FW offset in spiromRitul Guru
update EC FW offset location in spirom to 0x81000 For mayan board EC FW is located at offset 0x81000 location, 0th location contains pointer to this EC FW location. Change-Id: I63c797e12ed131e8411c11379f4db9bcc29b49a2 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/common/data_fabric: print decoded control register contentsFelix Held
Since all SoCs define the df_mmio_control union for the bits used in the code, data_fabric_print_mmio_conf can take advantage of that and also print a decoded version of those bits. Output on Mandolin before the patch: === Data Fabric MMIO configuration registers === idx control base limit 0 93 fc000000 febfffff 1 93 10000000000 ffffffffffff 2 93 d0000000 f7ffffff 3 1093 fed00000 fedfffff 4 90 0 ffff 5 90 0 ffff 6 90 0 ffff 7 90 0 ffff Output on Mandolin with the patch: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06e1d3a3e9abd664f59f2bb852394e7f723f2b30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/mendocino/data_fabric: add Rembrandt DF_MMIO_REG_SET_SIZEFelix Held
In contrast to Mendocino and all other AMD SoCs in the coreboot tree, Rembrandt, on which Mendocino is based on, has a DF_MMIO_REG_SET_SIZE of 3 instead of 4, so the next data fabric MMIO register is 3 DWORDs after the last one instead of the 4 DWORDs on the other SoCs. This was checked against PPR #56558 Rev 3.04. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I454ad5d182f0040db93c9b3a83941333392c6061 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/*/data_fabric: introduce and use DF_MMIO_REG_SET_SIZEFelix Held
To be able to handle a special case, add a per-SoC define for DF_MMIO_REG_SET_SIZE instead of having this hard-coded as 4 in the DF_MMIO_* macros. To avoid some duplication, also introduce the DF_MMIO_REG_OFFSET macro. TEST=Output from data_fabric_print_mmio_conf doesn't change on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67420a2973c8ef9a7f0ce19ddc0013de69731689 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/common/data_fabric: replace NB with DF prefix for DF registersFelix Held
Since the MMIO decode range registers in the data fabric are part of the data fabric and not of the northbridge, replace the NB prefix with a DF prefix to make this a bit clearer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ife5e4581752825e9224b50252955d485a067af74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/*/data_fabric: rename define for MMIO decode register set countFelix Held
This should make it a bit clearer that those registers are in the data fabric configuration registers. Also move those defines right after the register definition those are related to. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic107bd217f4af0a9ddfbe41aafd3c882aa968e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08soc/amd/phoenix/include/cpu: rename CPUID define to match CPU modelFelix Held
CPUID 0x00a70f80 is Phoenix 2 and not Phoenix, so update the define name to match. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7500130d5470fdd824980b81746f3a0f6d277d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72843 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-08mb/intel/mtlrvp: Add ACPI configuration for USB2/3 portsHarsha B R
This patch adds ACPI configuration for USB2/3 ports for mtlrvp as per schematics. This helps in generating corresponding ACPI code at runtime that includes port information. BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP. Connect USB device and check if corresponding enumeration of USB device (14.0) is observed on executing lspci. 00:14.0 USB controller: Intel Corporation Device 7e7d (rev 01) 00:14.1 USB controller: Intel Corporation Device 7e7e (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie150247661322e3944be15dc70f66033266d8aac Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72787 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Describe mainboard configuration for BB RetimerHarsha B R
This patch describes BB retimer for tcss_dma0 and tcss_dma1 with respect to GPP_B21 as per schematics. +--------------+------------+ | tbt_pcie_rp0 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp1 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp2 | tcss_dma1 | +--------------+------------+ | tbt_pcie_rp3 | tcss_dma1 | +--------------+------------+ BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of tbt_pcie_rp as part of lspci. 00:07.0 PCI bridge: Intel Corporation Device 7ec4 00:07.1 PCI bridge: Intel Corporation Device 7ec5 00:07.2 PCI bridge: Intel Corporation Device 7ec6 00:07.3 PCI bridge: Intel Corporation Device 7ec7 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie1a0026b064aa4f7fcd27e75c0b0d052ec620dcc Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72786 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Describe TCSS USB portsHarsha B R
This patch describes the TCSS USB ports for mtlrvp as per schematics. This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below, tcss_usb3_port1: USB3 Type-C Port C0 tcss_usb3_port2: USB3 Type-C Port C1 tcss_usb3_port3: USB3 Type-C Port C2 tcss_usb3_port4: USB3 Type-C Port C3 BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C ports as part of cbmem -c. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72785 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 20:56:27 +0000