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2018-12-03nb/intel/x4x: Use common code for SMM in TSEGArthur Heymans
This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel DG41WV, resume from S3 still works fine. Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25597 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/i945: Use common SMM_TSEG codeArthur Heymans
Use the common SMM_TSEG code to relocate the smihandler to TSEG. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. This fixes S3 resume being broken introduced by CB:25594 "sb/intel/i82801gx: Use common Intel SMM code". Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel d945gclf and Lenovo Thinkpad X60. Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25595 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03sb/intel/i82801jx: Use common Intel SMM codeArthur Heymans
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. The platform (x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25596 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/gm45: Correctly cache TSEGArthur Heymans
Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03soc/intel/apl: Configure LPC serial IRQ modeNico Huber
Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/fsp_baytrail: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/denverton_ns: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/common: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/broadwell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/braswell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I93c11e89da34c5432c6ce0415998b47bad339763 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29889 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30soc/intel/baytrail: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29888 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/fsp_model_406dx: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I00d15d0640a37f89ffd5cc87b89d5ba11fecb9ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29887 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/model_206{5,a}x: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29886 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/haswell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications the CPU. Generate PPKG in SSDT. Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29885 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30soc/intel/skylake: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29884 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30sdm845: Add clock supportDavid Dai
This sets up initial clock configuration for QUP and QSPI, and includes configuration of Root Clock Generators(RCG) and clock branches enablement. TEST=build & run Change-Id: I0b1d7f6daa179c0b24a97d42b66c1a9ee596b0a3 Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/25454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30arch/power8: Rename to ppc64Jonathan Neuschäfer
POWER8 is a specific implementation of ppc64, which is by now outdated (POWER9 has been on the market for a while). Rename arch/power8/ to potentially cover a wider range of hardware. TEST=Toolchains built before/after this commit can build coreboot for emulation/qemu-power8 from before/after this commit. Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2018-11-30security/vboot: Fix remaining measured boot issuesPhilipp Deppenwiese
Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30broadcom: Remove SoC and board supportPhilipp Deppenwiese
The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29google/kahlee/variants/aleena: Set STAPM values.Lucas Chen
According to aleena thermal testing to set STAPM values. skin scalar for 80%. time constant for 2500s. power limit for 7.8w. BUG=b:72979852 TEST=test build for thermal check. Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part NumberLucas Chen
Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29mb/google/octopus: Create Casta variantKarthikeyan Ramasubramanian
This commit create a casta variant for Octopus. The initial settings override the baseboard GPIO configuration for Touchscreen, LTE, Pen and Trace modules. BUG=b:119056117 BRANCH=None TEST=None Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/29763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-29mediatek/mt8183: Add DDR driver of rx dqs gating calibration partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I504d6d5c9ea01b11a9f2a05b5ee4b5f1af87e23f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-29arch/acpi.h: Add some update to version 6.2aElyes HAOUAS
Some tables updated to comply with ACPI version 6.2a. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-29mb/google/sarien: Add HD Audio verb tableLijian Zhao
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 TEST=Confirm audio play back is working on Sarien and Arcada board. Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2018-11-29azalia: Add Azalia Reset macroLijian Zhao
Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to execute function reset. Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-29{mb/cubieboard,soc/intel/quark}: Remove define __SIMPLE_DEVICE__Elyes HAOUAS
Remove the __SIMPLE_DEVICE__ define from files used only in romstage. This is not required since romstage always defines __SIMPLE_DEVICE__. Change-Id: I8db1b15c9186536c9b8a6b5d667fa5a11af1bad2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29821 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29arch/x86/acpigen.c: Add a method to notify all CPU coresArthur Heymans
Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-29siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29882 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-29siemens/mc_apl5: Enable SDCARDMario Scheithauer
This mainboard also has a SD slot. Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-29arch/x86/Makefile.inc: Fix typoPatrick Rudolph
Link 32bit ramstage if CONFIG_ARCH_RAMSTAGE_X86_32 is set. Required for 64bit ramstage support. Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29878 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29mediatek/mt8183: Add MT6358 PMIC supportHsin-Hsiung Wang
PMIC provides power features like auxadc, buck/ldo, interrupt-controller..etc BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic247faf73517f6512f9c9a69ba0254c749d68d4c Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29422 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29mediatek/mt8183: Add PMIC wrapper supportHsin-Hsiung Wang
The PMIC wrapper is a proprietary hardware to connect the PMIC. This patch implements PMIC wrapper driver for the communication with PMIC. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Idbdb15f11227ded3f5d18fe6504c8c646973b733 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-28mb/google/kahlee: Update vBIOS used for aleenaRichard Spiegel
The aleena board uses a display that's not compatible with current VBIOS. A VBIOS specific for aleena has been merged into blobs, so modify Kconfig so that it loads the new VBIOS when building aleena, but load original VBIOS for all other boards under kahlee folder. BUG=b:112618193 TEST=Build each board under kahlee, one at a time. After each build, opened build/config.h and searched VGA_BIOS_FILE to verify that the string only changed for aleena, all other boards remained with original string. Change-Id: Iccd0853692680908d951edd142a2d8e13a561391 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-28drivers/intel/gma: Fix typo in headerFrans Hendriks
Correct typo of 'version' BUG=N/A TEST=N/A Change-Id: I05d7856072042c79f9d7aafdfecc9b3635f1d0cc Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-11-28tss: implement tlcl_save_stateJoel Kitching
When an untrusted OS is running, we would like to use the Cr50 vendor-specific VENDOR_CC_TPM_MODE command to disable TPM. Before doing this, we should save TPM state. Implement tlcl_save_state for this purpose. This needs to live in coreboot codebase since on S3 resume path, depthcharge is not reached. Implement the function in both tcg-1.2 and tcg-2.0 for completeness. BUG=b:70681930,b:118202153 TEST=hack a call to tlcl_save_state into coreboot on S3 resume verify in AP console that it is called Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I8b51ca68456fc9b655e4dc2d0958b7c040d50510 Reviewed-on: https://review.coreboot.org/c/29646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-28soc/amd/stoneyridge: Replace public magic numbersPatrick Georgi
Some "magic" numbers became public available registers/bits after the code was originally written. Find all magic numbers, and if available in a public BKDG than replace them with literals. BUG=b:117648026 TEST=Build and boot grunt. Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-28sb/amd/sb800: Remove unused smbus_delay() functionElyes HAOUAS
Change-Id: I08ed67dd7159f8a407d61c9b5fc69ff6aef10057 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29843 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28src/{mainboard,southbridge}: Remove commented include linesElyes HAOUAS
Change-Id: Ie06ae528ade3e06ae880b488628692ce43c30f5a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29845 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28soc/fsp_broadwell_de: Add early microcode updatesPhilipp Deppenwiese
Add support for updating microcodes on FSP 1.0 platforms before memory is initialized. This is a requirement to fill other FIT entries except for microcode updates. Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29819 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Huang Jin <huang.jin@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28mb/hp/compaq_8200_elite_sff: Fix SATA port mapPatrick Rudolph
Assign correct SATA port map. Tested on HP8200: All SATA ports are now usable in GNU/Linux. Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/29855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-28security/vboot: Add VB2_LIB to romstage sources without dependenciesWerner Zeh
The coming feature "measured boot" relies on VB2_LIB in romstage. In the case where there is no separate verstage, compile the library just for romstage as it will then be shared across verstage and romstage code. If there is a separate verstage, compile the library separately for verstage and romstage. Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-28soc/intel/{baytrail,broadwell}: Correct Chromeos RAM reservationFrans Hendriks
RAM is reserved for Chromeos even when Chrome is not used. Use CONFIG_CHROMEOS to determine is RAM must be reserved. BUG=N/A TEST=Intel BayTrail CRB Change-Id: Ic1f5089227f802e2b2f62dc02fa0d1648c1855b5 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-28soc/intel/icelake: Fix IO decode setupSubrata Banik
Make pch_early_iorange_init() function similar to soc/intel/cannonlake/bootblock/pch.c while fixing below issue: * COM1 not being enabled properly. TEST=Able to get serial output from an 8250IO UART device at the standard 0x3f8 base address. Change-Id: I5ab02f46d27e667be3d9328d94b634ef04038d2f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-11-28src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE valueFrans Hendriks
Using 0 for PIRQ_PIC_IRQDISABLE might conflict with using IRQ0 as PIRQ. Change PIRQ_PIC_IRQDISABLE value to 0x80, so value 0 is reserved for IRQ0. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29393 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ↵Frans Hendriks
ILB_BASE_SIZE The sizes of IO_BASE and ILB_BASE areas a incorrect. Correct IO_BASE_SIZE and ILB_BASE_SIZE values. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-28vendorcode/cavium: Supply bdk_pop and bdk_dpop definitionsMartin Roth
This is an issue found by the new builder image and needs to be fixed before we can upgrade to the new toolchain version: In function `bdk_dram_get_size_mbytes': src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c:198: undefined reference to `bdk_pop' In function `bdk_get_num_cores': /src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h:164: undefined reference to `bdk_dpop' In function `init_octeon3_ddr3_interface': src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c:7550: undefined reference to `bdk_pop' Change-Id: Ibf71e4556014795bfedceccfe3837dc9deb29ad2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/29851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-28soc/intel/braswell/northcluster.c: Reserve local APIC resourcesFrans Hendriks
The resources of the local APIC are not reserved. Use mmio_resource() to add local APIC resources. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-28src/soc/intel/braswell/acpi/lpc.asl: Add ACPI and GPIO basesFrans Hendriks
ACPI and GPIO base are used by LPC controller, but not reserved. Both bases are added to the LPC device resources. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I5248694b497c4965d79dd7c25ec97592dc0dddbc Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-28sb/intel/common: Fix style issue in spi.cElyes HAOUAS
Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27mb/google/octopus/var/phaser: Deprecate board id 0Furquan Shaikh
This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of code in variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-11-27mainboard/google/reef: Bump mainboard mem versionKane Chen
This change is to bump fsp_memory_mainboard_version in order to trigger MRC full training BUG=b:119481870 CQ-DEPEND=CL:*716558 BRANCH=reef, coral TEST=make sure MRC retraining is triggered and the MRC cache is updated to newer version. Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/29647 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/intel/icelake_rvp: Enable HDA audio supportAamir Bohra
This patch enables HDA audio support on icelake rvp. Add ALC700 codec verb table and selects SOC_INTEL_COMMON_BLOCK_HDA_VERB config to detect and initialize codec configuration as specified in verb table. BUG=none TEST=verify codec is listed and audio playback is working Change-Id: Ibdf707f9002a09870ebe879c9db462084ecb01ea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-27mb/intel/icelake_rvp: Add EC acpi support codeAamir Bohra
This implementation adds below changes: 1. Add chrome ec asl support for iclrvp. 2. EC SCI, SMI, S3/S5 wake events. 3. Wake pin and EC SMI GPE confiiguration. Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29797 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/intel/icelake_rvp: Include cpu.asl in DSDT ACPI tableAamir Bohra
This implementation adds support of PNOT method included in cpu.asl. It is needed to notify CPU APCI device to re-evaluate the _CST table for list of supported C-states. Change-Id: I135cc3aa32a912c8ad3449d063d533f8873fcc94 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-27sb/intel/i82801gx: Use common Intel SMM codeArthur Heymans
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Tested on Intel D945GCLF, still boots fine but breaks S3 resume support because it hangs on SMI. Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27soc/intel/cannonlake: Delete unused macros in lpc.hSubrata Banik
TEST=Able to build and boot successfully. Change-Id: If013d8e59046152e9f1a026f48bd9cd9b43ab6af Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29836 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Enable audioSubrata Banik
BUG=b:116191230 BRANCH=None TEST=1. verified boot beep support at depthcharge. Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29753 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Enable trackpadSubrata Banik
BUG=b:112282079 BRANCH=None TEST=1. run evtest and make sure trackpad shows up in list 2. Able to wake system from S3 using trackpad Change-Id: I86d6b7815147d558065611604363bb607119c154 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29752 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Enable ps2 keyboardShelley Chen
BUG=b:112332115 BRANCH=None TEST=ensure at bootup that /sys/devices/pnp0/00:05 exists and driver link to '../../../bus/pnp/drivers/i8042 kbd' Also, can now see keyboard in evtest. Change-Id: I2a6b382be84bc5201beafe21ff8ddee3738bc5c2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29750 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Add initial mainboard code supportAamir Bohra
This patch includes support for both ICL ES0 and ES1 samples. Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md TEST=Able to build and boot dragonegg. Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27mb/google/poppy/variants/nami: Enable g2touch touchscreen deviceCrystal Lin
This change adds ACPI properties for GTCH7503 device. BUG=b:119169362 BRANCH=firmware-nami-10775.B TEST=Verify touchscreen works with this change Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29768 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/fizz/variants/karma: Disable SD controller and update GPIODavid Wu
The SD cardreader is on USB bus, not on SDIO/SDXC. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27mb/google/fizz/variants/karma: Enable touchscreen wakeupDavid Wu
Set GPIO GPP_B4 to high to enable touchscreen wakeup. BUG=b:119594783 BRANCH=master TEST=DUT can wake up with touchscreen. Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27mainboard/google/octopus/variants/ampton: Decrease I2C CLK frequencyCarl Yang
The touchpad and touch-panel CLK frequency should be smaller than 400 kHz which described in spec. Overwrite i2c speed parameters by overridetree.cb BUG=b:119540449 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage flash bios and check the touchpad i2c frequency meets the spec. Change-Id: I32c3e1bbfc2cdf39e9b7865a69996e54346d5f93 Signed-off-by: Carl Yang <carl_yang@asus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macrosElyes HAOUAS
MTRR addresses are publicly available at cpu/x86/mtrr.h, so use macros instead of "magic" numbers. Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29580 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/octopus/var/bobba: Deprecate board id < 2Furquan Shaikh
This change deprecates boards with id < 2. It updates touchscreen enable GPIO in overridetree and gets rid of variant.c to update enable GPIO at runtime. Additionally, it configures old enable GPIO as NC. BUG=b:119885949 Change-Id: I42fb7ef90e421118a8fdfa0d343d0bcf4a9bc087 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/google/octopus/var/fleex: Deprecate bid 0Furquan Shaikh
This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: If14abb324d9422720ca4d0f0859e092319d454ee Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/google/octopus: Update GPIO_178 in early_gpio_table in baseboardFurquan Shaikh
This change updates the configuration of GPIO_178 to be active low as per latest revision on different octopus variants. This effectively: 1. Gets rid of early_gpio_table in different variants -- phaser, meep, fleex, bobba. 2. Deprecates board id < 2 for bobba, board id < 1 for fleex and phaser. 3. Adds special early_gpio_table in yorp which has GPIO_178 as an active high signal. BUG=b:119885949 Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/google/octopus: Configure all debug header lines as NCFurquan Shaikh
This change configures all the pads going to debug header as not connected. BUG=b:111569213 BRANCH=None TEST=None Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-27mb/intel/icelake_rvp: Add USB port capablity informationAamir Bohra
This implementation adds USB port capablity map for ICL-U and ICL-Y RVP. Change-Id: I20bb43c47439df0a25ff148eae2b3e0546e4bc63 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-27src/{commonlib,drivers/intel/fslp1_1/include}: Fix typoFrans Hendriks
Correct typo of 'compilation' BUG=N/A TEST=N/A Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-11-27siemens/mc_apl5: Adjust the settings for the PCIe root portsMario Scheithauer
This mainboard has four connected PCIe devices. The required root ports are switched on and configured. Change-Id: I82b13e1d245a172762ebd689ae136a762027033f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29810 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27soc/intel/skylake: Add device settings for PL4 power limitPraveen hodagatta pranesh
PL4 is a preemptive CPU package peak power limit,it will never be exceeded. Power is preemptively lowered before limit is reached. This change provides option in devicetree and feeds FSP PowerLimit4 UPD for power limit purpose. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8 Reviewed-on: https://review.coreboot.org/c/29808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27soc/intel/common: Add audio controller device id for SKL-H pchPraveen hodagatta pranesh
This patch add new HDA controller pci id in common hda driver. BUG:None TEST:Boot to Yocto linux on kabylake rvp11 and verified audio playback functionality. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I820115c31bf6b8e1f1afe900b68690d84b51c259 Reviewed-on: https://review.coreboot.org/c/29807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-26sb/intel/common: Fix style issue in spi.cPatrick Georgi
Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan T <stefan.tauner@gmx.at> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-26sb/intel/spi: read FLCOMP descriptor early and cache itStefan Tauner
Change-Id: I4e5fe3ff083f2d0db1cfde16550b57537d5f7262 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/c/28349 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-26drivers/spi: store detected flash IDsStefan Tauner
Change-Id: I36de9ba6c5967dddd08a71a522cf680d6e146fae Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/c/28347 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-26drivers/intel/fsp1_1/raminit.c: Report only when NVS HOB is missingFrans Hendriks
Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always. This hob is only generated by FSP during non-S3 and MRC data is changed. Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is required. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang Jin <huang.jin@intel.com>
2018-11-26siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN readMario Scheithauer
An additional read of PTN configuration data at the end of the ptn3460_init function is not necessary. Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-26soc/intel/icelake: Add support to enable/disable USB charging in s3/S5Aamir Bohra
Change-Id: I0559b8a546f7a67759377c7f51b2faa2280aa797 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29793 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-25nb/intel/i945: Add and use defines for registers of device 0:01.0Elyes HAOUAS
Some registers are not documented in "Mobile Intel 945 Express Chipset Family" datasheet but they are in "Intel 945G/945GZ/ 945GC/945P/945PL Express Chipset Family" datasheet. Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-25nb/intel/i945/early_init.c: Correct the PEG_LC address of DEV(0:01.0)Elyes HAOUAS
This bug/typo was spoted by Felix Held. As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control" located at 0xec. Used address at 0x114 to enable GPEs is likely a typo. Patch not tested. Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/27307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-25nb/intel/gm45/northbridge.c: Check for NULL pointersArthur Heymans
Change-Id: Ic12a8c145d6348086f9931af93ce6d3b3dcb9039 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-23sb/intel/bd82x6x/early_usb.c: Fix formattingElyes HAOUAS
Remove whitespace between the function name and open parenthesis, and fix 81+ characters lines. Unnecessary comment about 'include sandybridge.h'removed. Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29428 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23mb/google/kahlee: Enable 2T mode for liara in DVT phaseChris Wang
Change the board id detection to support rev5, since the 2T mode still needed in DVT build. BUG=b:116082728 TEST=verify by ODM. Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-23arch/x86: drop special case cbfs locatorPatrick Georgi
CBFS used to have a special region for the x86 bootblock, which also contained a pointer to a CBFS master header, which describes the layout of the CBFS. Since we adopted other architectures, we got rid of the bootblock region as a separate entity and add the x86 bootblock as a CBFS file now. The master header still exists for compatibility with old cbfstool versions, but it's neatly wrapped in either the bootblock file or in a file carefully crafted at the right location (on all other architectures). All the layout information we need is now available from FMAP, a core part of a contemporary coreboot image, even on x86, so we can just use the generic master header locator in src/lib/cbfs.c and get rid of the special version. Among the advantages: the x86 header locator reduced the size of the CBFS by 64 bytes assuming that there's the bootblock region of at least that size - this breaks assumptions elsewhere (eg. when walking CBFS in cbfs_boot_locate() because the last file, the bootblock, will exceed the CBFS region as seen by coreboot (since it's CBFS - 64bytes). TEST=emulation/qemu-q35 still boots Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-23soc/intel/apollolake: Remove cycle in Kconfig symbol dependenciesPatrick Georgi
Change-Id: Iad60a5c8863283b7d373e1f6aaff48c40b7bb274 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-23src/soc/intel/braswell/southcluster.c: Replace fixed values by definesFrans Hendriks
The GPIO and ACPI base sizes have defines, but they are not used. Use GPIO_BASE_SIZE and ACPI_BASE_SIZE. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I348eda57ab9dc0bd45f8dc9ab0e7c47c462102fe Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29788 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23src/soc/intel/baytrail/southcluster.c: Replace fixed values by definesFrans Hendriks
The GPIO and ACPI base sizes have defines, but they are not used. Use GPIO_BASE_SIZE and ACPI_BASE_SIZE. BUG=N/A TEST=Intel BayTrail CRB Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Huang Jin <huang.jin@intel.com>
2018-11-23soc/intel/skylake: Drop FSP_CAR optionsNico Huber
It's not implemented for Skylake, all combinations that try to enable it either result in Kconfig or linker errors. Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's effective. TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default configs with and without this patch: binaries stay the same. Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-23src/arch/x86/acpi.c: Create log area and extend TPM2 tableMichał Żygowski
According to newest TCG ACPI Specification for Family 1.2 and 2.0 Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA. Update the table structure definition, create the log area for TPM2 in coreboot tables and fill the missing fields in TPM2 table. TPM2 should be now probed well in SeaBIOS rel-1.12.0 or master. Tested on apu2 with Infineon SLB9665 TT2.0. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/29800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-23intelblocks/cpu: Fix wrong comment for P_Req field in PERF_CTL MSRWerner Zeh
The mentioned bits 14:8 are wrong as the functions always write bits 15:8. What happens is visible in the written code. There is no need for an extra comment. Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-11-23siemens/mc_apl4: Set CPU clock to minimum ratioWerner Zeh
The power budget for this mainboard is very limited while the performance demand is low. Set the CPU clock to the lowest value to enable maximum efficiency and thus lowest power dissipation. Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-23soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratioWerner Zeh
Add a Kconfig switch to be able to set the CPU clock to the lowest possible ratio. If enabled the CPU will consume as little power as possible while providing the lowest performance. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to its need. Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-23intelblocks/cpu: Add function to set CPU clock to minimum valueWerner Zeh
Provide a library function to set the CPU frequency to minimum value. This will result in the lowest possible CPU clock with the lowest possible power consumption. This can be useful in mobile devices where the power dissipation is limited. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to it's need. Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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