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2024-01-22commonlib/bsd/compiler.h: Define __section(section) macroYu-Ping Wu
Define __section(section) to be a shorthand for __attribute__((__section__(section))). Change-Id: I67a37e5b2aae0bfa68b0319c477ab5d6c55e6501 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-22mainboard/Kconfig: add 24MB ROM sizeMaciej Pijanowski
16MB + 8MB flashes are used on some boards, such as Lenovo M920 Change-Id: Iac6e076ed17d7e944cc829ff0cb27ede50c6f7db Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80072 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-01-22mb/google/dedede/var/galtic: Correct name for mem-part K4U6E3S4AA-MGCRDaniel Peng
Repo sync code recently, run command as memtioned in TEST and found the changed for the auto-gen files. Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR, and no new for the used hex file. BUG=b:320181366 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79976 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22soc/intel/xeon_sp: Fix devicetree walking upPatrick Rudolph
Connect the PCI domain to the bus to allow walking the devicetree up. This is required to figure out which PCI domain a device belongs to. Change-Id: I8cc50cabf7ad540c52498e1ffe7f9246550ed87b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-01-22soc/intel/cmn/block/pmc: Fix prev_sleep_state string name mappingAnil Kumar
commit d078ef2152052b5ce8686249dcd05ebd50010889 ("soc/intel/cmn/block/pmc: Add previous sleep state strings in log") used SLP_TYP numbers to map ACPI sleep state value. This incorrectly printed wrong string for prev_sleep_state during S5. ex: after a cold reset the previous sleep state printed was [DEBUG] prev_sleep_state 5 (S3) This patch corrects this by using ACPI sleep state numbers for mapping the prev_sleep_state values. TEST=test the logs on google/rex board after cold reset [DEBUG] prev_sleep_state 5 (S5) Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I9bcdacc4d01a8d827a6abdf9af2b9e5d686ed847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80144 Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-22soc/intel/meteorlake: Fix system hang by enabling SMI handlingKane Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:306267652 TEST=Cold reboot test on 20 google/screebo by ODM, all passed w/o hang. Change-Id: Ie1f096f8eda4adcf1627e44afa517b02adddad76 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-21device_util: Drop unused function bus_pathArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id23a291af20473c3b3e67178b66fcde920d49984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-20mb/purism/librem_skl: Fix pcie_rp5 in device tree (WLAN)Jonathon Hall
WLAN has always been pcie_rp5, there is nothing on pcie_rp1. RP5 gets promoted to function 0 (RP1's function) since no earlier functions are enabled. This simplifies later refactoring that will handle the FSP root port enable flags (which were correctly set already) using the device tree enables. Test: Boot librem_13v2 and verify WLAN is enabled. Change-Id: I7a724a01b5f171a16de83ff6122630e2d66557c1 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-20soc/amd/*/chip: factor out FSP-S callFelix Held
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-20soc/amd: factor out non-CAR romstage to common codeFelix Held
Since the romstage code is very similar between all AMD non-CAR SoCs, factor out a common romstage implementation. All SoCs that select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so this Kconfig option can be used to determine whether to make that call. In the FSP case, amd_fsp_early_init gets called, while in the case of an implementation that doesn't rely on an FSP to do the initialization, cbmem_initialize_empty gets called to set up CBMEM which otherwise would be done inside the FSP driver code. Since only some SoCs call fch_disable_legacy_dma_io again in romstage right after amd_fsp_early_init, introduce the new SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the SoCs can specify if this call is needed or not. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-20soc/amd/*/romstage: factor out FSP-M callFelix Held
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code and a preparation to make the romstage of all non-CAR AMD SoCs common. Without isolating the call into the FSP-M code, building the common romstage would fail for genoa_poc due to fsp/api.h not being in the include path. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/80002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-20soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.cFelix Held
fsp_m_params.c and fsp_s_params.c only contain FSP-specific code, so only add those to the build if the SOC_AMD_PHOENIX_FSP Kconfig option is selected. Other files have FSP-specific parts too, but those will be reworked in future patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ife38ca6a548d7c3c2e765d9c9f30e0a4057bb373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79984 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20soc/amd/phoenix/Kconfig: factor out FSP-specific optionsFelix Held
Split the SOC_AMD_PHOENIX Kconfig option into SOC_AMD_PHOENIX_BASE that selects the non-FSP-specific options and SOC_AMD_PHOENIX_FSP that selects both SOC_AMD_PHOENIX_BASE and the FSP-specific options. This will help to separate the FSP-specific from the FSP-agnostic code. The mainboards using this SoC now select SOC_AMD_PHOENIX_FSP instead of SOC_AMD_PHOENIX. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e95fbfd9d16930ba3e6cc497557d61adba5a6fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79983 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20mb/google/brox: enable WIFI_SARShelley Chen
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG for WIFI to choose the right wifi_sar hex file. Below is the file mapping: wifi_sar_0.hex = wifi6 wifi_sar_1.hex = wifi7 BUG=b:319302319 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Change-Id: I212c80412141e7770a512bd8ccf4111963bab395 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80085 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19device/Kconfig: Move Intel/ACPI/USB4 specific Kconfig optionsArthur Heymans
This options should not be visible on !Intel, !ACPI and !USB4. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia515d52baead9e151533278c33fda9436ee56168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79669 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/hp/snb_ivb_desktops: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from hp/snb_ivb_desktops are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I0974052c6c18f54b588d296c5c5d11e930f0fcd7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80047 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I31e348ba5954bc463f43e769ddb4aed413faf193 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/x230: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/x230 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Ia06f976ef1439377ff22149044feaa3463d2aeb8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/t430: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t430 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I84f432e89c41a02115715f7f1b56123dd0d81171 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/t530: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t530 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I5ba08843506bc22136aea42ac37936a4f5cad5ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/siemens/chili: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80022 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-19mb/purism/librem_cnl: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-19mb/purism/librem_l1um_v2: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Id592241a1dc33559115800da10a57a5fc10867f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-19mb/protectli/vault_cml: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I76ec42fccfa42bbe3943e048968a76eec3584ee8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-01-19mb/dell/snb_ivb_workst: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from dell/snb_ivb_workstation are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Iac70aa25dd324e1ed5fa0bb995eb995ec3545715 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-01-19mb/dell/snb_ivb_workst: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80052 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/starlabs/starbook/cml: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ia004de6606a1685822d5567123887c60d89e3119 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-01-18mb/google/brya: Drop primus4es boardJakub Czapiga
Primus4es board is no longer supported thus drop it from the tree. TEST=Build all Brya boards in CrOS-SDK - Primus4ES not built. No negative impact observed. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-18include/bootmem.h: Add commentMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I8f6752e887af8c1ceba56153e3da864abd040ffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79947 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18include/memlayout.h: Add OPENSBI linker macroMaximilian Brune
This adds an opensbi linker macro for easier integration into memlayout.ld linker scripts. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I4f138de685c6bfb3cdbf79d63787eb0c5aab8590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77974 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/dedede/var/pirika: Add initial fw_config configuration settingDaniel Peng
1. Describe the FW_CONFIG probe for the settings for Palutena. - WIFI_SAR_ID_0 for AW Wi-Fi module AW-CM421NF - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW 2. In contrast to the AW Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table in dedede platform. 3. For Palutena project, the SKU ID segment of Palutena is set for "0x350000~0x35FFFF". BUG=b:319792428 BRANCH=firmware-dedede-13606.B TEST=build pass Change-Id: Ic4f38928d24c4398d90df226cfe0788a30075bf2 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79930 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2024-01-18mb/google/nissa/var/craaskov: Add fan performance controlRex Chou
Add 6w and 15w fan performance control. BUG=b:318454915 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: If21baa2f6f9bcd527cec2bced27c5fb2cd607830 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79988 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/nissa/var/craaskov: Modify 6W and 15W DPTF parametersRex Chou
1. Modify 6w/15w DPTF parameters based on b:290705146#comment41. 2. 6W MSR power limit_1 power (Watts) increase to 20. 3. 15W MSR power limit_1 power (Watts) increase to 20. BUG=b:290705146 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: I15fa4b8f7c7088ff56da6493659ae45572913b5a Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-18device/device.h: Fix outdated commentArthur Heymans
LAPIC devices in devicetree is not possible any longer since commit 3eba665 "util/sconfig: Remove lapic devices from devicetree parsers". TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-18sb/intel/bd82x6x: Rework PCH ID cacheAngel Pons
Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore. Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-18soc/intel/braswell: Use {read,write}32p()Elyes Haouas
Change-Id: I00894565efc405a47348236ad7df50071a843487 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77972 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/brox: Fix user facing camera acronymShelley Chen
I got confused and used UFS (User Facing Side) for the User Facing Camera (UFC) in the FW_CONFIGs. Change references of the camera from UFS --> UFC. BUG=b:300690448 BRANCH=None TEST=None. The camera has not been enabled yet. Change-Id: I4f8240ae51aad1e077f325a9eab5a2a92f1402cb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79997 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/intel/elkhartlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17mb/google/poppy: Use chipset dt reference namesMarvin Evers
Use the references from the chipset devicetree as this makes the comments superfluous. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-17arch/x86/mpspec: turn compile-time check into Kconfig dependencyFelix Held
Instead of checking if there is more than one PCI segment group and erroring out in that case during the build, add this requirement as a dependency to the GENERATE_MP_TABLE Kconfig option. The mpspec.c source file only gets included in the build if GENERATE_MP_TABLE is selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie532a401ad0161890d0fb4ca2889af022d5f6b47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-17vc/amd/psp: Remove unknown section flagsLennart Eichhorn
The `d` flag used in .section is unknown in LLVM/clang 17 and fails the build. It is also not documented in the ARM compiler manual. The GNU assembler supports the `d` flag but it also seems to compile without. ARM compiler manual: https://developer.arm.com/documentation/101754/0621/armclang-Reference/armclang-Integrated-Assembler/Section-directives GNU compiler manual: https://sourceware.org/binutils/docs/as/Section.html `coreboot.rom` does not change between compiling a google skyrim board with or without this patch. However the debug info for the following three files in the build directory changes with this patch: * build/verstage/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.o * build/cbfs/fallback/verstage.elf * build/cbfs/fallback/verstage.debug Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5 Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79366 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17tree: More use accessor functions for struct region fieldsNico Huber
Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-17mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay from 1ms ↵Rex Chou
to 6ms Modify touchscreen enable_delay to 6ms to meet with spec. eKTH3915N_Product Spec_V1.3_20221028_IPM.pdf BUG=b:318443640 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79978 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2024-01-17soc/mediatek/mt8188: Enable EARLY_MMU_INITYidi Lin
The boot time is improved by 65ms. (762ms -> 697ms) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I74191ab8cbefa08b7e296312645ea40b46fabf77 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79991 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/mediatek: Add EARLY_MMU_INIT kconfig optionYidi Lin
Accessing RAM before mmu initialized is time consuming. During mmu initialization, `mmu_init()` and `mmu_config_range()` write logs to the console buffer and contribue the extra boot time. This patch adds a kconfig option to move `mtk_mmu_init()` to `bootblock_soc_early_init()`. When `EARLY_MMU_INIT` is enabled, mmu is initialized before `console_init()` ready. So `mmu_init()` and `mmu_config_range()` won't write logs to the console buffer and save the boot time. It saves about 65ms on Geralt with EARLY_MMU_INIT enabled. Before: 0:1st timestamp 239,841 (0) 11:start of bootblock 239,920 (79) 12:end of bootblock 323,191 (83,271) After: 0:1st timestamp 239,804 (0) 11:start of bootblock 239,884 (80) 12:end of bootblock 258,846 (18,962) BUG=b:320381143 TEST=check timestamps in cbmem Change-Id: I7f4c3c6c836f7276119698c6de362794cf4222a6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-17Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17mb/google/nissa/var/gothrax: Tune eMMC DLL valuesSimon Yang
Gothrax cannot boot into OS with a kernel loading failure. Update eMMC DLL values to improve initialization reliability How to get these values: - Sending different speed TX/RX command/data signal to eMMC and check the response is successful or not. - Collecting above results from each eMMC model that project used. - Analysing logs to provide a fine tuned DLL values. BUG=b:310701323 TEST=Cold reboot stress test over 2500 cycles Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-17mb/google/brox: Move storage devices to overridetreeShelley Chen
These are specific to the brox board, so moving devices to the brox variant. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-17mb/google/brox: Set up FW_CONFIGShelley Chen
Brox project has FW_CONFIG bits already set up in the project file for the retimer and for storage, so make sure that the brox device tree matches those settings. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79854 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-16soc/intel/apollolake: Fix PCI memory resource allocReto Buerki
There is a mismatch in how PCI memory resources are allocated on Apollo Lake with the current configuration. While the ACPI code expects resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code allocates them above, leading to the following error messages on Linux: pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref] Tested on up/squared with Linux kernel version 6.1.0. Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS, and by moving the UART base address into the expected range. Thanks to Nico Huber for the help in writing this patch. Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Signed-off-by: Reto Buerki <reet@codelabs.ch> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79957 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-16device: Add support for multiple PCI segment groupsFelix Held
Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new segment_group struct element and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-16mb/google/nissa/var/craaskov: Add Micron MT62F1G32D4DR-031 to mem_partsIan Feng
Add new memory Micron MT62F1G32D4DR-031 WT:B. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 2 (0010) BUG=b:319778218 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79914 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-15include/device/pci_mmio_cfg: assert CONFIG_ECAM_MMCONF_BUS_NUMBER != 0Felix Held
Make sure that CONFIG_ECAM_MMCONF_BUS_NUMBER is non-zero when the ECAM_MMCONF_SUPPORT Kconfig option is selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic102b7dca9ffebb2d384a068a1fb1f4b6fb6c5f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79933 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-15soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBERFelix Held
The Cavium CN81xx SoC selects ECAM_MMCONF_SUPPORT, but doesn't set a value for ECAM_MMCONF_BUS_NUMBER which results in it defaulting to 0 which is wrong. Both the Cavium CN8100 SFF EVB and the OpenCellular Elgon (GBCv2) mainboard specify 32 PCI buses in their Linux devicetree files, so set the SoC's ECAM_MMCONF_BUS_NUMBER Kconfig option to 32 to match this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79931 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-15device/Kconfig: handle ECAM_MMCONF_BUS_NUMBER being 32Felix Held
Provide a default for the ECAM_MMCONF_LENGTH Kconfig option for the ECAM_MMCONF_BUS_NUMBER option being set to 32. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01e7da5d49f296dde2de41e23e86e3f49fe78193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-15sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriateElyes Haouas
Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77738 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-01-15soc/intel/xeon_sp: Redesign resource allocationArthur Heymans
The xeon_sp code worked around the coreboot allocator rather than using it. Now the allocator is able to deal with the multiple IIOs so this is not necessary anymore. Instead do the following: - Parse the FSP HOB information about IIO into coreboot PCI domains - Use existing scan_bus and read_resource - Handle IOAT stacks with multiple domains in soc-specific code TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-15src/soc/amd/glinda: Update the PCIE MMCONFIG base address and sizeAnand Vaikar
The PCIE MMCONFIG base address value and size is updated correctly to access the PCIE config space registers. TEST=Verified that PCIE enumeration takes place in boot log and config space registers are accessible. Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-15soc/amd/glinda/include/data_fabric: update IOHUBS0 fabric id Anand Vaikar
The IOHUBS0 is a data fabric component which has a fabric id value specific to SOC. Updated the fabric id for glinda SOC. TEST=Verified that fabric ID is programmed correctly in boot logs. Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79830 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-15sb/intel/bd82x6x/sata: Enable SATA clock gatingPatrick Rudolph
Program SATA IOBP and enable clock gating after port enable bits have been written. The same registers are already set for DMI and PCIe. TEST: Lenovo X220 still boots over SATA. Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79146 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-15sb/intel/bd82x6x/early_usb: Add USB TX/RX gainsPatrick Rudolph
Describe the USB 'current' settings based on MRC.bin that converts the USB trace length to a predefined register value. MRC.bin decides which setting to use based on the PC type, mobile or desktop, and the trace length. Tested: Lenovo X220 still boots. Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-15sb/intel/bd82x6x/early_usb: Print error for invalid USB settingPatrick Rudolph
According to BWG the USB current setting 0 should not be used for desktop boards. As autoport defaults to 0 if the USB current doesn't match one of the lookup table entries most of the desktop boards in tree have such a setting. Print an error to alert users of such boards to update the USB current settings. Tested: Lenovo X220 still boots. Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78827 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/lenovo/x230: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I38ef315dbdadb140e8e7163e755a078bc906e1b5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t430: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ib94dd2778cf89ae8b97b43031d729c728f59a29e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t530: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ied9f37355432d58f83cb8453111a261c4eddc14a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/x220: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/x220 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/x220: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ife8f3bc8b7fd14bb9a0e8dd4bc3d33b44c8f794f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asrock/b75m-itx: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-by: Janik Haag Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/h61-series: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from asus/h61_series are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/h61-series: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I8008fcc994e49c1626fd366c74661fcceb21a323 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/maximus_iv_gene-z: Remove superfluous comments from dtFelix Singer
Since all devicetrees from asus/maximus_iv_gene-z are using the reference names for PCI devices, remove the equivalent comments documenting their function. Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/p8x7x-series: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79967 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/lenovo/t520: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t520 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t520: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I18ce899516fd38b21ded1e3144aa22e705c534b8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79965 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14sb/intel: Use boolean for pcie_hotplug_map attributeFelix Singer
Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79932 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14drivers/mipi: Update init code for BOE_NV110WUM_L60Ruihai Zhou
1. Correct bank1 to bank0 2. Adjust CLK duty 3. Fix abnormal power off setting 4. Change VDDE power off frame from VGL to VGH Fixes: 0d50536("drivers/mipi: Add support for BOE_NV110WUM_L60 panel") BUG=b:319398058 TEST=boot Ciri with BOE_NV110WUM_L60 and see firmware screen Change-Id: I2f068ba0ec9dede3e3361b55c38a8eca8793905a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-14mb/google/geralt: Enable IVO_T109NW41 MIPI panel for CiriRuihai Zhou
The IVO_T109NW41 will be the second source MIPI panel for Ciri. BUG=b:319025360 TEST=boot Ciri with IVO_T109NW41 panel, see firmware screen BRANCH=None Change-Id: I9dc2228d39bb8bb048d1f37727c96b0ad621e912 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-14mb/google/geralt: Enable BOE_NV110WUM_L60 panel for CiriRuihai Zhou
The MIPI panel BOE_NV110WUM_L60 will be used for Ciri, enable it. Also remove the `mdelay(10)` after mtk_i2c_bus_init, because MTK confirms this is not needed. Add mdelay(2) between VDD18 and VSP/VSN to meet the panel datasheet. BUG=b:308968270 TEST=Boot to firmware screen BRANCH=None Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78957 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14tree: Use accessor functions for struct region fieldsNico Huber
Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: Iaae116a1ab2da3b2ea2a5ebcd0c300b238582834 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-14mb/hp/compaq_elite_8300_usdt: Add VBTRiku Viitanen
Extracted from a system running OEM BIOS v03.08 (latest as of now). Build-tested and boots Linux (through SeaBIOS). Command used: intelvbttool --inlegacy --outvbt data.vbt Change-Id: Ibd999d30d6e8fea1368afae67f4dc1c3039d3ae1 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-13tree: Remove duplicated includesElyes Haouas
Change-Id: I09dd5871cb366ef95410efc1ca6c4337f23b52fd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79912 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-13lib/fw_config: Remove redundant stdbool and stdintElyes Haouas
<types.h> already includes <stdbool.h> and <stdint.h> Change-Id: Ie8676769127d21a3b4693ed947a7231b94e99241 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-13lib/smbios: rename segment group parameter of smbios_write_type41Felix Held
Rename the segment group parameter of smbios_write_type41 from 'segment' to 'segment_group' to be in line with the PCI specification. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6ca0ce8b6b3b0357df72bafa2b6069132d0937e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79926 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-13lib/smbios: add segment_group parameter to smbios_write_type9Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-13soc/amd/common/data_fabric/domain: write _SEG method in SSDTFelix Held
As a preparation for the multi PCI segment group support, use acpigen_write_BBN to generate the _SEG method that returns the segment group number of the PCI root. Until the multi PCI segment group support is enabled in coreboot, it will always return 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2a812dcc564c5319385e9ad482d29b2984a71b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79924 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-13acpi/acpigen: add acpigen_write_SEG for segment group number methodFelix Held
Introduce acpigen_write_SEG to generate the ACPI method object that returns the PCI segment group number for a PCI(e) host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-13mb/google/brox: Enable Elan trackpadShelley Chen
BUG=b:311450057,b:300690448 BRANCH=None TEST=to be tested on a device with i2cdetect Change-Id: If6da1c722e87a50c6d422b300f16a52d884fa08f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Configure vGPIOs for NVMeShelley Chen
This is needed for NVMe to work when PCIe device is connected to the CPU side of RPL soc. BUG=b:311450057,b:300690448, b:319058143 BRANCH=None TEST=Tested on device and was able to boot to the OS Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Disable package c state demotionShelley Chen
This needs to be disabled for RPL otherwise we'll hit the assertion: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066 There is a comment in the referenced file/line in the assertion that says that "C state demotion must be disabled for Raptorlake J0 and Q0 SKUs." So, disabling it. BUG=b:311450057,b:300690448 BRANCH=None TEST=Tested that we didn't hit this assertion on the device after this change Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79855 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12sb/intel/bd82x6x: Remove dummy SOUTH_BRIDGE_OPTIONS Kconfig symbolElyes Haouas
Change-Id: If4ae9c800325f5de8f170f8922bacffad1c9bb20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77532 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-12mb/google/nissa/var/anraggar: add FW config to apply the wifi sarJianeng Ceng
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings. - WIFI_6 for MTK Wi-Fi module MT7921L - WIFI_6E for Intel Wi-Fi module AX211NGW BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-01-12soc/intel/xeon_sp: Allocate resources above 4GArthur Heymans
This makes sure that prefetchable mem64 memory gets allocated above 4G which allows non prefetchable resources to be allocated in the tight window below 4G. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79058 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12device/Kconfig: Add an option to allocate above 4G by defaultArthur Heymans
Historically resource allocation in coreboot was 32bit x86 thing. To remain compatible with this behavior (e.g. to keep 32bit payloads happy), resource allocation limits resources to 32 bits unless explicitly overridden. However this behavior is not always appropriate: e.g. on non x86 platforms the PCIe mem decode window could be above 4G. Another case on x86 is where the decode window(s) below 4G are not adequate for fitting all resources and the payload is 64bit capable (e.g. Linux). This adds a Kconfig flag to override the behavior to limit resources to 32bit by default and to allocate resources according to the real hardware limits. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78331 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-01-12mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324Robert Chen
driver Since DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER value on dedede cannot meet DRIVERS_I2C_SX9324 on nissa, need to update the tuning value. Update proximity sensor fine tune value with quandiso EVT machine. BUG=b:314550601 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and verify p-sensor watch 'cat /sys/bus/iio/devices/iio:device*/*raw' Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-12mb/pcengines/apu2/Kconfig: select HUDSON_FADT_LEGACY_DEVICESFelix Held
The APU boards have an NCT5104D chip on the LPC bus that implements some serial ports that have the legacy IO port interface to the host and doesn't describe this in the ACPI tables, so select HUDSON_FADT_LEGACY_DEVICES to have the corresponding FADT bit set. Since this chip doesn't provide an 8042-compatible keyboard controller, don't select HUDSON_FADT_8042. TEST=Surprisingly, this doesn't seem to make a difference to the Linux kernel; is creates all ttyS[0..3] devices with and without this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8872b8c3d6e0610630ba17a0fccdcf8cebb1d3c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-12sb/amd/pi/hudson/Kconfig: replace HUDSON_LEGACY_FREE optionFelix Held
HUDSON_LEGACY_FREE controlled both if the legacy devices and the 8042 flags are set in the IA-PC boot architecture filed of the FADT. Since some systems have legacy devices on the LPC bus, but no 8042-compatible keyboard controller, replace this option with the two new options HUDSON_FADT_LEGACY_DEVICES and HUDSON_FADT_8042. TEST=The FACP table doesn't change on APU2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ff85630c90fb2ae8c8826bbc9049a08668210d Reviewed-on: https://review.coreboot.org/c/coreboot/+/79893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-11cpu/x86/smi_trigger: use call_smmFelix Held
Use call_smm instead of writing the command number directly to the APMC SMI command IO port. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iefbdb3d17932d6db6a17b5771436ede220c714fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/79828 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11arch/x86/include/smm_call: improve documentation of call_smmFelix Held
Since the inline assembly code in call_smm doesn't make it exactly obvious how this function to call the APMC SMI handler works in detail, add a more detailed explanation as comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3566af191492ce00a3033335ff80e01c33e98e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11arch/x86/include/smm_call: use pm_acpi_smi_cmd_portFelix Held
Use pm_acpi_smi_cmd_port() to get the APMC trigger IO port instead of using the hard-coded APM_CNT define. This makes sure that the correct APMC IO port will be used even when a system doesn't use the default APM IO port. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb79c91cfcd75db760bd80cff7f3d0400d1f16cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/79568 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11drivers/smmstore/ramstage: use call_smmFelix Held
Use call_smm instead of open-coding the same in inline assembly functionality in init_store. The local ebx variable is dropped, since call_smm takes a pointer to the argument instead of an integer, and the local eax variable is renamed to res to make the code a bit clearer, since the EAX register is used for both passing the command and subcommand to the APMC SMI handler and to get the return value from the handler. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>