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We test for it in xcompile and add it to CFLAGS.
Change-Id: I041a881b542bc55c1725af384f038da3356e3bb1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10426
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The input/output value max is no longer used for tracking the
bus enumeration sequence, everything is handled in the context
of devicetree bus objects.
Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8541
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ifd277992a69a4182e2fac92aaf746abe4fec2a1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8540
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib33d3363c8d42fa54ac07c11a7ab2bc7ee4ae8bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8539
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Parameter max is the cumulative number of PCI buses scanned on the
system so far. Use the property subordinate from the parent PCI bridge
device to keep track of the first available bus number instead of
passing that on the stack.
Change-Id: I1a884c98d50fa4f1eb2752e10b778aea8a7b090a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8537
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I1766c92abe7a74326c49df74ba38930a502fcb5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8536
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For the PCI root node, input parameter max==0 and output value
max is not relevant for operation.
Change-Id: I23adab24aa957c4d51d703098a9a40ed660b4e6c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8855
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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The actual use of the parameter max is to keep track of PCI bus
number while recursively scanning PCI bridges or PCI-e rootports.
Neither CPU, SMBus, LPC or other static buses are involved in this
enumeration, but the way bridge operations were originally designed
forced to pass this argument thru unrelated functions.
Follow-up removes these once the function prototype gets fixed.
Change-Id: Idbc9c515a362c571a1798bb36972058b309c2774
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8535
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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Use of scan_static_bus() and tree traversals is somewhat convoluted.
Start cleaning this up by assigning each path type with separate
static scan_bus() function.
For ME, SMBus and LPC paths a bus cannot expose bridges, as those would
add to the number of encountered PCI buses.
Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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For amdfam10, (ht_c_index > 3) never evaluates true as the code
already has a return for this case above.
Change-Id: Ie90941671e1b2b4f42e2b1b0641ca59334fcf0f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8688
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Allows to remove parameter max from the call, it is not involved
with the unitid assignment.
Change-Id: I087622f4ff69474f0b27cfd8709106ab8ac4ca98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8687
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.
Change-Id: Idcd059f05523916f726b94931c2487ab028b7d72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10409
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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cbfs_get_file_content was replaced with cbfs_boot_map_with_leak but
36f8d27ea9f741e184b76b5f42d7f777f207edc0 failed to get it into account.
Change-Id: I0c7840043b2ea6abaf8e70f4bf1a63c96aedebc1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10403
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ieb6f70f5b2863336bd6143b2dfbb1d67c4c26109
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Makes it cleaner by putting AML into separate file rather than having
an array in C code.
Change-Id: Ia5d6b50ad9dabdb97ed05c837dc3ccc48b8f490f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10385
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This should be an internal selectable variable rather than user-visible config.
Moreover the description is misleading.
This is a typical case of an option "Should it work?" where there is only one
right answer yet we still ask it.
Change-Id: Idc0ce2e1b9f89eddd034966cc877483d994ce0eb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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RELOCATABLE_MODULES controls inclusion of rmodule support but including it
without having anything that uses it is a pure waste of space. So instead
make RELOCATABLE_MODULES be selected exactly when there is something using it.
Change-Id: I377a955f0cd95b0f811b986df287864c3dc9f89a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10377
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As there can be more than one source of firmware assets this
patch generalizes the notion of locating a particular asset.
struct asset is added along with some helper functions for
working on assets as a first class citizen.
Change-Id: I2ce575d1e5259aed4c34c3dcfd438abe9db1d7b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10264
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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One can remove the struct buffer_area and use the region_device
embedded in the struct prog to represent the in-memory loaded
program. Do this by introducing a addrspace_32bit mem_region_device
that can have region_device operations performed on it. The
addrspace_32bit name was chosen to make it explicit that 32-bits
of address space is supported at the max.
Change-Id: Ifffa0ef301141de940e54581b5a7b6cd81311ead
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10261
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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The api to mirror_payload() was changed, but as no board
in coreboot.org selected MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
this issue was missed. Update to using the prog functions.
Change-Id: I4037f5dc6059c0707e1bf38eb1fa3d1bbb408e2a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10260
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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This reverts commit 701211a6e57a17ea861b4ad682dca7416fc9050e.
Change-Id: Ib3e573548bff5c17ab30cfab3d833a2065d689c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10222
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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A new CBFS API is introduced to allow making CBFS access
easier for providing multiple CBFS sources. That is achieved
by decoupling the cbfs source from a CBFS file. A CBFS
source is described by a descriptor. It contains the necessary
properties for walking a CBFS to locate a file. The CBFS
file is then decoupled from the CBFS descriptor in that it's
no longer needed to access the contents of the file.
All of this is accomplished using the regions infrastructure
by repsenting CBFS sources and files as region_devices. Because
region_devices can be chained together forming subregions this
allows one to decouple a CBFS source from a file. This also allows
one to provide CBFS files that came from other sources for
payload and/or stage loading.
The program loading takes advantage of those very properties
by allowing multiple sources for locating a program. Because of
this we can reduce the overhead of loading programs because
it's all done in the common code paths. Only locating the
program is per source.
Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9134
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The RPM initialization Acknowledge is cleared by writing 1
into bit-10 of the RPM_INT_ACK register.
The existing code got it wrong and is writing zero to that bit.
BRANCH=storm
BUG=chrome-os-partner:39231
TEST=with this patch and an RPM firmware update, an SP4 device
survived more than 1000 reboots in a row.
Change-Id: Ibba296ed0571ad9403a0c51c7f82f07f185b4e83
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 13b4a0f093ba652ad6bccdfc4b3686c0741c6fe7
Original-Change-Id: I39e6ea50e0f66b4af68bdb868dd4437c34bb4524
Original-Signed-off-by: Viswanath Kraleti <vkraleti@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/266969
Original-Reviewed-by: Manoj Juneja <mjuneja@qti.qualcomm.com>
Reviewed-on: http://review.coreboot.org/10310
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch provides support for TPM Infineon SLB9670 by adding its
device ID to the list.
BRANCH=None
BUG=chrome-os-partner:40640
TEST=Built and test SLB9670 on SKL U Reference board Fab 2
Change-Id: I2d26fc6c7d074881f2e6189e1325808544b7d26d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c92884be75b631c302801e162292c245ed7bf5d
Original-Change-Id: I4607fc96f70175b2461b40ba61e7a821e187de40
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274053
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10387
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BRANCH=none
BUG=none
TEST=Booted on Oak and confirmed the output cacheable/non-cacheable
string is correct.
Change-Id: I062c1cc384b8cb9d07038399b1bc7ef47d992103
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 45552f95b55cd9fc81817e4ff02c78e885377065
Original-Change-Id: Ie52066dbefd2f54d0746792b89f0b57767811adb
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273994
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: http://review.coreboot.org/10390
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We have observed issues with enabling CONFIG_SMP and adding prints
before MMU is enabled on Tegra-based SoCs. This seems to be related
to the hardware assisted locks and the restrictions laid down by ARMv8
spec.
BUG=None
BRANCH=None
TEST=Boots to kernel prompt on smaug.
Change-Id: I29a52f5a972baf396c01faba3ae3e5ecd27563e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f52ee4b5b2e9b7f54eee0d105cb7e17f9a7e1613
Original-Change-Id: I432895560f468903c7beef00e78b6d38275a619c
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272449
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10311
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The current arm64 MMU interface is difficult to use in pre-RAM
environments. It is based on the memranges API which makes use of
malloc(), and early stages usually don't have a heap. It is also built
as a one-shot interface that requires all memory ranges to be laid out
beforehand, which is a problem when existing areas need to change (e.g.
after initializing DRAM).
The long-term goal of this patch is to completely switch to a
configure-as-you-go interface based on the mmu_config_range() function,
similar to what ARM32 does. As a first step this feature is added
side-by-side to the existing interface so that existing SoC
implementations continue to work and can be slowly ported over one by
one. Like the ARM32 version it does not garbage collect page tables that
become unused, so repeated mapping at different granularities will
exhaust the available table space (this is presumed to be a reasonable
limitation for a firmware environment and keeps the code much simpler).
Also do some cleanup, align comments between coreboot and libpayload for
easier diffing, and change all error cases to assert()s. Right now the
code just propagates error codes up the stack until it eventually
reaches a function that doesn't check them anymore. MMU configuration
errors (essentially just misaligned requests and running out of table
space) should always be compile-time programming errors, so failing hard
and fast seems like the best way to deal with them.
BRANCH=None
BUG=None
TEST=Compile-tested rush_ryu. Booted on Oak and hacked MMU init to use
mmu_config_range() insted of memranges. Confirmed that CRCs over all page
tables before and after the change are equal.
Change-Id: I93585b44a277c1d96d31ee9c3dd2522b5e10085b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f10fcba107aba1f3ea239471cb5a4f9239809539
Original-Change-Id: I6a2a11e3b94e6ae9e1553871f0cccd3b556b3e65
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271991
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10304
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With addition of bl31 and trusty, we need to increase the number of
parsed fw components in vboot to 6.
CQ-DEPEND=CL:273866
BUG=chrome-os-partner:40713
BRANCH=None
TEST=Compiles successfully and vboot finds trusty and bl31.
Change-Id: I3597e98370bbaef4d2e563c868eed59b2e18adca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ff87fdbc7779e6ee410905d1618281411b38a93
Original-Change-Id: Ia403f895b50cc5349bb700d01f62e13c679f68f4
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273865
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10391
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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They're not referenced in the code anywhere.
Change-Id: I4805e11523ca7d3cffb484c719f479b7a6ba3e15
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10384
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I79fd4d17b534274b1e84bc97ca5a2a6ee55e3114
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10383
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Only define the ASSERT macro when it is not already defined. This
change allows the UEFI/FSP definitions to be included with most other
coreboot includes.
BRANCH=none
BUG=None
TEST=Build and run on sklrvp
Change-Id: Iccfeb83eb1e52623ae0a0fe2a96b587ce61f82d7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10334
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch provides support for TPM Infineon TT1.2
devices by enumerating the TT1.2 ID in the Infineon
device list.
BRANCH=None
BUG=None
TEST=Built for sklrvp and tested on RVP3.
Change-Id: I9daecc09311477fd9947e829d80abc040b2c9e3d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ff86f96cb3e2f203dbc86e7004f1a037b98b90a
Original-Change-Id: I8b59eba348fc44632e22600646eb0b10eb2f4901
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/271256
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/10302
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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Current TPM driver does not support multiple devices for
a given vendor. As the device object never takes the 2nd
ID in the list. This patch fixes the same.
BRANCH=None
BUG=None
TEST=Built for sklrvp and tested on RVP3.
Change-Id: I82c3267c6c74b22650fc53dc6abdc2eb3daa138e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ff42613f11b4f1a79e907601f1ecb7b83a3aeaab
Original-Change-Id: Ieb44735c37208bfe90a8e22e0348dd41c8c642d2
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/271727
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Commit-Queue: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Reviewed-on: http://review.coreboot.org/10303
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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Change-Id: I106779571df5168ec358ad1cc4dc4195639a7a7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10359
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I867932db4388eb078b69b6f42c82967777d45d79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10358
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I35244ebd56e1653109f7cf68ed26a42035c17cc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10367
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I0c20b674b536a2964962f84228f681b53dc114dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10366
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I6416cd5780fbda0b3c2e236ce98a9f9a508e70c6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10293
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
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Change-Id: I231e59d3b9c3ebf6e058917613221892fc880fa1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10365
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ie9c3ef9fb4b3b2a0450a56e1d752b6509fa72a86
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10364
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Fix up commit c6f6be09 (Support for nehalem northbridge) to follow the
coreboot/Linux kernel coding style.
Change-Id: Ibf4f272ad54e6fef0b297189651f2bcf888b5b26
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10347
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Change-Id: I786dd8295d310bfd21db49cfbe5ea39675b25b68
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10361
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This change makes sure that LPC controller declares resources that it
actually decodes. bd82x6x already does it but i82801gx doesn't leading
to allocator potentially allocating something else to the same range.
Change-Id: Ieca9852e54c08e31d4d41aea97f317d9a6919806
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7662
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Remove dead code and dead includes.
Change-Id: I5564ebfbbef6f65c275c2f94f75724f4e36472db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10349
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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PS/2 emulation is part of H8, so should be inited in relevant files.
Change-Id: Ie873ea7f6f88f68f622351799462d0b000d17585
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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nvs.h uses u8 without including stdint.h.
Change-Id: I4ffcbb850cb7b8f47126ee1906b9e0960dd449e8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10331
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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h8.h uses u8 without including stdint.h.
Change-Id: I7e46f6b8ca92ed23af93597fe2f08add464eb176
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10330
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Change-Id: I8e694f37c8709efd702208aa005096ebf1f3abb5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10356
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Timestamps should not be forced on by a subset of chipsets.
However, they are a requirement on Chrome OS platforms, so
have CONFIG_CHROMEOS select it.
Change-Id: I408c6b17aa8721a3abec69020084174e414a8940
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/10357
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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SMM_TSEG now implies SMM_MODULES and SMM_MODULES can't be used without SMM_TSEG
Remove some newly dead code while on it.
Change-Id: I2e1818245170b1e0abbd853bedf856cec83b92f2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10355
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I534f992ed479c7cdc049bd598259b1f1cf2953b9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10354
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This gets rid of ugly tseg_relocate for fsp_bd82x6x.
This is adaptation of a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b
Change-Id: I4e80e6e98d3a6da3e3e480e9368fae1b3ed67cd6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10353
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This gets rid of ugly tseg_relocate for ibexpeak.
This is backport of 29ffa54969414b833de5c61b507b061f920d650b to ibexpeak.
Change-Id: I456d85abdbadb2fdccf77ca771e2518cf8b8c536
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10352
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This gets rid of ugly tseg_relocate for bd82x6x.
This is backport of 29ffa54969414b833de5c61b507b061f920d650b to bd82x6x.
Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Previously only internal mic really worked but since it's of good quality
it's not really noticeable.
Change-Id: Ie14c377b0370302d97e1f89eae5787e05e73b7d2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10286
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
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Not used anywhere.
Change-Id: I9bab092d285aaebdf9283ba08e23197f9785b3a6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
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Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.
Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7472
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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This allows SeaBIOS to fill it as necessary.
This is needed to make BitLocker work.
Change-Id: I35858cd31a90c799ee1a240547c4b4a80fa13dd8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10274
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.
Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10322
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Just not exporting TPM isn't good enough as it can still be accessed.
You need to send it a deactivate command.
Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10270
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This allows to deactivate TPM on X201.
Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10278
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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This allows to deactivate TPM on X230.
Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10273
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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This allows to deactivate TPM on boards using native sandy/ivy init.
Change-Id: I9455179c7b51097a3a9554c16a407365fbc65e6f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10272
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Did we not get rid of this in 2011?
Change-Id: I82cd7f0989e5d38e4a3b0067e471f7acdfd47543
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10321
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I54a4719c571e18eb38a47e50ea69a4a85195d4dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10320
Tested-by: build bot (Jenkins)
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There is no need to backup VolatileStorage in SPI flash at all.
At the time we need it, we have CBMEM available.
Change-Id: If0ca57b314140a833d6d59fe9e236e07816f05a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10317
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Use separate CBMEM allocations for stack and heap on S3 resume path.
The allocation of HIGH_SCRATCH_MEMORY is specific to AGESA and is moved
out of globals and ACPI. This region is a replacement for BIOS_HEAP_SIZE
used on non-resume paths.
Change-Id: I6658ce1c06964de5cf13b4e3c84d571f46ce76f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10316
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This function is required to be implemented by SoC only if some
platform specific parameters are to be passed in from the early
bootloader to bl31 component.
BUG=chrome-os-partner:40414
BRANCH=None
TEST=Compiles successfully.
Change-Id: I6e76a0b6735267971e12aa72a987e8d83f5ad102
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ab8bc12ffc2ee5bf69cef68bae852dcbf7ccb98
Original-Change-Id: If55aaee8d18a8045a5d842145c0e2c97a37a8bca
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272377
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10308
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Each SoC should have a BL31_MAKEARGS += ... defining all the make
arguments required for bl31 component compilation.
BUG=chrome-os-partner:40414
BRANCH=None
TEST=Compiles successfully and boots into bl31.
Change-Id: I20383ab61d012f7294d969f196044a5f1c07dfc1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 72bd297994248a9d96acc6f21d06bb6ff0d5292c
Original-Change-Id: I1ddd5c38e9214021d857d9d586310e23fa4114e0
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272430
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10309
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=chrome-os-partner:40414
BRANCH=None
TEST=ATF compilation successful
Change-Id: Ib4eeced911181f756bd47c19eeb2d196ab5a0a2f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3061a219c24294a9fec4f26fc60b02f67bb55d66
Original-Change-Id: I39849d4048d7333eeab9bd698b4fd496181081a2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272374
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Brain doesn't have HOST1_PWR_EN (GPIO0_B3) and 5V_DRV (GPIO7_C5).
The only USB power enable pin connected to the AP is USB2_PWR_EN
(GPIO0_B4) which controls power for both the physical type-A ports.
BUG=none
BRANCH=none
TEST=built and booted on Brain, both USB host mode ports work
Change-Id: Iea371926c7dcd111aa2e671a15fe97a3519bfc04
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4db71095a5116666cd27aedb09b4f02557362346
Original-Change-Id: Ibbb4b9b424156eb3db1ccfdd948050c1c067ad3c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271309
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@google.com>
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Now that vboot is using offsets for everything remove the
pass through vboot_get_region() and use region_devices
as first class citizens.
Change-Id: I1a86f3725e5bce38e6ca31e9641b1a8f4ac50e96
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10225
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Instead of being pointer based use the region infrastrucutre.
Additionally, this removes the need for arch-specific compilation
paths. The users of the new API can use the region APIs to memory
map or read the region provided by the new fmap API.
Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Because of the fmap API returning pointers to represent
regions within the boot device a vboot_region structure
was used to track the case where offsets could be pointers
on x86 but not on !x86. Normalize this tracking to use
offsets only as it provides consistency in the code.
Change-Id: I63c08b31ace3bd0e66ebc17e308f87eb5f857c86
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10221
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The CBFS_HEADER_ROM_OFFSET went away. Remove remaining
defintions that are not used.
Change-Id: Ibedce988143f0b7167cea1b27de5b33698b5d82b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The boot_device is a region_device that represents the
device from which coreboot retrieves and boots its stages.
The existing cbfs implementations use the boot_device as
the intermediary for accessing the CBFS region. Also,
there's currently only support for a read-only view of
the boot_device. i.e. one cannot write to the boot_device
using this view. However, a writable boot_device could
be added in the future.
Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10216
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Making large changes in pieces is leading to a little bloat.
Bump up the romstage size temporarily so that jenkins will be
happy.
Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10220
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This avoids the need to supply weak function and avoids associated risks of
forgetting to link in relevant files.
Change-Id: Ie96475babb4aa4ea8db49023af5b31bfa63b21dc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7373
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7367
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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Change-Id: I77276342b3f44c7c845a10682ff1f15599c4c721
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7365
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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Note: apu1c models do not support this. That we expose S3 in
ACPI table while it is not available, is a wider issue to solve.
Change-Id: I9b07550d0523593f51c1882a40cccd783115057b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10315
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ib6ac8ab3aca991fa623fedcd87a20470248d58e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10298
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Separate it to low-memory backup in romstage and MTRR recovery
in ramstage. How much of the MTRR part we really need will be
resolved later.
Change-Id: Ic64b3f74cf6ef0954eda6e84754745de81c465b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8607
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Use function prototypes that match more closely with the structure
of other OEM hooks in agesawrappers.
Change-Id: Id241fdce78a21a5138ef60ac2f841b694da92241
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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This is more agesawrapper-related code than CPU.
Change-Id: I3058ef965a83aed1972e02f0f566f81d5dbd7adf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10295
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Now that the users of cbmem_set_top() always provide a consistent
cbmem_top() value there's no need to have cbmem_set_top() around.
Therefore, delete it.
Change-Id: I0c96e2b8b829eddbeb1fdf755ed59c51ea689d1b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10314
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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On S3 resume, CBMEM_ID_CONSOLE from previous boot is found in ramstage,
even when romstage did not create it. So buffer did not get cleared
on S3 resume path.
Also do not allocate for preram_cbmem_console in CAR when there
are no means to back it up to ram.
Change-Id: I175cebbb938adf2a7414703fefffb8da796e9fa9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10301
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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With LATE_CBMEM_INIT, do not search for the initial collection from
CBMEM in ramstage. On S3 resume this would find the non-empty
collection from previous run of ramstage. Start with an empty table
instead.
Remove a spurious error message as the stamps get stashed and
will be copied to CBMEM later.
Change-Id: Ib94049531c0ac23af25407bd2ca7644ee0163d69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10300
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Implementation for cbmem_find() did not work for boards without
EARLY_CBMEM_INIT in romstage.
This is required for S3 resume to work on AGESA plaforms.
First broken with commit 0dff57d
cbmem: switch over to imd-based cbmem
Change-Id: I9c1a4f6839f5d90f825787baad2a3824a04b5bdc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10299
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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For x86 systems employing CONFIG_LATE_CBMEM_INIT, set_top_of_ram() is
called in ramstage to note the upper address of the 32-bit address
space. This in turn is consumed by cbmem. However, in this scenario
cbmem_top() cannot always be relied upon because get_top_of_ram()
doesn't return the same value provided to set_top_of_ram().
To fix the inconsistency in ramstage save the value passed in
to set_top_of_ram() and defer to it as the return value for
cbmem_top().
Change-Id: Ida796fb836c59b9776019e7f8b3f2cd71156f0e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10313
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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The __console attribute as well as linker binding
was dropped at some point. Kill of the dead code and
infrastructure.
Change-Id: I15e1fb4468fffe2e148ec9ac8539dfd958551807
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10279
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Old file defines wrong PCI devices (1.2 2.2 3.2 4.2 5.2).
Wrong defines cause PCI devices not to be found in the pirq_data table.
Example error output:
PCI IRQ: Found device 0:02.01 using PIN A
PCI Devfn (0x11) not found in pirq_data table
PCI IRQ: Found device 0:02.02 using PIN B
Found this device in pirq_data table entry 3
Orig INT_PIN : 2 (PIN B)
PCI_INTR idx : 0x02 (INTC# )
INT_LINE : 0xA (IRQ 10)
PCI IRQ: Found device 0:02.03 using PIN C
PCI Devfn (0x13) not found in pirq_data table
PCI IRQ: Found device 0:02.04 using PIN D
PCI Devfn (0x14) not found in pirq_data table
PCI IRQ: Found device 0:02.05 using PIN A
PCI Devfn (0x15) not found in pirq_data table
Patch fixes, that pirq_data entries for pci devices 2.1 - 2.5 get found.
Change-Id: I4503433427f4ec90d022b65084c52077ba4f3511
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10289
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
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This should be overriden by mobo even if it's no-op override.
weak function in this case would only hide real problems.
Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Export SLIC table from file in CBFS.
Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7202
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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The comment about necessity of include isn't true anymore as get_cst_entries
is not weak anymore so if it's not found, the linking would fail.
Change-Id: I4bf88208d63ac3e625f464c3907e2e1ea575dd9f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7375
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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All boards now use per-device ACPI. This patch finishes migration
by removing transitional kludges.
Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7372
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This code in reality just describes the southbridge features, don't put a copy
in every mainboard.
Change-Id: I8cf3019a36b1ae6a17d502e7508f36ea9fa62830
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10231
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
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Some missing static declarations and whitespace on the console.
Change-Id: I1af59dbfb1396297bd671b43d9326dffdd7f59d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10284
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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