summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-02-22soc/amd: Move root complex SSDT TOM1/TOM2 generation functionRaul E Rangel
This will also be used for cezanne. Stoney also has a similar function, but it hard codes the scope path. I didn't have a device setup to test if switching to this function was a no-op. So I left it. TOM2 isn't used by any ASL, so we could remove it later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-22soc/amd/cezanne/acpi/soc.asl: Add platform.aslRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22soc/amd/cezanne/acpi: Add MMIO devicesRaul E Rangel
The devices were copied from picasso with the following modifications: * UART{2,3} were deleted * I2C{0,1} were added * eMMC was removed since it hasn't been validated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22mb/google/guybrush: Enable console UARTMathew King
BUG=b:180530492 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable guybrush variantMathew King
Enable the building of guybrush variants and configure the first variant also called guybrush. BUG=b:180419462 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable ACPI tablesMathew King
BUG=b:180419454 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-22mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17Subrata Banik
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22mb/google/dedede/var/drawcia: Configure IRQ as level triggered for elan_tsWisley Chen
Follow elan's suggestion to configure IRQ as level trigger. BUG=b:180570924 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I292670580b4c2c18ed0c20a9fbb4ad4289f4eca6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22nb/intel/ironlake: Do not call `collect_system_info` twiceAngel Pons
Move wait for TXT and early ME init out of `collect_system_info`, and then drop the first call to it. Also drop a useless register read. Tested on out-of-tree HP 630, still boots. Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/intel/xeon_sp: Define all SMI_STS bitsAngel Pons
As per document 336067-007US (C620 PCH datasheet), add macros for all bits in the SMI_STS register. These will be used in common code. Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22arch/arm/armv7/thread.c: Remove stale fileAngel Pons
This file is never built. Plus, `CONFIG_STACK_BOTTOM` does not exist. Change-Id: I111b20e3443dca701ee8666d44261a00a161d83f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-22mb/amd/padmelon: Drop unnecessary `PADMELON_SOC_IN_USE` optionAngel Pons
The SoC can be selected in the corresponding option choices directly. Change-Id: I226c500dd7370f4610b0117a9e70d727f1d66951 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22mb/google/oak: Clean up TPM KconfigAngel Pons
Rowan was the only Oak variant that used TPM2. However, it was removed in commit 0aa1f9e905 (google/oak: Delete rowan). Since the other three variants use TPM1, remove now-unnecessary Kconfig options from Oak. Change-Id: If19df00463f63f1101475f59b5ecea5a9724a9ab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-22mb/intel/harcuvar: Drop build guards for ENABLE_FSP_MEMORY_DOWNAngel Pons
Ensure the code gets build-tested for CONFIG_ENABLE_FSP_MEMORY_DOWN=n. Change-Id: I6213e3e0ea3b2acfc97017739ac069ee3811d742 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-22mb/amd/padmelon: Replace `HAVE_S3_SUPPORT` symbolAngel Pons
Replace it with `HAVE_ACPI_RESUME`, which defaults to n for this board. Change-Id: Ibb07c0d001ded8d7ff991bf63607872bf4b79c8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo
CrashLog is a diagnostic feature for Intel TGL based platforms. It is meant to capture the state of the platform before a crash. The state of relevant registers is preserved across a warm reset. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-22soc/rockchip/rk3399/sdram: Remove superfluous parameterMoritz Fischer
Remove extra parameter in phy_dll_bypass_set, since it does not depend on the channel at hand. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: Iae09a6053daf58bf12604e1903c754dc9f1e986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-22mb/google/zork/var/vilboz: adjust USB phy settings for all USB portsFrank Wu
Sometimes the USB device will be lost after DUT resume. Adjust USB phy settings for all USB ports to fix the failed symptom. BUG=b:174538960 BRANCH=zork TEST=USB devices stay connected after running suspend test Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/intel/shadowmountain: Add the romstage codeV Sowmya
This patch includes the romstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early ramstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-21mb/: Drop the provided name in chip_opsKyösti Mälkki
Little point to replicate a string already provided both as a global Kconfig and global mainboard_part_number. Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2021-02-20mb/lippert/frontrunner-af: Split sections from dsdt.aslKyösti Mälkki
Added file acpi/sleep.asl is really a copy from persimmon with debug statement and some comments removed. Added file acpi/gpe.asl is slightly modified copy from persimmon with changes that seem valid, considering the other changes present in ASL for the board. Rename existing usb.asl to usb_oc.asl for consistency. Change-Id: I493ad1c110380378bad80e49cd888f47fbe41a92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA fam14 boards: Drop _SI scope with _SST in ASLKyösti Mälkki
Change-Id: Ieb2f7a6b2721ddeef6945c3e0a0f4cc5627dd533 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA,binaryPI boards: Drop _SI scope with _SST in ASLKyösti Mälkki
Change-Id: I0fca35753c93ba928a0f67bb68a6cfdc26c0e756 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20ACPI: Use common OperationRegion for PCI_MMCONFKyösti Mälkki
Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20AGESA,binaryPI boards: Move common PCBA in ASLKyösti Mälkki
Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA,binaryPI boards: Drop unused variables in ASLKyösti Mälkki
Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA fam14 boards: Move include for usb_oc.aslKyösti Mälkki
Do this for consistency with later platforms. Change-Id: Ia4903b40a8f617c59868aaa116115fa23603438c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20sb,soc/amd: Drop OSFL method in ASLKyösti Mälkki
Variable OSVR had a static value of 3 and OSFL() did not actually call _OSI or _OS methods. The conditional in HDA _INI method of OSVR is dropped and use of DMA NoSnoop attribute remains disabled to retain previous behaviour. For soc/amd/picasso a different decision was made in CB:40782 as HDA _INI method was just dropped and default configuration enables use of DMA NoSnoop attribute. Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20sb/amd/cimx/sb800: Drop OSFL method in ASLKyösti Mälkki
Method only set variable OSRV, which nobody evaluates. Change-Id: Ia21b544eaaa61a8fc634eb568b4c7401a225eb76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20soc/amd/stoneyridge: Fix _INI method in SSDT for HDAFurquan Shaikh
CB:40785 ("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") moved the HDA device in ACPI from DSDT to SSDT. During this, _INI method generated in SSDT incorrectly inverted the values for NSEN, NSDO and NSDI. This change fixes the mistake so that the _INI in SSDT matches the original _INI in DSDT for HDA device. Change-Id: I294b561a479b77ab8afb5f3e0de367ad24f3a764 Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20soc/intel/cannonlake: Add devicetree setting to disable turboPatrick Rudolph
Introduce a new flag to disable turbo called 'cpu_turbo_disable'. Keep the default and enable turbo on all platforms. Change-Id: Ia23ce4d589b5ecc5515474eea52a40788ae3d3b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-02-20drivers/generic/bayhub_lv2: remove unnecessary configsVictor Ding
coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related bits in "Link Capability Register" and "L1 PM Substates Capabilities Register". coreboot overrides these configs even if the driver sets them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is redundant and useless. BUG=b:177955523 BRANCH=zork TEST="lspci -vvvv" prints are identical with and without this patch; LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch. Signed-off-by: Victor Ding <victording@google.com> Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20drivers/generic/bayhub_lv2: move the driver to ".enable"Victor Ding
coreboot sets up certain configs (e.g. L1ss) based on the device's reported capacities; however, this BayHub lv2 driver modifies some of its capacities after coreboot uses them. Therefore, coreboot may make incorrect configs based on out-of-date capacities. This patch moves the driver from ".init" to ".enable" so that the capacities are set before the rest of coreboot queries them. BUG=b:177955523 BRANCH=zork TEST="lspci -vvvv" reported "PCI-PM_L1.2-" and "ASPM_L1.2-" on L1SubCtl1 of both PCI device "00:01.3" and "02.00.0" Signed-off-by: Victor Ding <victording@google.com> Change-Id: I857b7c7c6732bbd26de561052affa3a3e7e25737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20soc/rockchip/rk3399/sdram: Use rank_mask in WDQL trainingMoritz Fischer
Add rank_mask based on the rank number and iterate based on that rather than iterating all values. Note: LPDDR4 uses a different rank mask. Ported from u-boot. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I1bff9d20d3d66984c49073aa21212708039d578f Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20soc/rockchip/rk3399/sdram: Use rank_mask in CA trainingMoritz Fischer
Add rank_mask based on the rank number and iterate based on that rather than iterating all values. Note: LPDDR4 uses a different rank mask. Ported from u-boot. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I85f449af9f946ad677808800cdbe59e2001202c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50887 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd/common/block/data_fabric: add warning about broadcast readsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1b65ae3dd2b5c8fe7bc29a267d108e4d3a3e567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50883 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd: move SMM finalization to common codeFelix Held
This adds the SMM finalization to Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd/cezanne: add MP init and SMM initializationFelix Held
Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50505 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/rockchip/rk3399/clock: Add rkclk_ddr_reset() functionMoritz Fischer
This adds the rkclk_ddr_reset() function equivalent for the RK3399. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50889 Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/rockchip/rk3399/sdram: Add phy_ctrl_resetMoritz Fischer
Add support for resetting PHY PCTRL for both channel 0 and 1. On the ROCKPro64 board this allows getting past a pctl_cfg() failure. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890 Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/rockchip/rk3399/sdram: Clear PI_175 IRQs in data trainingMoritz Fischer
Clear PI_175 interrupts before attempting training in all relevant calls. Ported from u-boot. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50886 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19mb/hp/280_g2: Add new mainboardAngel Pons
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots. There are two possible BOM configurations: Sid has no legacy devices, whereas Manny provides two serial ports, a parallel port, a PCI slot and PS/2 keyboard/mouse connectors. These boards also have different Super I/O models: Manny uses an ITE IT8625E, whereas legacy-free Sid comes with an ITE IT8656E instead. This coreboot port has been done using a Sid board, thus support for Manny-specific features is missing. Booting should still be possible, though: none of these legacy features is essential. The board has an unpopulated 6-pin header, wired to PCH UART 2. This can be used to retrieve coreboot logs. Working: - Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH) - PCH SerialIO UART 2 to get coreboot logs - Rear USB ports - Realtek RTL8111 GbE NIC - Integrated graphics on DVI with libgfxinit - At least one SATA port - Flashing internally with flashrom - S3 suspend/resume - VBT - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1) Untested: - Audio - VGA: DP2VGA chip uses DDI E, and libgfxinit doesn't support DDI E yet - Front USB headers - Non-Linux OSes - PCI slot - IT8625E peripherals: serial, parallel and PS/2 ports Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48386 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19mb/google/guybrush: Enable CONFIG_CHROMEOSMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50507 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSRFelix Held
The new name is more consistent with the rest of the MSR definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19memlayout: Store region sizes as separate symbolsJulius Werner
This patch changes the memlayout macro infrastructure so that the size of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx) is stored in a separate _xxx_size symbol. This has the advantage that region sizes can be used inside static initializers, and also saves an extra subtraction at runtime. Since linker symbols can only be treated as addresses (not as raw integers) by C, retain the REGION_SIZE() accessor macro to hide the necessary typecast. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-19mb/google/mancomb: Add new mainboardMathew King
Mancomb is a new Google mainboard with an AMD Cezanne SOC. BUG=b:175143925 TEST=builds Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19mb/prodrive/hermes/eeprom: Add function to read HSI from EEPROMPatrick Rudolph
Will be used to determine the board revision. Change-Id: I41e4c6ad83e23c9d79e6abab3f38ad46bd3bec06 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50788 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19mb/prodrive/eeprom: Add BMC settingsPatrick Rudolph
Add settings describing the BMC. Will be used by the following patch to read the board revision. Change-Id: If464138fc1bdf02a45a21f638b179048d68d974d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50787 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18mb/google/brya: Enable MLB USB Type-A PortTim Wawrzynczak
The USB Type-A port on the MLB was added to the schematic at the last minute and it was missed when adding brya0's overridetree. Also fix a few USB ACPI entries. BUG=b:180403898 TEST=`lsusb` shows plugged-in flash drive Change-Id: I8bf96a8b365cb4ea2fc07d7cf673b08e8872ff88 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18soc/intel/common: Drop unused `fast_spi_flash_read_wpsr` functionAngel Pons
Also remove one macro that was only used inside that function. Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18soc/intel/common/block/fast_spi: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-18drivers/i2c/hid: Enforce level triggered IRQ modeKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. This change ensures that the IRQ is appropriately configured. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild. Build and boot to OS in Dedede. Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18lib: Add DDR5 DRAM typeSubrata Banik
TEST=Not seeing default msg "Defaulting to using DDR4 params." with this CL. Change-Id: Ib751396ec74b1491fd08b88b07462b315c4a152d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50745 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/rockchip/rk3399/sdram: Move WDQL training into a separate functionMoritz Fischer
Move WDQL training into its own function to enable better error handling. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I8544d6956ca1ce655093a549e7d2928ac9b279bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/50865 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/rockchip/rk3399/sdram: Move RL training into a separate functionMoritz Fischer
Move RL training into its own function to enable better error handling. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I02ffbd9deb3fff3bfd8d6e28d6e6d84a4b8c39ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/50864 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/rockchip/rk3399/sdram: Move RG training into a separate functionMoritz Fischer
Move RG training into its own function to enable better error handling. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I12f17123bc963ffa2dec1559343a141406a5e98d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50863 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/rockchip/rk3399/sdram: Move WL training into a separate functionMoritz Fischer
Move WL training into its own function to enable better error handling. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I7917846c51982a2473f11d14c51c270e59e59d74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50862 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/rockchip/rk3399/sdram: Move CA training into a separate functionMoritz Fischer
Move CA training into its own function to enable better error handling. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: Iefaec3121afbb3b29858e03f903d2ffc5ac75da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50861 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/rockchip/rk3399/sdram: Order and group tsel variablesMoritz Fischer
Order and group tsel variables in a meaningful way. No functional changes. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I417e0fbc129c2d9ad1b345bcff2e25ca6eca83bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50866 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/rockchip/rk3399/sdram: Shorten sdram_params to paramsMoritz Fischer
This shortens the use of sdram_params variable names to params. No functional changes. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I122035078ce37fe65b16bb1f3a2b2d58956431aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/50860 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18mainboard/pine64/rockpro64: Add initial ROCKPro64 supportMoritz Fischer
This adds initial support for the Pine64 ROCKPro64 board. The ROCKPro64 (http://pine64.org/rockpro64) is a SBC using the RK3399 SoC with up to 4GB LPDDR4. So far only the bootblock part works, the romstage starts to execute, though. For ramstage to work we'll need to port some of the changes required for LPDDR4 vs LPDDR3. This will be addressed in follow up changes. UART2 on the PI-2 connector can be used as a coreboot console. GND is pin 6 TXD is pin 8 RXD is pin 10 Flashing: I used an OpenWRT nightly for the ROCKPro64 and its builtin tool. $ mtd write coreboot.rom /dev/mtd0 Recovering from a bad flash: To recover from a bad flash bridging pins 23 and 25 on the PI-2 connector will make the board boot from SD card. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I47d0031fff8ee10b11ad74935eaeb05f1f7eb4b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50625 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/common/block/data_fabric: fix data_fabric_write32 broadcast caseFelix Held
Calling data_fabric_write32 with BROADCAST_FABRIC_ID as instance_id would have caused an infinite recursion, so call the right function data_fabric_broadcast_write32 for that case instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7f0a80f0430e8bfb29ee510ef86c278e3a42063 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-18nb/intel/pineview: Drop unused `GPIO32` macroAngel Pons
It's not used, and GPIO registers are on the southbridge. Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45423 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400Angel Pons
The 100 MHz reference clock seems to be unstable when using high multipliers. Use the 133 MHz reference clock instead. Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45503 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18nb/intel/sandybridge: Clean up `dram_freq` functionAngel Pons
The thing that this function initializes is the MPLL (Memory PLL). So, call it by its name. Also add a missing newline in a printk, and update a comment on the callsite of this function. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-18soc/intel/skylake: Move soc_fsp_loadArthur Heymans
Move this function into the compilation unit where it is called. Change-Id: Ia4bdcd545827c2564430521a98246fc96bf0ba92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18southbridge: Ensure common Kconfig gets included lastAngel Pons
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-18src/cpu: Remove unused symbolsPatrick Rudolph
Remove the unused Kconfig symbol CPU_MICROCODE_MULTIPLE_FILES. Change-Id: I18115e07694658a2f77c447d3ab5c899c1bdcc61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18sb/intel/ibexpeak: Drop obsolete SATA register settingsAngel Pons
Code was copy-pasted from older chips and has no effect on ibexpeak. Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47864 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG writeAngel Pons
This write was copied from Sandy Bridge. Neither Haswell reference code nor Broadwell perform this write. Therefore, it seems safe to remove it. Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46994 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18mb/google/brya: Remove `Some generic macros` commentAngel Pons
This comment is useless, and was dropped from the tree in the past. Change-Id: Ie46bf13ec27ff9cd9423795fc170cc7526e18122 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49124 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18sb/intel/lynxpoint: Correct read width in RMW cycleAngel Pons
The register is 32 bits wide, so do not read 16 bits out of it. LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses. Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18commonlib/bsd: Fix direct inclusion of <endian.h>Julius Werner
<endian.h> should never be included directly in commonlib files and should instead be chain-included via <commonlib/bsd/sysincludes.h>. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ibc67ea97da36ec58738236ef22f961d9bbaf8574 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18cbfs: Fix attribute tag printing in cbfs_find_attr()Julius Werner
Attribute tags are defined as hexadecimal constants, not decimal, so it makes more sense to print them like that in error messages as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3a5a6a8c9b8d24e57633595fc47221a483d8593a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4Julius Werner
cbfstool has always had a CBFS_FILENAME_ALIGN that forces the filename field to be aligned upwards to the next 16-byte boundary. This was presumably done to align the file contents (which used to come immediately after the filename field). However, this hasn't really worked right ever since we introduced CBFS attributes. Attributes come between the filename and the contents, so what this code currently does is fill up the filename field with extra NUL-bytes to the boundary, and then just put the attributes behind it with whatever size they may be. The file contents don't end up with any alignment guarantee and the filename field is just wasting space. This patch removes the old FILENAME_ALIGN, and instead adds a new alignment of 4 for the attributes. 4 seems like a reasonable alignment to enforce since all existing attributes (with the exception of weird edge cases with the padding attribute) already use sizes divisible by 4 anyway, and the common attribute header fields have a natural alignment of 4. This means file contents will also have a minimum alignment guarantee of 4 -- files requiring a larger guarantee can still be added with the --alignment flag as usual. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I43f3906977094df87fdc283221d8971a6df01b53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18rmodtool: Make memlayout symbols absolute and do not relocate themJulius Werner
Memlayout is a mechanism to define memory areas outside the normal program segment constructed by the linker. Therefore, it generally doesn't make sense to relocate memlayout symbols when the program is relocated. They tend to refer to things that are always in one specific spot, independent of where the program is loaded. This hasn't really hurt us in the past because the use case we have for rmodules (ramstage on x86) just happens to not really need to refer to any memlayout-defined areas at the moment. But that use case may come up in the future so it's still worth fixing. This patch declares all memlayout-defined symbols as ABSOLUTE() in the linker, which is then reflected in the symbol table of the generated ELF. We can then use that distinction to have rmodtool skip them when generating the relocation table for an rmodule. (Also rearrange rmodtool a little to make the primary string table more easily accessible to the rest of the code, so we can refer to symbol names in debug output.) A similar problem can come up with userspace unit tests, but we cannot modify the userspace relocation toolchain (and for unfortunate historical reasons, it tries to relocate even absolute symbols). We'll just disable PIC and make those binaries fully static to avoid that issue. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic51d9add3dc463495282b365c1b6d4a9bf11dbf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18Revert "soc/amd: Add option to select if SOC supports ESPI sub decode"Felix Held
This reverts commit 64d0ad347b5c9c698547f0ff15779e88a10014f4. In the current revision 3.001 of the PPR #56569 the register exists and the bit definitions match. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18soc/amd/cezanne/root_complex: provide ACPI name in PCI device_operationsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7f17348b1146a07fcb3e905122d7185b60da962f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18soc/amd/cezanne/chip: add soc_acpi_nameFelix Held
We were missing this, so we ran into the scope assert in acpi_device_write_pci_dev for the data fabric PCI devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I566791527ba839ba52ec5fa28f0f6c25f547d1da Reviewed-on: https://review.coreboot.org/c/coreboot/+/50815 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/picasso/chip: remove unneeded functionality in soc_acpi_nameFelix Held
Now that all ACPI names are moved to the corresponding PCI devices, the functionality in the chip code isn't needed any more. TEST=No warnings or errors on coreboot console or in the Linux ACPI parser. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d39b6d4bd53cd0ca189fb6f55ca26dab68793fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50822 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/common/block/iommu: move ACPI name to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f1dce92475ce0ee05a8d090fc3b3d1e613f62c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50821 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/picasso/root_complex: provide ACPI name in PCI device_operationsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5471f7be41683ef4a14107f38e93339080d01bdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50820 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/common/block/smbus: move ACPI name to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I47415be02571240d3cecfdb91cb9f8097c5b7fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/50819 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/common/block/lpc: move ACPI name to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7517d81d41422cfa10fabd12ab3da4f61c3f9034 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50818 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/picasso/chip: make soc_acpi_name staticFelix Held
This function isn't used outside of the same compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I332046341bc7a5a499355f2147296e8c09d7e0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50817 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17vc/google/chromeos: Account for GNVS allocated earlyKyösti Mälkki
We have adjusted allocation order such that GNVS is available before ME hash needs to be stored. Change-Id: I8428dd85f44935938a118a682767f2f8d6d539ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-17vc/google/chromeos: Allocate RAMOOPS lateKyösti Mälkki
The allocation is for the OS. Just need to take care in the firmware that ChromeOS GNVS is allocated first. Change-Id: I16db41b31751d7b4a8a70e638602f3f537fe392e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17soc/intel/alderlake: Fix PCI IRQ tablesTim Wawrzynczak
Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the 2nd field in each package is supposed to be pin, not function number, and some of the IRQ #s differ from what the FSP programs, therefore align the ACPI table to match what the FSP is currently programming. BUG=b:180105941 TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing` errors seen in dmesg Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17mainboard/amd/bilby: Add Bilby CRB boardRitul Guru
Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs. Bilby mainboard code is taken from mandolin variant Cereme. These new files are a renamed copy and subsequent patches will be applied to create a working bilby implementation. Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-17soc/amd/cezanne: Add FCH IO-APIC to MADTRaul E Rangel
TEST=Boot majolica to linux and see IO-APIC logs ACPI: Local APIC address 0xfee00000 ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) ACPI: IRQ0 used by override. ACPI: IRQ9 used by override. Using ACPI (MADT) for SMP configuration information Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib8094c3edf401659d9d740e2cc6266ddd5f91da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-17soc/amd/cezanne/pcie_gpp: add pci_driver for external root portsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic63ca41ae484cc34c560cf78de37dc1cde32f364 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50805 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17soc/amd/cezanne/pcie_gpp: replace PCI ID list with single PCI IDFelix Held
Since all bridges to the internal buses have the same PCI ID, we can just add this one ID to the pci_driver struct and don't need to use a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice024b91f49f03995acbd8dfc8b33d3ae3559dde Reviewed-on: https://review.coreboot.org/c/coreboot/+/50804 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17vc/intel/fsp: Change line endings to unixMartin Roth
These files have windows line endings. Change to unix to match the rest of the tree. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17treewide: Remove trailing whitespaceMartin Roth
Remove trailing whitespace in files that aren't typically checked. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8dfffbdeaadfa694fef0404719643803df601065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17drivers/intel/fsp2_0: Allow larger FSPS UPD than expected in corebootNikolai Vyssotski
Enforcing the exact match of FSPS UPD block size between FSP and coreboot mandates simultaneous updates to coreboot and FSP repos. Allow coreboot to proceed if its UPD structure is smaller than FSP one. This usually indicates that FSPS has an updated (larger) UPD structure which should be soon matched/updated on the coreboot side to keep them in sync. While this is an undesirable situation that should be corrected ASAP, it is safe from coreboot perspective. It is safe (as long as default values in FSP UPD are sane enough to boot) because FSPS UPD buffer is allocated on the heap with the size specified in FSPS (larger) and filled with FSPS default values. This allows FSP UPD changes to be submitted first followed by changes in coreboot repo. Note that this only applies to the case when entire FSPS UPD structure grows which should be rare as FSP should allocate enough reserve space, anticipating future expansion, to keep the structure from growing when new members are added. BUG=b:171234996 BRANCH=Zork TEST=build Trembyle Change-Id: I557fd3a1f208b5b444ccf76e1552e74ecf4decad Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-17soc/amd/picasso/agesa_acpi: add cast before right shiftFelix Held
Without the cast the left shift is done on a 32 bit variable that gets extended to 64 bits afterwards which results in missing MSBs. To avoid this, do the cast to 64 bits before the left shift. Found-by: Coverity CID 1443793, 1443794 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-17mb/prodrive/hermes: Write board layoutPatrick Rudolph
The I2C EEPROM on SMBUS needs to be updated with the current board layout, so that the BMC knows the actual configuration. Collect all needed information and update the EEPROM if something changed. Every byte written add a delay of 5 msec. Change-Id: Ic8485e6c700eede75b1e829238ee70da65118ace Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-17mb: guard irq_tables for clang-formatPatrick Georgi
Some (notably older Intel) boards use a tabular description of irq routing that we want to keep pristine no matter what clang-format considers correct (as that's ugly). Change-Id: I259255a9f60208c659b658ecb81535e84a2aaa8c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-17soc/intel/xeon_sp/smmrelocate: Don't run twice on the BSPArthur Heymans
This only makes sense if relocation via MSR is possible, to relocate APs in parallel. xeon_sp hardware does not support these MSR. TESTED: ocp/deltalake boots fine. SMM is relocated on CPU 0 just like all other cores. Change-Id: Ic45e6985093b8c9a1cee13c87bc0f09c77aaa0d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 01:01:34 +0000