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Adding Touchpad support into devicetree.
BUG=b:177348842
BRANCH=dedede
TEST=touchpad function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I7ecafb5b3e39ff2ed9e176531bd0939f830a6397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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and associated GPIO configuration
Adding camera support in devicetree and associated GPIO configuration.
BUG=b:177351873
BRANCH=dedede
TEST=camera function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I539e969e180c8c71d4b54b50519d2e1ff25415f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Post boot SAI PCR access to ITSS polarity regsiter is locked.
Restore of ITSS polarity does not take effect anyways. Hence
removing the related programming.
Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configuring GPP_G7 as NC causes SD card detection issue.
Remove the GPP_G7 override and keep the baseboard
configuration as native function (SDIO_WP).
BUG=b:179733306
BRANCH=firmware-dedede-13606.B
TEST=Built and verified Kingston 64G SD card operation on boten
Change-Id: Ied319437de0e867ee9821d0151ff0c76834c4726
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This makes it clear what this function pointer is used for.
Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.
Change-Id: I0443a45522b2267e8e23b28e4e2033f25a7ccbf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.
Change-Id: I6888b08ac11ba2431601fa179d063cee0bb93370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.
Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This adds functionality to mask certain IIO errors on the root complex as recommended by HW vendor.
Tested on DeltaLake mainboard. Boot to OS, verify IIO mask registers are programmed correctly.
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Change-Id: I99f05928930bbf1f617c2d8ce31e8df2a6fd15e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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As one option is consumed by MPinit, update the soc config even earlier.
Tested on Prodrive hermes:
Turbo can be disabled and cores won't exceed their base frequency.
Change-Id: I9f444c3b91d2ee1a613ebac1922f1e6b60363c0b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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With an external GPU connected via the expresscard slot this is
required.
Change-Id: I154721ff2c712cfe7eb79b8bf8943182c8c36548
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Let's not have 7 boards of all use a different name for
the .enable_dev function in mainboard chip_operations.
Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The semantics of pirq_setup() from previous platforms was to
only setup the global pointers for PIC and APIC tables, not
to create or modify the tables themselves.
Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not
applicable for SW CM platform at the resume sequence. This change
removes the pollng for "LA == 1" to improve resume performance.
BUG=b:177519081
TEST=Boot to kernel and validated s0ix on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I0e6414f686a995536a0fd8aa0f6f70e5a36718a3
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50992
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust H1 I2C CLK:
404kHz -> 391 kHz
BUG=b:179753353
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: Iedd47dd6fc4f7ac7f0aac480d63ddbdf85a84ec2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Set up EC_IN_RW GPIO in coreboot.
BUG=b:180686277
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: I367f6f17fff3d10be19a83d63e927959068408dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I9b523bda2332859074d2e12c5cb70df68e18063d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I9524a44f8f4b8e286229d81d10704438f11c4580
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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FSP expects mp_get_processor_info to give processor specfic apic ID,
core(zero-indexed), package(zero-indexed) and thread(zero-indexed) info.
This function is run from BSP for all logical processor, With current
implementation the location information returned is incorrect per logical
processor. Also the processor id returned does not correspond to the
processor index, rather is returned only for the BSP.
BUG=b:179113790
Change-Id: Ief8677e4830a765af61a0df9621ecaa372730fca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50880
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support to get core, package and thread ID from lapic ID.
Implementation uses CPUID extended topology instruction to derive
bit offsets for core, package and thread info in apic ID.
BUG=b:179113790
Change-Id: If26d34d4250f5a88bdafacdd5d56b8882b69409e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Bits are already cleared in southbridge_detect_s3_resume().
Change-Id: If8bb85abacd59c7968876906e126300c9e4314e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This helps towards unified chipset_power_state.
Change-Id: I8f152dc9f1e0f26e4777489913e9fb2c9cd3dac0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Let's not have CBMEM hooks in between the different
INITRAM timestamps.
Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I6356bb7ea904ca860cbedd46515924505d515791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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For consistency with other nb/intel rename variable from
wake_from_s3 to s3resume.
Change-Id: If94509c4640f34f2783137ae1f94339e6e6cf971
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.
Change-Id: I34a123f9fc13bd86264317c7762bf6e9ffd0f842
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.
Change-Id: Ida04d2292aabb5a366f3400d8596ede0dee64839
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This helps towards unified chipset_power_state.
Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Samsung K4E6E304EC-EGCG-4GB # 1011
BUG=b:179455694
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass stress test under run-in.
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the UPD size in coreboot sizes mismatches the one from the FSP-M
binary, we're running into trouble. If the expected size is smaller than
the UPD size the FSP provides, call die(), since the target buffer isn't
large enough so only the beginning of the UPD defaults from the FSP will
get copied into the buffer. We ran into the issue in soc/amd/cezanne,
where the UPD struct in coreboot was smaller than the one in the FSP, so
the defaults didn't get completely copied.
TEST=Mandolin still boots.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. GPIO_4 to NC
BUG=b:179333669
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.
BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".
Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EC does not exist in Bilby platform, so removing EC size from board.fmd
and updating bilby fmap size to 0xfef000.
Removing unused EC FW config options MANDOLIN_HAVE_MCHP_FW and
MANDOLIN_MCHP_FW_FILE.
Change-Id: I9ca4e421b0d80d041ed4046fa20cc16e24a776d0
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Calling cbmem_recovery(0) late in ramstage would appear
to remove all CBMEM entries created so far.
Change-Id: I2abb079844c4b41be09354d603ad36e4a56ea2e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 1a25c9cdfd3fd391328133ba94c63ecd1083e4f8.
Reason for revert: No longer necessary.
Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id0c45ff1ee4a2dc4c0f9a82f6a311f7acac156fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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ChromeOS does not compile in CONFIG_OF, so PRP0001 will not successfully
register the device with its driver. Change to GOOG0005 to match other
ChromeOS devices with I2C-connected Cr50 TPM.
BUG=b:180657076
TEST=abuild
Change-Id: Ic1d4eb5e12ea7f7e693f1ffd3848e59668ac2deb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50920
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This differs slightly from picasso. The PCI BAR region is between TOM1
and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms
are doing. It also matches what linux derives from the e820 tables:
> [mem 0xd0000000-0xf7ffffff] available for PCI devices
Picasso currently declares the region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region.
TEST=Boot majolica and check logs
pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window]
pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff]
pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff]
pci_bus 0000:00: root bus resource [bus 00-3f]
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ff02012795e2166e3a4197071b1136727089318
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will also be used for cezanne. Stoney also has a similar function,
but it hard codes the scope path. I didn't have a device setup to test
if switching to this function was a no-op. So I left it.
TOM2 isn't used by any ASL, so we could remove it later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The devices were copied from picasso with the following modifications:
* UART{2,3} were deleted
* I2C{0,1} were added
* eMMC was removed since it hasn't been validated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:180530492
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the building of guybrush variants and configure the first variant
also called guybrush.
BUG=b:180419462
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:180419454
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Follow elan's suggestion to configure IRQ as level trigger.
BUG=b:180570924
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: I292670580b4c2c18ed0c20a9fbb4ad4289f4eca6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.
Tested on out-of-tree HP 630, still boots.
Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per document 336067-007US (C620 PCH datasheet), add macros for all
bits in the SMI_STS register. These will be used in common code.
Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This file is never built. Plus, `CONFIG_STACK_BOTTOM` does not exist.
Change-Id: I111b20e3443dca701ee8666d44261a00a161d83f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The SoC can be selected in the corresponding option choices directly.
Change-Id: I226c500dd7370f4610b0117a9e70d727f1d66951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Rowan was the only Oak variant that used TPM2. However, it was removed
in commit 0aa1f9e905 (google/oak: Delete rowan). Since the other three
variants use TPM1, remove now-unnecessary Kconfig options from Oak.
Change-Id: If19df00463f63f1101475f59b5ecea5a9724a9ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Ensure the code gets build-tested for CONFIG_ENABLE_FSP_MEMORY_DOWN=n.
Change-Id: I6213e3e0ea3b2acfc97017739ac069ee3811d742
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Replace it with `HAVE_ACPI_RESUME`, which defaults to n for this board.
Change-Id: Ibb07c0d001ded8d7ff991bf63607872bf4b79c8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove extra parameter in phy_dll_bypass_set, since it does not
depend on the channel at hand.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Iae09a6053daf58bf12604e1903c754dc9f1e986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Sometimes the USB device will be lost after DUT resume.
Adjust USB phy settings for all USB ports to fix the failed symptom.
BUG=b:174538960
BRANCH=zork
TEST=USB devices stay connected after running suspend test
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch includes the romstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Little point to replicate a string already provided both
as a global Kconfig and global mainboard_part_number.
Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Added file acpi/sleep.asl is really a copy from persimmon with debug
statement and some comments removed.
Added file acpi/gpe.asl is slightly modified copy from persimmon with
changes that seem valid, considering the other changes present in ASL
for the board.
Rename existing usb.asl to usb_oc.asl for consistency.
Change-Id: I493ad1c110380378bad80e49cd888f47fbe41a92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ieb2f7a6b2721ddeef6945c3e0a0f4cc5627dd533
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I0fca35753c93ba928a0f67bb68a6cfdc26c0e756
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Do this for consistency with later platforms.
Change-Id: Ia4903b40a8f617c59868aaa116115fa23603438c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Variable OSVR had a static value of 3 and OSFL() did not
actually call _OSI or _OS methods.
The conditional in HDA _INI method of OSVR is dropped and
use of DMA NoSnoop attribute remains disabled to retain
previous behaviour. For soc/amd/picasso a different decision
was made in CB:40782 as HDA _INI method was just dropped and
default configuration enables use of DMA NoSnoop attribute.
Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Method only set variable OSRV, which nobody evaluates.
Change-Id: Ia21b544eaaa61a8fc634eb568b4c7401a225eb76
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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CB:40785 ("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") moved
the HDA device in ACPI from DSDT to SSDT. During this, _INI method
generated in SSDT incorrectly inverted the values for NSEN, NSDO and
NSDI. This change fixes the mistake so that the _INI in SSDT matches
the original _INI in DSDT for HDA device.
Change-Id: I294b561a479b77ab8afb5f3e0de367ad24f3a764
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Introduce a new flag to disable turbo called 'cpu_turbo_disable'.
Keep the default and enable turbo on all platforms.
Change-Id: Ia23ce4d589b5ecc5515474eea52a40788ae3d3b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related
bits in "Link Capability Register" and "L1 PM Substates Capabilities
Register". coreboot overrides these configs even if the driver sets
them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is
redundant and useless.
BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" prints are identical with and without this patch;
LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch.
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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coreboot sets up certain configs (e.g. L1ss) based on the device's
reported capacities; however, this BayHub lv2 driver modifies some
of its capacities after coreboot uses them. Therefore, coreboot may
make incorrect configs based on out-of-date capacities.
This patch moves the driver from ".init" to ".enable" so that the
capacities are set before the rest of coreboot queries them.
BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" reported "PCI-PM_L1.2-" and "ASPM_L1.2-" on L1SubCtl1
of both PCI device "00:01.3" and "02.00.0"
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I857b7c7c6732bbd26de561052affa3a3e7e25737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.
Note: LPDDR4 uses a different rank mask.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I1bff9d20d3d66984c49073aa21212708039d578f
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.
Note: LPDDR4 uses a different rank mask.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I85f449af9f946ad677808800cdbe59e2001202c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1b65ae3dd2b5c8fe7bc29a267d108e4d3a3e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50883
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds the SMM finalization to Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50505
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds the rkclk_ddr_reset() function equivalent for the RK3399.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50889
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for resetting PHY PCTRL for both channel 0 and 1.
On the ROCKPro64 board this allows getting past a pctl_cfg() failure.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clear PI_175 interrupts before attempting training in all relevant
calls.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50886
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots.
There are two possible BOM configurations: Sid has no legacy devices,
whereas Manny provides two serial ports, a parallel port, a PCI slot
and PS/2 keyboard/mouse connectors. These boards also have different
Super I/O models: Manny uses an ITE IT8625E, whereas legacy-free Sid
comes with an ITE IT8656E instead.
This coreboot port has been done using a Sid board, thus support for
Manny-specific features is missing. Booting should still be possible,
though: none of these legacy features is essential.
The board has an unpopulated 6-pin header, wired to PCH UART 2. This
can be used to retrieve coreboot logs.
Working:
- Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH)
- PCH SerialIO UART 2 to get coreboot logs
- Rear USB ports
- Realtek RTL8111 GbE NIC
- Integrated graphics on DVI with libgfxinit
- At least one SATA port
- Flashing internally with flashrom
- S3 suspend/resume
- VBT
- SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
Untested:
- Audio
- VGA: DP2VGA chip uses DDI E, and libgfxinit doesn't support DDI E yet
- Front USB headers
- Non-Linux OSes
- PCI slot
- IT8625E peripherals: serial, parallel and PS/2 ports
Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48386
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:175143925
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50507
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new name is more consistent with the rest of the MSR definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Mancomb is a new Google mainboard with an AMD Cezanne SOC.
BUG=b:175143925
TEST=builds
Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Will be used to determine the board revision.
Change-Id: I41e4c6ad83e23c9d79e6abab3f38ad46bd3bec06
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50788
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add settings describing the BMC.
Will be used by the following patch to read the board revision.
Change-Id: If464138fc1bdf02a45a21f638b179048d68d974d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50787
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The USB Type-A port on the MLB was added to the schematic at the last
minute and it was missed when adding brya0's overridetree. Also fix
a few USB ACPI entries.
BUG=b:180403898
TEST=`lsusb` shows plugged-in flash drive
Change-Id: I8bf96a8b365cb4ea2fc07d7cf673b08e8872ff88
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Also remove one macro that was only used inside that function.
Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
This change ensures that the IRQ is appropriately configured.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild. Build and boot to OS in Dedede.
Change-Id: I3245a9de6e88cd83528823251083e62288192f0d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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TEST=Not seeing default msg "Defaulting to using DDR4 params." with
this CL.
Change-Id: Ib751396ec74b1491fd08b88b07462b315c4a152d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50745
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move WDQL training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I8544d6956ca1ce655093a549e7d2928ac9b279bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50865
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move RL training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I02ffbd9deb3fff3bfd8d6e28d6e6d84a4b8c39ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move RG training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I12f17123bc963ffa2dec1559343a141406a5e98d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50863
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move WL training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I7917846c51982a2473f11d14c51c270e59e59d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50862
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move CA training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Iefaec3121afbb3b29858e03f903d2ffc5ac75da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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