| Age | Commit message (Collapse) | Author |
|---|
|
Change-Id: I12e6ec4aec7dcadcbb886c3fc4c3b9126a0a835c
Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported
is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of
qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu
via a flag.
To execute:
$ qemu-system-aarch64 -M virt,secure=on,virtualization=on \
-cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic
Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Change-Id: Iaf370e04adb04eb81555a57e81812ebe3339971d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The pinctrl driver in the linux kernel automatically turns off SCI
routing for all GPIOs exported via ACPI, so this patch sets up
dual-routing of the EMR_GARAGE_DET signal so that one can be used
for IRQs and one for the SCI wake.
Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The touchscreen controller was never added to the device tree, and the
next board rev will have this IC connected. Set it up in the device tree
with conservative power resource timings from the datasheet.
BUG=b:138869702
BRANCH=none
TEST=compiles; current board rev does not have touch IC
Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Enabling stylus pen device and pen_eject event.
- Adding enable_gpio for power sequencing
- Configuring GPP_H4 and GPP_H5 as native function
- Adding PENH device node for pen ejection event
BUG=b:137326841
BRANCH=none
TEST=Verified pen input operation and pen_eject event (pop-up and wake
from s0ix on pen ejection)
Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Platform does not set up IED.
Change-Id: Ied72888c6406b59332bc3d68eccb50bf1eab3419
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I361fb0e02fd0bd92bb1e13fe84c898a1ac85aa40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Implementation remains the same.
Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
No need to limit these declarations to FSP. Both
PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE
can be built on top of this.
Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Use a name consistent with the more recent soc/intel.
Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Use a name consistent with the more recent soc/intel.
Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
|
|
Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I471598d3ce61b70e35adba3bd983f5d823ba3816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
FSP1.0 has low memory corruptions below CONFIG_RAMTOP
on S3 resume path, as romstage ram stack will be utilised
before there is a chance to make the necessary backup
to CBMEM.
Previously done for intel/minnowmax in commit b6fc727.
Change-Id: I2e128079b180f9978e8519b190648d516aaee0dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34673
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.
Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and
(unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE.
Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Vortininja needs different SAR values than meep. Use sku-id to load SAR values.
BUG=b:138261454
BRANCH=octopus
TEST=build and verified SAR values by sku id
Change-Id: I7b3ab51e1d6cada4faaba1b9d72bd9eacf6b04dd
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
This patch implements i2c driver for MT8183.
BUG=b:80501386
BRANCH=none
TEST=Boot correctly on kukui.
Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30976
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It fails if you call extract() when ramdisk is present but initrd
size is 0. This CL adds if-statement to throw an error when initrd
size is 0.
Change-Id: I85aa33d2c2846b6b3a58df834dda18c47433257d
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add support for the integrated TPM in Kconfig and update device tree.
Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Change the TPM2 ACPI Table to support CRB Interface when selected.
Change-Id: Ide3af348fd4676f2d04e1d0b9ad83f9124e09dcc
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
When we use Intel Platform Trust Technologies, we need to verify
that the enable bit is set before we use the integrated TPM.
Change-Id: I3b262a5d5253648fb96fb1fd9ba3995f92755bb1
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Add support for Intel PTT. For supporting Intel PTT we need to disable
read and write access to the TPM NVRAM during the bootblock. TPM NVRAM
will only be available once the DRAM is initialized. To circumvent this,
we mock secdata if HAVE_INTEL_PTT is set. The underlying problem is,
that the iTPM only supports a stripped down instruction set while the
Intel ME is not fully booted up. Details can be found in Intel document
number 571993 - Paragraph 2.10.
Change-Id: I08c9a839f53f96506be5fb68f7c1ed5bf6692505
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
When imlpementing changes in VBOOT, within the build process, tegra210
overflows into the romstage. Reduce the size of romstage from 104 to
100 and increase the size from verstage from 66 to 70.
Change-Id: Ie00498838a644a6f92881db85833dd0a94b87f53
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34640
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Increase log level from ERR to CRITICAL in run_ap_work().
* Print or return errors if mp_run_on_all_cpus() failed.
Tested on Supermicro X11SSH-TF.
Change-Id: I740505e3b6a46ebb3311d0e6b9669e7f929f9ab9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch makes SPKR_PA_EN PIN output and high for boot beep
to work in pre-os environment.
BUG=b:135104721
BRANCH=NONE
TEST=Boot Beep is working with required ALC1011 depthcharge code
changes.
Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
|
|
The device Vortininja uses the variant meep, and supports WACOM/EMRIGHT
digitizer.
BUG=b:138276179
BRANCH=octopus
TEST=verified that WACOM/EMRIGHT digitizer can works.
Change-Id: I2bed4edb0261953f122f1d9ccca1fe4fa9406b33
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.
BUG=b:138098572
Test=compiles
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This implementation adds support to provide list of LPSS controllers
for a canonlake and icelake platforms. It implements strong function
of get_soc_lpss_controllers defined under intel common block lpss
driver.
Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add an API to check if device is a LPSS controller. This API can be
used for IRQ assignments for LPSS PCI controllers, since the LPSS
controllers have a requirement of unique IRQ assignments and do not
share same IRQ# with other LPSS controllers.
SOC code is reponsible to provide list of the LPSS controllers
supported and needs to implement soc_lpss_controllers_list API,
in case it needs to use this common implementation.
Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Increase reset delay to 120ms of touchscreen to meet wacom touchscreen
T4 specification and resolve re-bind hid over i2c driver failed after
touchscreen firmware auto update.
BUG=b:132211627
TEST=Stress touchscreen firmware auto update 200 times and not found
re-bind driver failed.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I488660aefdc6df27077efc7fec2f3b99adbaef9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Reviewed-by: Nick Crews <ncrews@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Change-Id: Ic038adad6cf76867cd4a8626d4c49e17018389fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Icf802904c569e621ca3b3105b6107936776c5cee
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31458
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This code was only used by allwinner CPUs which is removed at this
point.
Change-Id: I31a2a502bffdc605cc31127723ed769b8665c314
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Allwinner code was never completed and lacks a driver to load
romstage from the bootblock.
Change-Id: If2bae9e28a6e1ed6bfe0e9cb022ca410918cc4db
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33133
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Allwinner code was never completed and lacks a driver to load
romstage from the bootblock.
Change-Id: I12e9d7213ce61ab757e9317a63299d5d82e69acb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33132
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Kaby, Coffee and Whiskey Lake are all supported by the same code
path in libgfxinit.
TEST=Played Tint on clevo/kbl-u(n130bu).
Change-Id: Ic911bda3dd62c4d37a1b74a87fb51adc6c9d6ad4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31464
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested on SiFive/unleashed:
Boots into Linux until earlycon terminates.
Change-Id: I35abacc16f244b95f9fd1947d1a5ea10c4dee097
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34142
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This implementation revises the UART PCI device reference in common
UART driver. The SOC functions have been aligned to provide the UART
PCI device reference using pcidev_path_on_root.
The uart_get_device() return type is changed, and files in which
it gets used are updated.
Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Commit 509f469 [drivers/fsp1_1/raminit.c: Always check FSP HOBs]
inadvertently made use of the mrc_hob conditional on
CONFIG_DISPLAY_HOBS, when there is no relation between the two,
leading to MRC cache data being corrupted. On some devices this
caused RAM training to be redone, on others it resulted in a
bricked device.
Fix this by removing the condition on CONFIG_DISPLAY_HOBS.
Test: boot google/{cyan,edgar}, observe third boot and onward do not
brick device, properly use mrc_hob via cbmem console and timestamps.
Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34685
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The cache is at the end of TSEG. As SMM_RESERVED_SIZE was
half of TSEG size, offseting from the start gave same
position.
Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.
Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.
Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.
Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE.
Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
After adjustment
Touch Pad CLK: 383.4 KHz
Touch Screen CLK: 381.6 KHz
Audio codec CLK: 386.0 KHz
TouchPad SDA hold time: 0.325ns
BUG=b:137722634
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage
Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
droid/blorb needs to use different SAR values than bobba. Use sku-id to load the SAR values.
BUG=b:138091179
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34542
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
smbios.h had already declared smbios_mainboard_enclosure_type so this
change defines it. It can be overridden in a mainboard so the enclosure
type can be set at runtime.
We have a mainboard that will be used in different enclosures and we are
planning on using a single BIOS image for all of the enclosures so it
will need to be set dynamically based on sku.
BUG=b:138745917
TEST=Built arcada firmware and verified via dmidecode that enclosure type
is correctly set to "Convertible", then temporarily added a
smbios_mainboard_enclosure_type to arcadas board file returning
0x20 and verified with dmidecode that the enclosure type is
"Detachable"
Change-Id: Iba6e582640989f5cb7e6613813e7b033760a977c
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Tested on qemu-riscv:
Boots into Linux until initrd should be loaded.
Change-Id: I4aa307c91d37703ad16643e7f8eb7925dede71a8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the
platform. It will also jump to the specified payload when done.
This behaviour is similar to BL31 on aarch31.
The payload is 41KiB in size on qemu.
Tested on qemu-riscv:
Required to boot a kernel as OpenSBI's instruction emulation feature
is required on that virtual machine.
Tested on SiFive/unleashed:
The earlycon is working. No console after regular serial driver
should take over, which might be related to kernel config.
Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
BRANCH=none
BUG=b:138152075
TEST=Build for cometlake board with the PmTimerDisabled policy in
devicetree set to 1.
With PmTimerDisabled = 0
>> iotools mmio_read8 0xfe0018fc
0x00
With PmTimerDisabled = 1
>> iotools mmio_read8 0xfe0018fc
0x02
Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines
whether the ACPI Timer is enabled to run.
- 0: ACPI Timer is enabled
- 1: ACPI Timer is disabled
Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
|
|
Caller needs to take into account that bus numbers may
have not been assigned yet. Same issue existed before
with early ramstage and mostly does not cause problems
when used with static devices on bus 0.
Change-Id: I4865b4277dbc858c8c2ffd2052defcaa1a92173c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34614
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Constify the struct device arguments in below APIs:
> acpi_device_name
> acpi_device_path_fill
> acpi_device_path
> acpi_write_dbg2_pci_uart
> acpi_device_scope
> acpi_device_path_join
The APIs do not seem to modify the argument and are using
device argument as reference to device only.
Change-Id: Ic2ce045f17efa288eb41503795723d0ad5ec78bd
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34625
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add rise time / fall time to I2C config in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
BUG=b:138258384
BRANCH=none
TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run
at 395-399 kHz.
Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34559
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This function can capture and allocate its own eye data, so in that case
set need_free to true so it is freed at the end.
Change-Id: I63ca6d743e6610d3e3ab6bd7b0356aabdfa6f784
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1393969
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Accessing the higher vidtcon variables using pointer arithmetic from the
lower address FIMD_CTRL struct is undefined behaviour, since pointers
manipulations are not allowed outside the objects they point to. The
standard-blessed way is to perform the arithmetic using integer
addresses first, and then convert that to a pointer. The end result is
the same, but avoids the risk of unsafe optimizations from an
over-zealous compiler.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402096, 1402124, 1402131, 1402169
Change-Id: I13ed23836e8e9076ae0bfd88c05c4f2badac9c49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Refactor I2C code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot
Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c
Signed-off-by: qii wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Add a check to enable ACPI timer emulation only when the APCI PM timer
is disabled.
Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Added for symmetry with other stage_cache_add()
command variants, currently for amd/stoneyridge.
Change-Id: I580054104a61f1b03ba36a7c97ad4411c3d29855
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34651
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch overrides EnableTcoTimer FSP UPD default value based on
PmTimerDisabled coreboot devcietree config.
BRANCH=none
BUG=b:138152075
Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
|
|
This patch moves SOC_INTEL_COMMON_BLOCK_THERMAL selection from respective
soc/intel/{skl/cnl/icl} to common/pch/Kconfig.
Change-Id: I7c9c8a87cfc5cb4c2fa8b215e56cc35c1f0cce28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34650
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch ports CB:34522 and CB:33147 changes from CNL to ICL.
TEST=Build and boot dragonegg
Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch ensures skylake soc is using common thermal code
from intel common block.
TEST=Build and boot soraka
Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.
BUG=b:138282962
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot-up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Moving these to bootblock as we are seeing some instances where
devices are rebooting into the recovery broken screen with the 0x5a error (no
bootable storage device in system). This needed to be done for KBL
platforms and never got transferred to hatch.
Please reference https://review.coreboot.org/c/coreboot/+/23647
BUG=b:137681648
BRANCH=None
TEST=Run autotest faft_bios and faft_ec suites
Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku.
More fine-tuning will happen later.
BUG=b:1704071
BRANCH=none
TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch ...
- adds the PCH ID for C232 chipset,
- renames "Premium" chipset to "HM170" (because of same IDs),
- reorders the Skylake-H PCH IDs ascending by hex values.
Used documents:
- Intel 332690-005EN
Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add the Command Response Buffer which is defined in the TPM 2.0 Specs.
CRB can be specified with MAINBOARD_HAS_CRB_TPM, even though it is
actually SoC/SB specific.
Change-Id: I477e45963fe3cdbc02cda9ae99c19142747e4b46
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Add function which checks if Intel Platform Trust Technology / Intel
integrated TPM is enabled/active.
Change-Id: If93bb5e1a3a59b5045f4e44359683876fb387a71
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34380
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new bootmem memory type OpenSBI.
It's similar to BL31 on aarch64.
Required for OpenSBI integration.
Change-Id: I5ceafd5a295f4284e99e12f7ea2aa4c6d1dbb188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
FSP v1263 for CML supports FSP to use coreboot stack. This change
selects common stack config, that enables coreboot to support
share stack with FSP.
BUG=b:133398276
Change-Id: I4098a4374363ca6f3c86c396d097f9eabc9a28fe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34130
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models
60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make
the code backward compatible with Merlin Falcon.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The initial implementation was assigning the devfn as PCI device
reference directly which was incorrect.
Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change-Id: I7abca61db61d2f2df149ca601631c45d8c4f342e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34613
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=133345634
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Hatch.
Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.
Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.
Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31521
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The device Dorp uses the variant Meep, and supports HDMI.
-sku33 (HDMI)
-sku34 (HDMI + keyboard backlight)
-sku35 (HDMI + Touchscreen)
-sku36 (HDMI + keyboard backlight + Touchscreen)
BUG=b:136522841
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I59ba2e56cf2f83ca9d533454570bcdd39c0a2e7c
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34509
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For dorp HDMI sku, select VBT which enables HDMI output.
-sku33 (HDMI)
-sku34 (HDMI + keyboard backlight)
-sku35 (HDMI + Touchscreen)
-sku36 (HDMI + keyboard backlight + Touchscreen)
Cq-Depend: chrome-internal:1502253
BUG=b:136522841
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I62262378f85bb899073ffac7804be876e649e429
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
There were two hooks in the boot state machine which dumped the ME
status to the debug UART, which is unnecessary. Removed the hook
for the BS_OS_RESUME_CHECK state, leaving just BS_PAYLOAD_LOAD, which
is called before FspNotifyEndOfFirmware, as required.
BUG=b:138463532
BRANCH=none
TEST=Boot up, check cbmem to ensure the ME status messages are
only printed one time.
Change-Id: I86bc6e33de4096f33023730ffabb25715c985de0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
This patch enables lockdown configuration for hatch family (hatch,
kindred, helios and kohaku)
BUG=b:138200201
Change-Id: Ia6dc90156dc76fde490b25cf833da3cf80f664f2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This patch disables FSP-S chipset lockdown UPDs and lets coreboot perform
chipset lockdown in ramstage.
BUG=b:138200201
TEST=FSP debug build suggests those UPDs are disable now.
Change-Id: I7e53c4e4987a7b0e7f475c92b0f797d94fdd60f4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id3382d19088cba2703350339b0bd0cfb3c0e63b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
* PCH IDs: H310, H370, Z390, B360, C242, HM370
* IGD IDs: Another variant of UHD-Graphics 630
* MCH/CPU IDs: Used at i3-8100
Used documents:
* 337347-005
TESTED=Gigabyte Z390M Gaming
Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds a user selectable option to enable all WiFi SAR
configs that apply to hatch.
BUG=b:138177048
Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
The amdht code currently relies on an idiosyncratic ASSERT() macro,
which actually doesn't do anything right now, and even it did would only
print a janky error message. Replace this with the normal ASSERT() macro
from <assert.h>. The default behaviour now is to print an error message
but do nothing else, and failed assertions will only halt if you enable
FATAL_ASSERT, in which case, well, you asked for it.
Change-Id: I6db7565171a345f9afbc9fb37cff8fda58f942df
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402076
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
There will be a possible out of bounds array access if
power_limit_1_time == ARRAY_SIZE(power_limit_time_sec_to_msr), so
prevent that in the index check. This issue was fixed for other cpus in
commit 5cfef13f8d (cpu/intel: Fix out-of-bounds read due to off-by-one
in condition). Based on the discussion for that commit, also remove the
magic constant 28 in favour of the index of the last array element.
Change-Id: Ic3f8735b23a368f8a9395757bd52c2c40088afa1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The bdk_phys_to_ptr() function converts a uint64_t address to a void *
pointer. Judging by the comments, the old implementation had a check
that would refuse to convert a null pointer, which required several
workarounds when trying to convert the address 0 to a pointer. This
isn't the case for coreboot though, which implements this function
as a simple (void *) cast, so we can remove the old workarounds.
Change-Id: I6537d1699e6726c1fb155d69a51e14da856232de
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1393962
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Ensure that best_en_idx is within bounds before accessing the _en array.
Change-Id: Ifa6259e28875a8cf8199896bda7982370ccaa277
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1393971
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34593
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The total number of errors is only needed after a final tuning run at the
end of this function, so we can remove this unneeded store for earlier
runs.
Change-Id: I62adb38ccba98d90bcf8ccd13998762b9b694111
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1393967
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The virt machine is special as it doesn't emulate flash and it puts
the coreboot.rom at start of DRAM. The payload loader doesn't know
about CBFS in DRAM and overwrites the CBFS while decompressing
payloads, resulting in undefined behaviour.
Mark the region as SRAM to make sure the payload won't
overwrite the CBFS while decompressing.
As payload is always decompressed to DRAM, it wouldn't touch
SRAM memory regions.
Change-Id: I36a18cb727f660ac9e77df413026627ea160c1e1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Fix regression introduced in bd4bcab
"lib: Rewrite qemu-armv7 ramdetect".
The detected DRAM size is in MiB, thus needs to adjusted accordingly
before passed to ram_resource.
Wasn't seen earlier as everything works, except payload loading.
Change-Id: I4931372f530e7b4e453a01e5595d15d95a544803
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
This reverts commit 598af2e2c2785c00eb4290cdcefe1082b2a6f858.
Reason for revert: This commit breaks every board with VBOOT enabled
if the platform is apollolake, broadwell, skylake, baswell, baytrails
or icelake. The reason is, that the SoC selects
VBOOT_MUST_REQUEST_DISPLAY by default, and this has a dependency now
on VBOOT_MAY_SKIP_DISPLAY_INIT. This will only be auto-selected if
it is a CHROMEOS platform.
Change-Id: I3872d9aa993326ded135d8a5d950d5b1b1eddf34
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34308
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015).
Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33842
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit 46445155ea21b0aa9106e12a00b9b1d89887a461.
Reason for revert: Breaks coreboot. Either no UART working or the
complete boot process stops.
Platform: Intel Apollolake, tested on Up Squared
Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Print an error message and return if an invalid QUP or BLSP is
encountered. This prevents a possible null pointer dereference
of spi_clk.
Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401086
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Consider the following assignment:
u64 = s32
For positive values this is fine, but if the s32 is negative, it will be
sign-extended in the conversion to a very large unsigned integer. This
manifests itself in two ways in the following code:
First, gpu_pipe{a,b}_port_select are defined as int, and can have the
values 1 or 2. In the case when they have the value 2, the shift 2 << 30
will be a negative number, making it susceptible to the sign-extension
problem above. Change these variables to something more reasonable like
a uint8_t, which is unsigned.
Second, in any bit shift, any variable with width less than an int will
be implicitly promoted to an int before performing the bit shift.
For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its
highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become
negative, again introducing the above problem. To prevent this, cast all
smaller variables to a u32 before the shift, which will prevent the
implicit promotions and sign extensions.
Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The build directory might not exist in the src dir.
BUG=b:112267918
TEST=make what-jenkins-does
Change-Id: I2d4fa6cc455592f92070796cd065cd66646d5ba9
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The logic for the calculation of plld.m is rather complicated, so do a
sanity check that it is non-zero before doing the division.
Change-Id: I60f49b8eed47a3de86713304bde7a4d3f3d935dd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1260981
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
volt_str is used to print information about the RAM configuration
in report_common_dimm(), so let's print out "unknown voltage" if the
voltage isn't recognized rather than a garbage value.
Change-Id: I8e85917fd682e166172fbf10597bde4a8a11dfc7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1393958, 1393982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
