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2022-07-07soc/intel/alderlake/acpi/gpio.asl: Fix lower case typoMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If66c2799d4d74ff9f309665a0336b5f679796f9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07mb/google/brya: Change GPP_F17 programmingTim Wawrzynczak
Currently the EC's MKBP interrupt line is programmed as dual-routed to both SCI and IOAPIC. The brya EC will pulse the MKBP GPIO and also send a host event when there is an MKBP event for host to service. This causes an extra SCI to be generated, and the kernel will respond to each MKBP event with an extra unnecessary host command. Changing the pad configuration for the MKBP GPIO to APIC only fixes this issue. BUG=b:236706977 BRANCH=firmware-brya-14505.B TEST=excess GET_NEXT_EVENT host commands are gone from EC log Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic7dd596987f6d34c69d46674bdd07785235e2d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65480 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07mb/google/brya/var/agah: Update FBVDD power-down delayTim Wawrzynczak
The EEs have observed the ramp down delay on this signal in more detail and 40 ms can still meet the sequencing requirements. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-07mb/google/brya/var/agah: Remove variant_fill_ssdt()Tim Wawrzynczak
Since the GPU will be left powered on, the kernel has the opportunity to save context and this method to save the BARs is not required. BUG=b:233959099, b:236289930 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19cf12426361a53e3672c1e05aa6d68d5dd6627c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-07mb/google/geralt: Add NOR-Flash supportRex-BC Chen
Initialize NOR-Flash in the bootblock. TEST=read nor flash data successfully. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I8ee24b5b24643bce57eb29682d6d0234a6fe8641 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65622 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/mediatek/mt8188: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers for flash read/write. TEST=read nor flash data successfully. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4e84fc023111b86f7f4984020d24811e3361ba03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65621 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/meteorlake: Remove `ADL` instancesSubrata Banik
This patch removes all instances of the `ADL` from Meteor Lake SoC directory. TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8153b2070467beb582ce1f70be97272ce09ca04c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65667 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/meteorlake: Update IFD_CHIPSET kconfig valueSubrata Banik
This patch updates IFD_CHIPSET kconfig value from `ifd2` to `mtl`. TEST=Able to build and boot Google/Rex image on MTL emulation platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416f881bcbe3dd7494ead636d6b593366a51b31c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-07mb/google/brya/var/kinox: Configure TDC currentDtrain Hsu
Configure TDC current for VR domains. +-----------+-------+-------+---------+-------------+----------+ | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | +-----------+-------+-------+---------+-------------+----------+ | IA | 2.8 | 2.8 | 80 | 43 | 28000 | +-----------+-------+-------+---------+-------------+----------+ | GT | 3.2 | 3.2 | 40 | 23 | 28000 | +-----------+-------+-------+---------+-------------+----------+ - IA TDC current from 20A to 43A. - GT TDC current from 20A to 23A. - Others comes from 'commit c6d716694272 ("soc/intel/alderlake: Configure the SKU specific parameters for VR domains")' BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ie9cf8975309b57b4189e2b50f37bd61ac0105e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65659 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07mb/google/brya/var/kinox: Support DPTF oem_variablesDtrain Hsu
Enable DPTF oem_variables and override based on charger type. BUG=b:230803675 TEST=1. With 90W adapter, check ACPI object ODVX and oem_variable[0]=1 Name (ODVX, Package (0x06) { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) 2. With 65W adapter, check ACPI object ODVX and oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I78929ecbc9db56aa234b3f46c641d1f2f3b7cba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-07mb/google/brya: Disable SaGV support for agah variantAnil Kumar
agah proto boards with i7 silicon face boot issues due to high power consumption during MRC training. This patch is a temporary WA to run in SAGV disabled mode while the thermal issue is being investigated. BUG=b:234402102 BRANCH=firmware-brya-14505.B TEST=Build CB image and boot on agah board. Change-Id: I431d233b23fb4f5c68117ea380fdec5646b88346 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65300 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-07mb/msi/ms7d25: add basic FSP configuration in devicetreeMichał Kopeć
Configure some basic FSP parameters in devicetree for to allow for booting an OS. Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63499 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mb/msi/ms7d25: add GPIO configurationMichał Kopeć
Based on the output of: - inteltool from CB:63374 - intelp2m from CB:63403 TEST=Build coreboot binary for msi/ms7d5 and boot the board. Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFIMichał Żygowski
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-06soc/intel/common: Update the comment on CSE Region layoutSridhar Siricilla
The comment indicates CSE's data partition is placed after BP2. But, it was place after BP1.So, the patch updates the comment to reflect the CSE Region layout correctly. TEST=Build the code for Brya and didn't notice any compilation errors Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-06soc/mediatek: Move FLASH_DUAL_READ to commonRex-BC Chen
FLASH_DUAL_READ is a common configuration for all MediaTek SoCs, so we move it to common folder and select it in SoCs' Kconfig. As suggested in CB:58837, we also rename FLASH_DUAL_READ to FLASH_DUAL_IO_READ to reduce confusion. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If267a332519412a7919c5b7817047fabe4a564c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65620 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/mediatek/mt8188: Add GPIO driversGuodong Liu
Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:233720142 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I0a2a5178949e9ad3e033ac332e0f1e8565e39b3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Move some gpio functions to common/gpio_op.cRex-BC Chen
gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd() can be reused for mt8192, mt8195 and mt8186, so move it to new file "gpio_op.c" in common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek/mt8188: Add timer supportBo-Chen Chen
Add timer drivers to Makefile. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I0e3e58c7118a18e738a5abba391db0be9cfd7bf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65588 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Make timer_prepare() a common functionRex-BC Chen
timer_prepare() is the same for MT8195 and MT8186, so move it to common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek/mt8188: Initialize watchdogBo-Chen Chen
Add watchdog support for MT8188. This implementation is based on chapter 3.10.10 in MT8188 Functional Specification. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iaf56c78d89af53d0272583b463c050e69bbeb07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65587 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen
There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for SabrinaJon Murphy
Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here. BUG=b:218709292 TEST=Set serial soft fuse, boot to kernel, check logs Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/qualcomm/ipq40xx: Do resource transitionKyösti Mälkki
Change-Id: I93c16b563c7a4f4c653d2ebfd001170cb0fca82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-06mb/google/nissa/var/joxer: Add lock gpio pinsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia087b62904fd515bf73960a188b225f1d49197dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65646 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06mb/google/nissa: Select Kconfig to perform CSE FW update in ramstageKrishna Prasad Bhat
Alder Lake-N based nissa boards use compressed ME_RW blobs for CSE FW Update. Choose SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE Kconfig to perform CSE FW sync in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW upgrade/downgrade on nivviks. Change-Id: I00630096c52434f44914f3ae82ff043ecf77b80d Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65368 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06common/intel/cse: Add function to perform CSE FW update in ramstageKrishna P Bhat D
When compressed ME RW blobs are used for CSE FW update, it has to be loaded into memory to decompress. So perform CSE FW update in ramstage. Alder Lake-N based nissa boards use compressed ME RW blobs to save on SPI flash size. Enable CSE FW update in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW update on nivviks and verify upgrade/downgrade works. Change-Id: Ide9471146d186dca11fb020e5006eeaa01442669 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06soc/intel/alderlake: Add check for CSE FW sync in romstageKrishna P Bhat D
Some Alder Lake-N boards will use compressed ME RW blobs to obtain savings on the SPI size (1916KB before compression, ~1132KB after compression). So add an additional check before calling cse_fw_sync() from romstage. When compressed blobs are used, the call to CSE firmware update has to be in post-RAM stages. BRANCH=firmware-brya-14505.B Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06mb/google/nissa/var/pujjo: Add lock gpio pinsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I9f0fcf52b6b7d622e4fd182e007de6401856c7fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65645 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/meteorlake: Enable X2APICSubrata Banik
This patch enables X2APIC to avoid hang-ups due to `Switching from X2APIC to XAPIC mode is not implemented.`  BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP) TEST=Able to enable X2APIC on rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/baytrail,braswell,quark: Drop RES_IN_KIBKyösti Mälkki
Change-Id: I2360a1a79f07ff8466ed01aa7f180d410e019292 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05mb/google/brask/variants/moli: set tcc_offset to 0℃Raihow Shi
Set tcc_offset value to 0 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8d4c631e07873923226683c8aa0cf36cb872e2d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-05mb/starlabs/labtop/tgl: Nit - minor format changeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I068c6e46d85d869afc72280509a03d5ff682b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65618 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05mb/starlabs/labtop: Define CCD Port in KconfigSean Rhodes
Define the CCD (aka "Webcam") USB port in the devicetree as it is used in multiple places. It is used in devtree to disable it based on the CMOS setting "webcam", and in the devicetree to configure the port tuning. This also corrects the port that is disabled on CML, from usb2_port[6] to usb2_port[3]. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I16e368fc7965f978f2302633122ba63038603c1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64704 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05mb/starlabs/labtop/tgl: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. This also removes usb3_port[2] as it is not connected and fixes the labelling of usb3_port[0] and usb3_port[1]. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7923fc00c36687a7f89d863eb0ea4e01a036502d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-05mb/starlabs/lite/glk: Update VbtSean Rhodes
Update the Vbt to disable the fixed mode feature, to allow for bootloader resolutions higher than 1920x1080. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibd9850dcaef97a58c6694ee594014e9f16ae7f96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-05mb/google/nissa: Lock gpio pins in fw config for nissa variantsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=check gpios are locked in pinctrl dump. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieed2d40b0222d8c8c193e0590131f83a5d96add9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-05mb/google/nissa: Lock gpio pins for nissa variantsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=check gpios are locked in pinctrl dump. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-04soc/intel/alderlake: RPL-P power limits and VR settingsJeremy Compostella
This patch sets the Power Limits and Voltage Regulator settings for three RaptorLake SKUs (45W, 28W and 15W) following the guidance from document 686872 (June 7th edition). BUG=b:237809660 TEST=Power Limit and VR serial logs review + debug instrumentation SKUs successfully booted Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-04mb/qemu-i440fx,soc/nvidia: Fix coverity reported defectsKyösti Mälkki
In reality the expression should not overflow as the value fits in 32 bits. Change-Id: I50d83dce25a4d464e1c979502c290d8ecd733018 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-04soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I4f48742b04edd50fbc0db342b563534e709d6fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake/fsp_params.c: Handle CnviWifiCore parameterMichał Żygowski
Platform with public FSP hooked-up have an additional parameter to control CNVi WiFi with CnviWifiCore UPD. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I19efb645fbe1530a571c92d0573c1c60ff6605a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake: Hook up ADL-P and ADL-S public FSPMichał Żygowski
Update 3rdparty/fsp submodule to include AlderLake FSP. Hook up the Kconfig settings to point to Fsp.fd and headers for ADL-S and ADL-P platforms which the FSP has been published for. The FSP binaries are compliant with the specification revision 2.3 so update these settings accordingly. Although FSP header is v2.3 compliant, the features set of the FSP v2.3 is not being met. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04mb/google/brya: Disable PCH USB2 phy power gating for crotaTerry Chen
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for primus board. Please refer Intel doc#723158 for more information. BUG=b:237725329 TEST=Verify the build for crota board Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I6dde74c098ba57b7cd66ce7b9ee941b8961ad20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04mb/google/brya/var/kinox: Change HDMI port form DDPC to DDP2ericky_cheng
Modify GPIOs according to SOC_GPIO_Table_0629.xlsx. - GPP_A21 from TCP_DP1_CTRLCLK to NC - GPP_A22 from TCP_DP1_CTRLDATA to NC - GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1) - GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1) BUG=b:237468533 TEST=emerge-brask coreboot Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-07-04mb/google/nissa: Lock PLT_RST_L pinReka Norman
There is a requirement that the TPM RST signal cannot be asserted by software. On nissa this is PLT_RST_L, so lock this pin to prevent it being reconfigured as a GPIO. BUG=b:216671701 TEST=Try to change GPP_B13 from the kernel: $ echo 677 > /sys/class/gpio/export $ echo out > /sys/class/gpio/gpio677/direction $ echo 0 > /sys/class/gpio/gpio677/value $ echo 1 > /sys/class/gpio/gpio677/value GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED" Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-04mb/google/nissa/var/craask: Enable G2 touchscreenTyler Wang
Add G2 touchscreen support for craaskvin. BUG=b:235919755 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7ade3ac1d135b8b21b09ef335ab7b30ae7a5e2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-04mb/google/nissa/var/joxer: set up gpioMark Hsieh
Set the GPIO configuration of joxer BUG=b:237628218 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1f7529342fc0800878f875d3641a2f93fbe6009a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-04soc/qualcomm/sc7180: Update hardware watchdog loggingKshitiz Godara
Move watchdog functionality to common folder. BUG=b:221393157 TEST=None Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: Ib2f7f21ce991fd8193329e7b8260e58e47bf39c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-04mb/google/brask/var/kuldax: Add ACPI _PLD custom valuesDavid Wu
This patch uses ACPI _PLD macros to add custom values for USB ports. C0 A2 A3 +----------------+ | REAR | | | | | | | | FRONT | +----------------+ A1 A0 BUG=b:232419500 TEST=emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5ada4e9b25102a9cfd3b02a2abcd956f6cbc5619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-04src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infozhixingma
CPUID_RAPTORLAKE_P_Q0 is ES. Add it to generate is_es = 1 in ACPI BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: I67d70dc7e916a4818869aef86e7e642b66ea5dae Reviewed-on: https://review.coreboot.org/c/coreboot/+/65118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-04mb/amd/bilby: Add PSP NVRAM and RPMC NVRAM region to flash mapRitul Guru
Create PSP NVRAM and RPMC NVRAM region with size 128K & 64K respectively, which are supported region by the PSP. moved CBFS up due to build error, CBFS need not to be at the end the flash for amd Zen cpu. Change-Id: Ide778c61a755697c1bef1eaa87f2976d8ff12eb6 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-04soc/amd/sabrina: Add support for Rembrandt SoC as base SoCRitul Guru
This change adds new Rembrandt SoC support by defining it as base SoC of sabrina as sabrina is derived from Rembrandt SoC. All the needed changes for Rembrandt SoC will be applied under SOC_AMD_REMBRANDT config. Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-04mb/google/brya/var/kano: Disable PCH USB2 phy power gatingDavid Wu
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for kano board. Please refer Intel doc#723158 for more information. BUG=None TEST=Verify the build for kano board Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19430a68e1e847e71382781563200a4c88f37a59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-07-04mb/google/brya/var/pujjo: Add GPIO tableleo.chou
Fill GPIO table for Pujjo. BUG=b:235774770 TEST=emerge-nissa coreboot Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I307b8460632f1feae9591200057c0e6471cbab24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65104 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04mb/google/brya/var/ghost4adl: Update Type-C locationsCaveh Jalali
This updates the ACPI locations of Type-C ports. BUG=b:232806406 TEST=none Change-Id: Ia15e09a58c731a1364a994fadf8df39115fbe7c4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04mb/google/geralt: Add MediaTek MT8188 reference boardRex-BC Chen
Add mainboard folder and drivers for new reference board 'Geralt'. TEST=saw the coreboot uart log to bootblock BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I5e437d46097369bef535ff64e6a693b7cf67f2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65586 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org>
2022-07-04soc/mediatek/mt8188: Add a stub implementation of the MT8188 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8188'. Difference of modules including in this patch between MT8188 and existing SoCs: Timer: Similar to MT8195 and MT8186, MT8188 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. The implementation is based on these files: MT8188G_Application Processor Technical Brief_v0.4.pdf MT8188G_Functional Specification v0.4.pdf MT8188 Application Processor Registers-1.pdf MT8188 Application Processor Registers-2.pdf TEST=saw the coreboot uart log to bootblock BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org>
2022-07-03soc/intel/meteorlake: Use coreboot native event handler for FSP-M/SSubrata Banik
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:237263080 TEST=Able to build and boot MTL simics. Also, verified the FSP debug log is using coreboot debug library as below: Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-03vc/intel/fsp2_0: Add UPDs into the FSP partial header version 2222Subrata Banik
This patch adds below UPDs into the existing FSP partial header v2222.1 FSP-M UPD: DisableMc0Ch0 DisableMc0Ch1 DisableMc0Ch2 DisableMc0Ch3 DisableMc1Ch0 DisableMc1Ch1 DisableMc1Ch2 DisableMc1Ch3 DdrFreqLimit GpioOverride SerialIoUartDebugMode SerialDebugMrcLevel SmbusDynamicPowerGating WdtDisableAndLock SaIpuEnable SkipCpuReplacementCheck TcssDma0En TcssDma1En VtdBaseAddress CpuCrashLogDevice CpuCrashLogEnable LCT TdcEnable TdcTimeWindow Lp5CccConfig RMTBIT RmtPerTask RMTLoopCount MrcFastBoot EnCmdRate SaGvGear TAT PchHdaVcType BdatTestType RdEnergyMc0Ch0Dimm1 RdEnergyMc0Ch0Dimm0 CorePllVoltageOffset RdEnergyMc1Ch1Dimm1 RdEnergyMc1Ch1Dimm0 DciEn PchPort80Route ActEnergyMc0Ch1Dimm1 ActEnergyMc0Ch1Dimm0 HeciCommunication2 PcdSerialDebugBaudRate HeciTimeouts ThrtCkeMinDefeatLpddr PchPcieHsioRxSetCtle BdatEnable DisableCpuReplacedPolling PchSataHsioRxGen1EqBoostMagEnable CoreVoltageOffset PchPcieHsioTxGen1DownscaleAmp PchHdaDspUaaCompliance VddVoltage WRVC1D PreBootDmaMask tWR RingVoltageAdaptive PchSataHsioTxGen3DeEmphEnable PchPcieHsioRxSetCtleEnable RingPllVoltageOffset OcSupport WrEnergyMc0Ch0Dimm1 PdEnergyMc1Ch1Dimm1 PdEnergyMc1Ch1Dimm0 DmiGen3ProgramStaticEq SmramMask tRAS PerCoreHtDisable IdleEnergyMc1Ch0Dimm0 IdleEnergyMc1Ch0Dimm1 Gen3LtcoEnable tWTR RCVET DmiGen3UsPresetEnable tCWL PwdwnIdleCounter WRTC1D CLKTCO PrimaryDisplay DisableMessageCheck tFAW PchSataHsioTxGen2DeEmphEnable SerialIoUartDebugRtsPinMux GtExtraTurboVoltage TXTCO PchSataHsioTxGen3DownscaleAmp CpuRatioOverride PostCodeOutputPort DmiHweq CoreVfPointCount NModeSupport Ddr4DdpSharedZq RdEnergyMc1Ch0Dimm0 RdEnergyMc1Ch0Dimm1 PchSataHsioTxGen2DownscaleAmp DebugInterfaceEnable WrEnergyMc0Ch1Dimm0 WrEnergyMc0Ch1Dimm1 SaPllVoltageOffset DmiGen3EndPointPreset PchSataHsioRxGen2EqBoostMag VDDQT PvdRatioThreshold CoreVfPointOffsetMode DmiGen3DsPortRxPreset BclkRfiFreq SmbusArpEnable PowerDownMode DebugInterfaceLockEnable RingVoltageOffset EnableExtts SerialIoUartDebugCtsPinMux PchPcieHsioTxGen2DownscaleAmpEnable Avx2VoltageScaleFactor GearRatio GtVoltageOverride EccSupport RingMaxOcRatio TrainTrace EnablePwrDn IsTPMPresence OcLock DmaBufferSize SOT CoreVfPointRatio PchPcieHsioTxGen2DownscaleAmp TjMaxOffset CoreMaxOcRatio RingDownBin PchSataHsioRxGen1EqBoostMag BiosAcmSize tRFC PchPcieHsioTxGen1DownscaleAmpEnable PdEnergyMc0Ch1Dimm0 PdEnergyMc0Ch1Dimm1 RDMPRT TxtLcpPdBase CMDVC SerialIoUartDebugBaudRate PchTraceHubMemReg1Size CoreVoltageOverride McPllVoltageOffset PdEnergyMc1Ch0Dimm0 PdEnergyMc1Ch0Dimm1 GttMmAdr PchPcieHsioTxGen1DeEmphEnable ApStartupBase CoreVoltageAdaptive GtVoltageMode PcieImrRpSelection TxtLcpPdSize PchPcieHsioTxGen2DeEmph3p5 ThrtCkeMinTmr RealtimeMemoryTiming UserBudgetEnable PchPcieHsioTxGen3DownscaleAmpEnable GmAdr PchSataHsioTxGen1DeEmphEnable CrashLogGprs tRTP RMC PchSataHsioTxGen3DownscaleAmpEnable RDODTT RDVREFDC PerCoreRatio IdleEnergyMc0Ch1Dimm1 tRCDtRP DidInitStat SerialIoUartDebugRxPinMux SerialIoUartDebugMmioBase BiosSize MmioSizeAdjustment PchTraceHubMode DmiGen3Ltcpre CoreVoltageMode DmiGen3UsPortTxPreset Gen3EqPhase3Bypass BclkSource KtDeviceEnable DciUsb3TypecUfpDbg CoreVfPointOffset Gen3RtcoRtpoEnable TotalFlashSize BclkAdaptiveVoltage TvbRatioClipping EnablePwrDnLpddr WRTC2D RankInterleave PchSataHsioRxGen3EqBoostMag IdleEnergyMc0Ch0Dimm1 IdleEnergyMc0Ch0Dimm0 Ratio JWRL Avx3RatioOffset Avx2RatioOffset RDVC1D DCC PchSataHsioTxGen2DeEmph ExitOnFailure IdleEnergyMc1Ch1Dimm1 IdleEnergyMc1Ch1Dimm0 RingVoltageOverride SpdProfileSelected ScramblerSupport SaGvFreq WRVC2D DmiGen3EqPh3Method CMDSR RdEnergyMc0Ch1Dimm0 RdEnergyMc0Ch1Dimm1 UserThresholdEnable ThrtCkeMinDefeat DmiGen3EqPh2Enable tRRD ChHashEnable BistOnReset ChHashInterleaveBit RemapEnable RDVC2D DIMMRONT WrEnergyMc0Ch0Dimm0 DmiAspm PchPcieHsioTxGen2DeEmph6p0Enable PchSataHsioTxGen1DeEmph RDEQT TxtDprMemoryBase WrEnergyMc1Ch0Dimm1 WrEnergyMc1Ch0Dimm0 DmiGen3EndPointHint CleanMemory PchSmbAlertEnable SaOcSupport PchSataHsioTxGen3DeEmph TxtImplemented CoreVfPointOffsetPrefix PchHdaTestPowerClockGating DmaControlGuarantee DIMMODTT ERDMPRTC2D RootPortIndex SkipStopPbet VtdIopEnable DmiGen3DsPortTxPreset ActiveCoreCount PchLpcEnhancePort8xhDecoding GtVoltageOffset DisPgCloseIdleTimeout ActEnergyMc1Ch0Dimm1 ActEnergyMc1Ch0Dimm0 Idd3n Idd3p PchSataHsioTxGen1DownscaleAmpEnable BClkFrequency ActEnergyMc0Ch0Dimm0 ActEnergyMc0Ch0Dimm1 DdrFreqLimit Gen3EqPhase23Bypass WrEnergyMc1Ch1Dimm0 DmiGen3DsPresetEnable PcieImrSize EWRTC2D IbeccOperationMode VtdBaseAddress TvbVoltageOptimization DciDbcMode HobBufferSize PchHdaSdiEnable PcieImrEnabled IdleEnergyMc0Ch1Dimm0 SerialIoUartDebugAutoFlow tCL PdEnergyMc0Ch0Dimm1 PdEnergyMc0Ch0Dimm0 RDTC2D ERDTC2D SerialIoUartDebugParity PchPcieHsioTxGen2DeEmph3p5Enable PchPcieHsioTxGen1DeEmph DmiGen3Ltcpo PchSmbusIoBase RaplPwrFlCh1 RaplPwrFlCh0 EnhancedInterleave PchPcieHsioTxGen2DeEmph6p0 MemTestOnWarmBoot Ibecc PanelPowerEnable BiosAcmBase DmiGen3UsPortRxPreset DmiAspmL1ExitLatency CmdMirror PchSataHsioTxGen2DownscaleAmpEnable tREFI CpuBclkOcFrequency CridEnable EpgEnable SmbusSpdWriteDisable DdrSpeedControl PchSataHsioRxGen2EqBoostMagEnable GtMaxOcRatio DmiMaxLinkSpeed PchSataHsioRxGen3EqBoostMagEnable PcieImrRpLocation CmdRanksTerminated SkipMbpHob SerialIoUartDebugTxPinMux PchSataHsioTxGen1DownscaleAmp PchPcieHsioTxGen3DownscaleAmp PerCoreRatioOverride PchHdaAudioLinkDmicClockSelect SerialIoUartDebugDataBits SrefCfgEna Avx512VoltageScaleFactor MmioSize SaVoltageOffset SaIpuEnable ActEnergyMc1Ch1Dimm0 ActEnergyMc1Ch1Dimm1 ProbelessTrace VtdIgdEnable ALIASCHK PchTraceHubMemReg0Size DIMMODTCA TgaSize EWRDSEQ SerialIoUartDebugStopBits RDTC1D CMDNORM RingVoltageMode EnableAbove4GBMmio WrEnergyMc1Ch1Dimm1 Txt PcieMultipleSegmentEnabled CnviDdrRfim FSP-S UPD: CpuMpPpi LidStatus ITbtConnectTopologyTimeoutInMs D3HotEnable D3ColdEnable PchLockDownGlobalSmi PchLockDownBiosInterface PchUnlockGpioPads RtcMemoryLock SkipPamLock EndOfPostMessage CpuUsb3OverCurrentPin PcieRpHotPlug SerialIoUartAutoFlow TccActivationOffset VmdEnable Enable8254ClockGating Enable8254ClockGatingOnS3 HybridStorageMode PcieRpHotPlug Hwp Cx PsOnEnable EnergyEfficientTurbo PchPmDisableEnergyReport UfsEnable FspEventHandler GnaEnable VbtSize PcieComplianceTestMode CStatePreWake SerialIoUartDataBits SataPortsExternal CstateLatencyControl0TimeUnit SataP0Tinact PmcV1p05PhyExtFetControlEn ApIdleManner SataPortsSpinUp DisableProcHotOut ITbtPcieTunnelingForUsb4 SerialIoUartDmaEnable SaPcieItbtRpNonSnoopLatencyOverrideMode SaPcieItbtRpSnoopLatencyOverrideMode MlcSpatialPrefetcher PchXhciOcLock PmcPowerButtonDebounce TccOffsetClamp LogoPixelWidth AvxDisable Custom1PowerLimit1 Custom1PowerLimit2 PmcCpuC10GatePinEnable PchPmSlpStrchSusUp IshI2cSdaPadTermination Custom2PowerLimit1Time RtcBiosInterfaceLock WatchDogTimerBios SataP1TDisp PchPciePort8xhDecodePortIndex PcieRpImrSelection TcCstateLimit PchS0ixAutoDemotion PchFivrExtV1p05RailEnabledStates PcieRpSlotPowerLimitScale IshUartCtsPinMuxing PcieRpSnoopLatencyOverrideMode TTCrossThrottling PsysPowerLimit1 SataRstInterrupt IshSpiClkPadTermination PcieEnablePeerMemoryWrite SataP1T2M ChipsetInitBinPtr LogoPixelHeight PsysPowerLimit1Time HwpInterruptControl DevIntConfigPtr IshUartRtsPadTermination PsysPowerLimit1Power EnergyEfficientTurbo Custom3TurboActivationRatio PcieDpc TurboMode PchFivrExtVnnRailSupportedVoltageStates ITbtDmaLtr IshSpiClkPinMuxing PchSbAccessUnlock PcieRpSystemErrorOnCorrectableError PcieRpSlotPowerLimitValue SendEcCmd SataSpeedLimit SataRstPcieEnable PchUsb3HsioCtrlAdaptOffsetCfg SataP0T2M PchHdaVerbTableEntryNum DmiTS1TW DmiTS2TW PcieRpImrEnabled GpioIrqRoute SataPortsSolidStateDrive RaceToHalt PcieRpNonSnoopLatencyOverrideMultiplier PcieRpUnsupportedRequestReport AesEnable PchFivrExtVnnRailSxVoltage SataP1Tinact PkgCStateUnDemotion SataPortsZpOdd PchSerialIoI2cPadsTermination PchFivrExtV1p05RailSupportedVoltageStates PchUsbLtrLowIdleTimeOverride IshSpiMosiPinMuxing PchProtectedRangeLimit SaPcieItbtRpNonSnoopLatencyOverrideValue SataP1T3M PchPmWoWlanEnable IshUartRtsPinMuxing SataLedEnable VmdGlobalMapping PcieRpEnableCpm IshGpGpioPadTermination PchDmiCwbEnable ForcMebxSyncUp FspEventHandler PchFivrExtVnnRailIccMax PchPmMeWakeSts DisableD0I3SettingForHeci PcieRpNonSnoopLatencyOverrideMode PmgCstCfgCtrlLock PchUsbLtrHighIdleTimeOverride Usb3HsioTxRate2UniqTran SiNumberOfSsidTableEntry IshSpiMisoPadTermination IshUartRxPadTermination PcieRpSlotImplemented PchUsbOverCurrentEnable EndOfPostMessage SaPcieItbtRpSnoopLatencyOverrideValue EnableHwpAutoEppGrouping SerialIoUartDbg2 ConfigTdpLock EsataSpeedLimit PchTsnEnable PowerLimit3DutyCycle TTSuggestedSetting PchEnableDbcObs IehMode VmdPort PchFivrExtVnnRailCtrlRampTmr PchPmSlpAMinAssert CstateLatencyControl5TimeUnit ProcessorTraceEnable ChipsetInitBinLen PchTemperatureHotLevel Usb3HsioTxRate3UniqTranEnable NumberOfEntries Custom2ConfigTdpControl PowerLimit3Lock SiCustomizedSsid PchUsb3HsioFilterSelP DisableVrThermalAlert PchIoApicEntry24_119 SmbiosType4MaxSpeedOverride PowerLimit3Time C1StateUnDemotion PchDmiAspmCtrl PchUsb3HsioFilterSelN PchTTEnable PcieRpNoFatalErrorReport Custom1ConfigTdpControl PmcC10DynamicThresholdAdjustment PchFivrVccinAuxRetToLowCurModeVolTranTime BiProcHot VmdPortFunc PchUsb3HsioFilterSelNEnable PchHdaVerbTablePtr TurboPowerLimitLock PcieRpSystemErrorOnNonFatalError PmcUsb2PhySusPgEnable PcieRpSystemErrorOnFatalError PchProtectedRangeBase VccSt PchFivrExtVnnRailSxEnabledStates EnableHwpAutoPerCorePstate CstateLatencyControl1TimeUnit SaPcieItbtRpSnoopLatencyOverrideMultiplier PchPmSlpS4MinAssert PcieRpTransmitterHalfSwing Usb3HsioTxRate3UniqTran RenderStandby ProcessorTraceOutputScheme SkipFspGop PchHdaPme EcCmdProvisionEav BgpdtHash Usb3HsioTxRate0UniqTran UsbOverride PkgCStateDemotion EnableAllThermalFunctions PchPmWolEnableOverride IshSpiCsPinMuxing PchIshSpiCsEnable IshUartCtsPadTermination PmcV1p05IsExtFetControlEn MaxRingRatioLimit PchIshPdtUnlock IshUartTxPinMuxing PchFivrExtV1p05RailIccMax BiosGuardAttr LogoPtr CpuBistData ShowSpiController PchPmWolOvrWkSts SataP0T1M CstCfgCtrIoMwaitRedirection TcoIrqEnable PchHdaLinkFrequency ITbtForcePowerOnTimeoutInMs SerialIoSpiCsEnable VmdMemBar2Base TStates SiSkipSsidProgramming TccOffsetTimeWindowForRatl AmtSolEnabled PchUsb3HsioCtrlAdaptOffsetCfgEnable PchFivrExtVnnRailIccMaximum PchEspiLgmrEnable SkipPamLock IshGpGpioPinMuxing PchUsb3HsioFilterSelPEnable PchFivrExtVnnRailVoltage SataPortsDevSlpResetConfig ProcHotLock PchDmiTsawEn SerialIoSpiCsPolarity PkgCStateLimit EnableRsr PmcDbgMsgEn PchPmPwrCycDur NumOfDevIntConfig SerialIoSpiDefaultCsOutput PchPmPciePllSsc PxRcConfig CstateLatencyControl4TimeUnit PcieRpPmSci ConfigTdpBios PmcPdEnable PchT1Level PmcModPhySusPgEnable DisableTurboGt EnableTcoTimer IshSpiMisoPinMuxing IshI2cSclPinMuxing PcieRpCorrectableErrorReport C1StateAutoDemotion PchEspiLockLinkConfiguration PchFivrExtV1p05RailCtrlRampTmr SataRstPcieStoragePort PchFivrExtV1p05RailVoltage PchPmSlpSusMinAssert PchHotEnable PcieRpNonSnoopLatencyOverrideValue TcoIrqSelect PcieRpCompletionTimeout FwProgress StateRatioMax16 ConfigTdpLevel IshI2cSdaPinMuxing PcieRpPhysicalSlotNumber SerialIoUartParity TxtEnable PchLegacyIoLowLatency PchUsbLtrMediumIdleTimeOverride PchPmPmeB0S5Dis SerialIoUartPowerGating PcieRpSnoopLatencyOverrideValue PchPmSlpLanLowDc PchT2Level CstateLatencyControl2TimeUnit PchPmSlpS3MinAssert PchUsb3HsioOlfpsCfgPullUpDwnResEnable MonitorMwaitEnable Usb3HsioTxRate1UniqTran Eist IshSpiMosiPadTermination PowerLimit4Lock Custom3PowerLimit1Time PcieEnablePort8xhDecode DualTauBoost WatchDogEnabled MaxRatio Custom2TurboActivationRatio PchFivrExtVnnRailEnabledStates ApplyConfigTdp IshI2cSclPadTermination PowerLimit2Power ThermalMonitor CpuUsb3OverCurrentPin PchTTLock Custom1PowerLimit1Time PchEspiHostC10ReportEnable Usb3HsioTxRate2UniqTranEnable SataPortsInterlockSw EnablePerCorePState PsysPowerLimit2Power UfsEnable PchPmDisableNativePowerButton VmdVariablePtr Custom3PowerLimit2 PchPmDisableEnergyReport Custom3PowerLimit1 DmiTS3TW EnforceEDebugMode CstateLatencyControl3TimeUnit VmdCfgBarBase DmiSuggestedSetting SataPortsEnableDitoConfig SerialIoUartBaudRate Usb3HsioTxRate1UniqTranEnable SataPortsHotPlug MachineCheckEnable Custom1TurboActivationRatio Custom2PowerLimit1 Custom2PowerLimit2 VmdMemBar1Base SaPcieItbtRpLtrConfigLock SataP0TDispFinit PchFivrExtVnnRailSxIccMaximum PchTsnLinkSpeed SataThermalSuggestedSetting SaPcieItbtRpLtrEnable TimedMwait PchTsnMultiVcEnable PcieRpFunctionSwap PcieEqOverrideDefault SataP1T1M PsysPowerLimit2 PchLanLtrEnable SerialIoUartStopBits SciIrqSelect C1e PchFivrExtVnnRailSxIccMax PowerLimit3 PowerLimit2 PowerLimit1 MeUnconfigOnRtcClear PcieRpPcieSpeed PchUsbLtrOverrideEnable UsbPdoProgramming Custom3ConfigTdpControl SataP1TDispFinit PchFivrDynPm VmdPortDev EnableItbm MinRingRatioLimit PcieRpFatalErrorReport MctpBroadcastCycle EcCmdLock StateRatio PchPmVrAlert DmiTS0TW LogoSize PchIoApicId SaPcieItbtRpForceLtrOverride PcieRpSnoopLatencyOverrideMultiplier IshUartTxPadTermination PchCrid SataRstPcieDeviceResetDelay ProcHotResponse BltBufferSize MlcStreamerPrefetcher PcieRpLtrConfigLock SiSsidTablePtr SataP0TDisp PchUsb3HsioOlfpsCfgPullUpDwnRes BltBufferAddress PcieRpDetectTimeoutMs PpinSupport SataRstRaidDeviceId PchPmLatchEventsC10Exit IshUartRxPinMuxing PpmIrmSetting EnergyEfficientPState PchFivrExtV1p05RailIccMaximum PortResetMessageEnable PchReadProtectionEnable BiosGuardModulePtr PchWriteProtectionEnable AmtEnabled PchHdaCodecSxWakeCapability SiCustomizedSvid PcieEdpc TccOffsetLock PchPmPwrBtnOverridePeriod SaPcieItbtRpNonSnoopLatencyOverrideMultiplier WatchDogTimerOs PchTTState13Enable PowerLimit1Time PchT0Level IshSpiCsPadTermination SataP0T3M Usb3HsioTxRate0UniqTranEnable SataTestMode PmcOsIdleEnable PowerLimit4 PcieRpAcsEnabled PavpEnable UsbTcPortEn Additionally, optimize the `reserved` fields across header files. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I976a5762701711fbf000c43c5ff05f9bd93f688f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-01mb/google/rex: Redirect AP UART over LPSS UART 0Subrata Banik
This patch ensures AP UART messages are coming over LPSS UART 0 hence, select required kconfig and program both early and late UART RX/TX GPIOs accroding to the rex schematics dated 06/27. BUG=b:224325352 TEST=Able to see AP UART log over LPSS UART0. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Generate LP5 RAM IDSubrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) BUG=b:224325352 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibcd25ae80d625b623b9a78ff2cd4447e85831cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65476 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add memory initEric Lai
Add memory init with placeholder to fill in required memory configuration parameters. DQ map and Rcomp can be auto probed by the FSP-M hence, kept it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Able to boot till FSP-M/MRC using MTL simics. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add EC smihandlerEric Lai
Add SMI handler implementation to manage power cycle, power state transition and Chrome EC events. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I10aab8257fce92aaf913a53c0c9fb6c1a4f5dea6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64623 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64622 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8374a9b528f8dff4e23b6bdb4d1368dfd2c79b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64620 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock, romstage and ramstage. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I51426f9557dafc357fc54a971b6f76fac5323e0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64593 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add entry stubs of each stageEric Lai
Add entry point stubs of each stage for Rex. More functionalities will be added later. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2310e58ab92bdb0ce86a9f7284cc0b3e04a2889f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64591 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add flashmap descriptorEric Lai
Add 32MB flashmap descriptor as below: Descriptor Region -> 0 - 0x3fff (~16KB) CSE Partition -> 0x4000 - 0x8fffff (~9MB) BIOS Region -> 0x900000 - 0x1ffffff (23MB) BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia5ced770bb02c11a9ab39837e66562d2ee22b6e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-01mb/google/rex: Add MTL reference platformSubrata Banik
This commit is a stub for rex, which is a an Intel Meteor Lake-P reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I46bd8d47b370cacbe0a09bbeaccacf7f1d51d8b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62969 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01soc/intel/mtl: Add GPIOs for Meteor Lake SOCRavi Sarawadi
Add definitions for the GPIO pins on Meteor Lake SoC, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_CPU, GPP_V, GPP_C Comm. 1: GPP_A, GPP_E Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3 Comm. 4: GPP_S, JTAG Comm. 5: GPP_B, GPP_D, VGPIO BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30nb/intel: Drop local legacy_hole definitionsKyösti Mälkki
These are architectural and followup works will address the VGA MMIO and/or ASEG better. Change-Id: I88e1dca8058661e31ba934b9860751e13a107108 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55928 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30mb/google/brya/var/gimble: Disable PCH USB2 phy power gatingMark Hsieh
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for primus board. Please refer Intel doc#723158 for more information. BUG=b:237421399 TEST=Verify the build for gimble board Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie66c9679c985215ad7f1a5ae76560b839ea95702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65474 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/qualcomm: Do resource transitionKyösti Mälkki
For ipq806x this fixes two resources getting declared with same index. The latter previously overwrote former. Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-30mb/emulation/qemu-i440fx,q35: Do resource transitionKyösti Mälkki
Change-Id: Ifb47e0d1d1b9c01c1332af4135f5578160c491a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-30soc/intel/common: Compile debug_feature in ramstage to fix build errorKrishna P Bhat D
In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in ramstage to fix build error. BRANCH=firmware-brya-14505.B Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/alderlake: Enable all bits for IO decode / enable registerSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I86423c45ca33a79d3d8cf8e4ca4737da94a4aa4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-30soc/intel/common: Update CSE FW update flow for compressed ME_RW blobsKrishna P Bhat D
In the CSE FW update flow, update is triggered when there is a mismatch in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed, compared and then the CSE RW region is updated. However, in the case of compressed blobs, we cannot directly map the blobs from SPI. It needs to be decompressed before the hash is calculated and compared. Add a check for compressed blobs and figure out whether it needs to be directly mapped from SPI or loaded into memory allocated for file in CBMEM, with the provided CBMEM ID. BRANCH=firmware-brya-14505.B Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30common/block/cse: Add Kconfigs to indicate when CSE FW sync is performedKrishna Prasad Bhat
CSE FW sync is currently performed in romstage, when uncompressed ME_RW blobs are used. When compressed blobs are used, this has to be done in post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be performed, in romstage or in ramstage. BRANCH=firmware-brya-14505.B Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30commonlib: Add CBMEM tag id for CSE FW UpdateKrishna Prasad Bhat
cbfs_unverified_area_cbmem_alloc() expects a tag id to allocate space to decompress ME_RW blobs within the CBMEM area, add a tag id for it. BRANCH=firmware-brya-14505.B Change-Id: I32f44496d389e3a7e4f2573ee4e46a145f7cd927 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30mb/google/corsola: Decide EC-is-trusted logic by board revYu-Ping Wu
Kingler and Krabby's rev 0 boards both have Cr50 instead of Ti50. In order to support them with the new firmware where TPM_GOOGLE_TI50 is selected, use the board rev to determine the EC-is-trusted logic. BUG=b:237355198 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I7797eafaa7a35355d241c4ea425a4716a35a7817 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-06-30ec/google/chromeec: Update ec_commands.hYu-Ping Wu
This change copies ec_commands.h directly from the ChromiumOS EC repo, with the exception of changing the copyright header to SDPX format. Update to commit SHA1 2cbf6fbf (ec_commands: Drop VBNV read/write support). BUG=b:178689388 TEST=none BRANCH=none Change-Id: I74fa8b1171ca109dee163a7657659cdac1687450 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65469 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30mb/google/nissa: Remove WLAN power sequencing workaroundReka Norman
CB:63368 added a workaround of driving EN_PP3300_WLAN_X low in bootblock to prevent a kernel crash on warm reboot. The crash has been fixed in the kernel, so remove the workaround. Kernel fix: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3463465/ BUG=b:225261075 TEST=Wifi works on nereid, warm reboot doesn't crash the kernel Change-Id: Idb5547e65ea934954326fcc740b14a83c939432e Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-30commonlib: Handle DIR64 relocation type in FSP relocation codeSridhar Siricilla
It seems fixup or adjustment addition for relocation type EFI_IMAGE_REL_BASED_DIR64 is missing in the fsp rebasing code. The patch address the miss. Without extending the fixup for the relocation type, build system throws warnings during the rebasing of FSP-M and FSP-S blobs which are built with 64bit. Portion of build output containing warning with debug enabled cbfs lib: ................................................... E: file offset: 9218 E: file type = 4 E: file attribs = 0 E: section offset: 9230 E: section type: 12 E: TE image at offset 9234 E: TE Image 0xffed80d4 -> 0xff256234 adjust value: ff37e000 E: Relocs for RVA offset 12000 E: Num relocs in block: 18 E: reloc type a offset f40 E: Unknown reloc type: a Portion of build output after fix: .................................. E: file offset: 9218 E: file type = 4 E: file attribs = 0 E: section offset: 9230 E: section type: 12 E: TE image at offset 9234 E: TE Image 0xffed80d4 -> 0xff256234 adjust value: ff37e000 E: Relocs for RVA offset 12000^M E: Num relocs in block: 18 E: reloc type a offset f40 E: Adjusting 0x7f2e7f377024 ffee9192 -> ff267192 E: reloc type a offset f48 TEST: Integrate FSP blobs built with 64 bit and do boot test. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I894007ec50378357c00d635ec86d044710892aab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65383 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-30mb/google/nissa/var/xivu: Add gpio.c to ramstageIan Feng
Fixes a bug in Makefile.inc. BUG=b:236576117 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2664df961a1fc0cd904a5e742face20c3fc8c3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65450 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30mb/google/nissa: Add fmd for debug FSPKangheui Won
Debug FSP is ~850KiB larger than release FSP and we don't have sufficient space for nissa flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. Note: This fmd will only used for internal testing/debugging and not for the firmware in released devices. BUG=b:231395098 TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-30soc/intel/alderlake: Add BUILDING_WITH_DEBUG_FSPKangheui Won
Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ibc561498d7edcb9d7ec155f090822f1eb25d10cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65466 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-30soc/intel/alderlake: add chipset devicetree for ADL-SMichał Kopeć
Add chipset devicetree and power limits for AlderLake-S platform. Based on Intel docs #619501, #619362 and #626343. Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2022-06-30soc/nvidia/tegra124: Do resource transitionKyösti Mälkki
Change-Id: I422ece7b64bf81bcc75a414fd27f15ec330d40be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-30soc/amd/common/psp: Revert AMD_SOC_SEPARATE_EFS_SECTIONFred Reitberger
Reverting commit 1e25fd426ad8 ("soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION"). A better solution was used in commit c17330c1dddb ("mb/amd/chausie: Add EC blob into CBFS"), and this is no longer necessary. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I27a8622a1f0d871690b181a79adca225a20996ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-30soc/intel/alderlake: Add ADL-S PCI IRQ constraintsMichał Żygowski
Add ADL-S specific table with IRQ constraints to avoid accessing non-existent devices. Also when using debug FSP, silicon init would assert on assigning IRQs for non-existent devices. This patch fixes the problem. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib4464a85bc11a8603bf471ea348bbfc9481db4aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30soc/intel/alderlake/iomap: Correct the ADL-S reserved rangeMichał Żygowski
Due to incorrectly interpreted DOC #630603, the reserved range remains the same for all ADL platforms and is sync with src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was only mean for static allocations, but the rest is also reserved. The only difference between ADL-S and other ADL platforms is Trace Hub base. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-29mb/google/brask/variants/moli: remove ASPM_DISABLE for I225VRaihow Shi
Disabling the ASPM for I225V will cause I225V suspend fail, so remove ASPM_DISABLE for I225v. BUG=b:235565637 TEST=emerge-brask coreboot and check LAN_I225V sku can boot into OS. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Id4505a713a3d92cb66c189cc2963111b6e90f092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-29mb/google/skyrim: Enable fingerprint sensor in SkyrimMoises Garcia
Add fingerprint device and select UART_ACPI driver. Disable FPMCU until the proper boot segment initializes it. BUG=b:228271993 BRANCH=NONE TEST=Can add fingerprints and unlock the device using them. Signed-off-by: Moises Garcia <moisesgarcia@google.com> Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-06-29soc/intel/jasperlake: Fix PMC read_resources callbackTim Wawrzynczak
The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icf51333f438ce2597c008b48305cf5816dacd3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/elkhartlake: Fix PMC read_resources callbackTim Wawrzynczak
The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib2d8c7ffe87fdd970f3172bb4e6b2c9386859ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65460 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29mb/google/brya/variants/nivviks: Enable DDR RFIM Policy for NivviksVidya Gopalakrishnan
DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Nivviks variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=b:237238786 BRANCH=None TEST=Build and boot Nivviks. - Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Iea5c6e0c404efb8231321701ea9282347e01f75d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 14:32:33 +0000