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2022-04-11cpu/x86/smm_module_loader.c: Clean up printing the CPU mapArthur Heymans
There is no reason to do this in a separate loop. Change-Id: I7fe9f1004597602147aae72f4b754395b6b527cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decodingMichał Żygowski
Some Super I/Os may be strapped to respond on the secondary ports 0x4e/0x4f. Enable them early so that mainboard is able to initialize a serial port for example. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-SMichał Żygowski
According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for PCH-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-SMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake: Select FSP2.3 for ADL-SMichał Żygowski
The FSP available at Intel R&DC kit #1000166 indicates FSP version 2.3 in the FSP headers. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake: Introduce PCH-S symbolMichał Żygowski
Introduce SOC_INTEL_ALDERLAKE_PCH_S symbol to differentiate from the low power chipsets. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I47676723747458b8b7fe726e900843c198901bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/63455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUGSubrata Banik
This patch binds all FSP-M and FSP-S UPDs required for serial redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to choose when to enable FSP debug output redirection to serial port. For example: PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S SerialDebugMrcLevel => For controllig MRC debug level. With this change FSP debug output will only be enabled when the user enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot serial image. BUG=b:225544587 TEST=Able to build and boot brya. Also, the FSP debug log is exactly the same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63167 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-11drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirectionSubrata Banik
Commit 3ba6f8cdf (drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler) implements a native FSP debug handler. However, coreboot still can't control when to redirect FSP debug output to the serial console, i.e., at present, integrating a FSP debug binary is enough to output FSP serial messages irrespective of whether user is intended to see FSP debug log. coreboot needs additional mechanism to control FSP debug binary to redirect debug messages over serial port. This patch introduces a config `FSP_ENABLE_SERIAL_DEBUG` to control the FSP debug output, user to enable this config from site-local config file in case like to override the default FSP serial redirection behaviour in more controlled way from coreboot. There could be scenarios as below: Scenario 1: coreboot release image integrated with the FSP debug binaries, is capable of redirecting to the serial console, but coreboot decides to override the config as below to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set Scenario 2: For coreboot serial image with FSP debug binaries integrated but coreboot decides to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 Scenario 3: The final image could be a coreboot serial image with FSP serial redirection enabled to output to the serial port. CONFIG_FSP_ENABLE_SERIAL_DEBUG=y CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 BUG=b:227151510 TEST=Able to build and boot google/redrix with all scenarios between #1--#3 and able to meet the expectation as mentioned above. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-10nb/intel/sandybridge: Restore `mainboard_early_init()` callAngel Pons
Commit 7a874330919a4df9cc5b66058b4340465b7ea041 (mb/google,samsung: Drop init_bootmode_straps()) got rid of the `mainboard_early_init()` function call and weak definition in Sandy Bridge code. However, this function is still used by several Sandy Bridge mainboards, so bring back the dropped call and weak definition. The aforementioned commit did not cause any build-time errors because it did not remove the `mainboard_early_init()` function declaration. Change-Id: I82768e9a187696d42b61be44d4aa048acc19d551 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-09mb/google,samsung: Drop init_bootmode_straps()Kyösti Mälkki
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-08src/mb/facebook/fbg1701: Verify FSP and SPD binaries in bootblockFrans Hendriks
romstage uses FSP and SPD before these are verified. Verify the FSP and SPD binaries in bootblock and measure these in romstage. BUG=N/A TEST=Boot Facebook FBG1701 and check log for FSP and SPD verified in bootblock. Change-Id: I061affa5111fb14d69a8459575e0c72f71b1a1aa Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63446 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-08soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameterWerner Zeh
Commit 1a4496e79f21 (soc/{apl,glk}: Allow to select the primary graphics device) adds code to set the FSP parameter 'PrimaryVideoAdaptor' based on the enum description of the FspmUpd.h for Apollo Lake. Unfortunately, the comment in the header file does not match the implementation in the FSP and hence setting PrimaryVideoAdaptor to 'GPU_PRIMARY_IGD' will be treated as if the selection was 'GPU_PRIMARY_PCI'. This in turn leads to Linux gfx driver issues for earlier driver implementations. This commit corrects the enum values for the FSP parameter to match the implementation. TEST=Boot into Linux on mc_apl1 and verify that graphics works. Change-Id: Iedbc144fa809f6d4587f5223b235ee95579c48f7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-08soc/intel/common/cse: Show CSE device slot and function number properlySubrata Banik
This patch fixes a problem where the `is_cse_devfn_visible` function is unable to show the CSE device slot and function number properly.  BUG=b:211954778 TEST=Able to display CSE device slot and function number properly as below: Before: [DEBUG]  PCI: 00:16.0 final [WARN ]  HECI: CSE device 00.0 is disabled [WARN ]  HECI: CSE device 00.0 is disabled [WARN ]  HECI: CSE device 00.0 is disabled [WARN ]  HECI: CSE device 00.0 is disabled [WARN ]  HECI: CSE device 00.0 is disabled With this code changes: [DEBUG]  PCI: 00:16.0 final [WARN ]  HECI: CSE device 16.1 is disabled [WARN ]  HECI: CSE device 16.2 is disabled [WARN ]  HECI: CSE device 16.3 is disabled [WARN ]  HECI: CSE device 16.4 is disabled [WARN ]  HECI: CSE device 16.5 is disabled Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I76a634c64af26fc0ac24e2c0bb3a8f397a65d77b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-08soc/intel/cse: Allow calling all functions associated with `cse_final`Subrata Banik
This patch fixes a problem where `cse_final` only calls into 1 function from available `notify_func` lists. BUG=b:211954778 TEST=Able to execute `cse_final_end_of_firmware` function as part of `cse_final` call. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I04d8c9c1213ddeb9ed85473e62fcca298c0d5172 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-07mb/google/brya/var/taniks: Enable Genesys L1 max entry delayJoey Peng
The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07soc/intel/common: Update CSE sub partition updateSridhar Siricilla
The patch adds support in the CSE Sub partition update procedure to use GET_BOOT_PARTITION_INFO HECI command output to create the region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO HECI command provides CSE's RO and RW boot partition information. Existing code relies on FMD file to get the CSE's boot partition's (CSE RO and CSE RW) start and size details. This change make independent of FMD file declaration with respect to CSE RO and CSE RW. TEST=Build and verify the CSE RO and CSE RW region device information through code instrumentation. Also, did boot test on Kano system. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07ec/google/chromeec: Initialize device_path subidAkihiko Odaki
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Change-Id: I910998a5555319cf9840493a31df4934054e08ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/63384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07soc/intel/alderlake: Hook up PAVP to KconfigLean Sheng Tan
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-07soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetreeLean Sheng Tan
The FSP needs to program VrPowerDeliverDesign configuration per platform according to the platform capabilities to avoid incorrect electrial/power parameters. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I74859e6735e59a15084a9e690b43f68341862833 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power ↵Teddy Shih
consumption To achieve low power consumption, we disable unused PCIe and SATA pins at beadrix/overridetree.cb according to baseboard/devicetree.cb and mainboard schematic. Original measured beadrix board's power consumption is about 250 mW. After we disable unused PCIe and SATA pins, as well as, enable the other low power MUX CL (3487086: USB MUX: Update low power mode of MUX anx7447 used as MUX only | https://chromium-review.googlesource.com/c/chromiumos/platform/ec/ +/3487086), the measured power consumption achieves about 110 ~ 116 mW, as well as, meets Google battery life for 14 days in the suspend state and Intel low power consumption about 116 mW. BRANCH=dedede BUG=b:204882915 TEST=on beadrix, measured power consumption meets Intel power consumption. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776 Reviewed-by: Teddy Shih <teddyshihau@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07mb/google/guybrush: allow MKBP devices and disable TBMC deviceKenneth Chan
Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:227240985 BRANCH=guybrush TEST=manual test on Dewatt: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63394 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07soc/intel/denverton_ns/chip.c: add soc_acpi_name functionJeff Daly
Intel common SoC code uses SoC-specific soc_acpi_name function to generate ACPI tables, add this to Denverton Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/60991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-04-07soc/intel/denverton_ns: add common device function macrosJeff Daly
Add device function macros for Denverton similar to other SoCs Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/60990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-04-07soc/mediatek/mt8186: Disable unused powerRex-BC Chen
To save the power consumption, we disable the unused power of optional components in coreboot. BUG=none TEST=the value of power consumption is as expected. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/63247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-04-07drivers/amd/agesa/romstage.c: Move timestamp and console init upArthur Heymans
Follow-up commits move this to a common place. Change-Id: I26a37f9384a581a8a750efccc2100a5c6a6f0f85 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-07mb/google/brya/var/nereid: Add WLAN power sequenceReka Norman
There are currently two issues related to the WLAN power sequencing on nereid: - If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck in S3. - During warm reboot, if we only assert RST without pulling the power low, then the kernel crashes. As a workaround while we investigate these issues, we pull the EN high in S5, then actively drive it low in bootblock and high in romstage to make sure it goes low during warm reboot. BUG=b:227694137, b:225261075 TEST=Cold boot succeeds, and there's no kernel crash during warm reboot. Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07mb/google/brya/var/nereid: Enable pen garageReka Norman
BUG=None TEST=evtest works: Select the device event number [0-14]: 9 Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153020.275201, -------------- SYN_REPORT ------------ Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153025.848689, -------------- SYN_REPORT ------------ Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153028.383195, -------------- SYN_REPORT ------------ Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153080.869155, -------------- SYN_REPORT ------------ Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-07mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMIReka Norman
Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" The default value before updating the descriptor is Type-C, but this was chosen arbitrarily. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07soc/intel/alderlake: Add support to update descriptor at runtimeReka Norman
On nereid, we need to update the descriptor based on fw_config (see the follow-up patch), so add support to update the descriptor at runtime. This is a temporary workaround while we find a better solution. This is basically adding back the configure_pmc_descriptor() function removed in CB:63339, just making it generic and allowing it to update multiple bytes at once. BUG=b:226848617 TEST=With the following patch, Type-C and HDMI work on nereid. Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR KconfigSridhar Siricilla
The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR code which updates PMC descriptor for an intermediate ADL-P SoC stepping A0. Since intermediate ADL-P SoC is no longer supported and no board is selecting the Kconfig, so remove the code that updates PMC descriptor. TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63339 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-06ELOG: Refactor watchdog_tombstoneKyösti Mälkki
The symbol watchdog_tombstone is not really about ChromeOS but ELOG instead. This prepares for furher move of the watchdog_tombstone implementation. Change-Id: I8446fa1a395b2d17912a23b87b83277c80828874 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-06mb/ti/beaglebone/board.fmd: Use 'FLASH' as device nameArthur Heymans
FLASH is often used when accessing FMAP base and size from fmap_config.h so it's handy to be consistent with all other boards. Change-Id: Ibba938c72d42ac74dcea8e8e6478ddae510d8c03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD deviceChris.Wang
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim, clock source 0/1/2 are routed for WLAN/SD/SSD device. BUG=b:227297986 BRANCH=none TEST=Build Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODESridhar Siricilla
The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h for Comet Lake, Jasper Lake and Tiger Lake SoCs. TEST=Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06mb/google/brya: Enable dynamic debug capability for brya familySridhar Siricilla
The patch enables dynamic debug capability for Brya family of boards. BRANCH=MAIN BUG=b:153410586 TEST= Verified the CSE firmware update functionality on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-04-06soc/intel/alderlake: Enable debug driver for Alder Lake platformSridhar Siricilla
The patch enables dynamic debug capability driver for Alder Lake platform. BUG=b:153410586 TEST= Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06soc/intel/common: Add support to control coreboot and Intel SoC featuresSridhar Siricilla
The patch adds a framework to control coreboot and Intel SoC features dynamically. BIOS reads control information from OEM Section in the Descriptor Region and control the developer selected features. With the feature, debug team can control the selected SoC and coreboot features without rebuilding coreboot. In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has to be selcted from mainboard. The OEM section starts from offset:0xf00 till end of the Descriptor Region(0xfff). BUG=b:153410586 BRANCH=None TEST=Verified CSE firmware update functionality on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-04-06ec/starlabs/merlin: Add EC related files for Cezanne boardsSean Rhodes
Add EC memory layout and Q events for AMD Cezanne based boards, "Byte" and "Fighter", which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-06ec/starlabs/merlin: Correct Q event for CPU DN SPEEDSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieea1c8d0923f6ea6b13cf76525c9c4c686a92c40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06mb/starlabs/labtop: Remove subsystem device IDSean Rhodes
Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetreeUwe Poeche
This patch provides the set value for intel speed step in devicetree for FSPS. Before that in case of not set value in device tree the default value of disabled was overwritten by default enabled of FSP. Test: mainboard/siemens/mc_ehl/variants/mc_ehl1 Check status of Bit 16 in MSR 0x1a0 after boot. Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06drivers/intel/fsp1_1: Rename hob finding functionsArthur Heymans
The hob finding functions are never looped over so there is no point for the 'next' inside their name. Change-Id: I18e452d313612ba14edda479d43f2797f6c84034 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06soc/intel/common: Add IOE SBI access for TCSS functionsJohn
Meteor Lake has the IOE Die for TCSS. This change adds IOE SBI access for TCSS pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06soc/intel/common: Abstract the common TCSS functionsJohn
This change abstracts the common TCSS functions for pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06ChromeOS: Drop filling ECFW_RW/RO state in CNVSKyösti Mälkki
This field was never meant to be filled out by coreboot, because it can't know what the right value for this will be by the time the OS is running, so anything coreboot could fill in here is premature. This field is only read by the chromeos-specific `crossystem` utility, not by kernel code, so if one does not run through depthcharge there'll be many more broken assumptions in CNVS anyway. Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Add legacy mainboard_ec_running_ro()Kyösti Mälkki
Motivation is to have mainboard_chromeos_acpi_generate() do nothing else than fill ACPI \OIPG package. Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-05mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD dataChris.Wang
The value at offset 329 should be: 0x4B -> "K" not 0x48 -> "H" in ASCII code. BUG=b:224884904 TEST=Build, confirm the part number is matched the corresponding parts Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05mb/google/guybrush/var/dewatt: Override SPD file for Samsung partsRobert Zieba
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This commit overrides the default SPD files used for these parts BUG=b:224884904 TEST=Verified that Dewatt SKU1 and SKU3 boot with changes Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05soc/intel/alderlake: Add HID for DPTF Battery ParticipantVarshit B Pandya
HID is defined in Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check BAT1 device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-05drivers/intel/dptf: Add support for Battery participantVarshit B Pandya
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add support for TBAT device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TBAT device Device (TBAT) { Name (_HID, "INTC1061") // _HID: Hardware ID Name (_UID, "TBAT") // _UID: Unique ID Name (_STR, "Battery Participant") // _STR: Description String Name (PTYP, 0xC) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-04drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencingAngel Pons
Checking whether a pointer is NULL after it has been dereferenced makes zero sense. Make sure the `wifi_ssdt_write_properties()` function never gets invoked with a NULL argument for the `dev` parameter, and simplify the logic around the `is_cnvi_ddr_rfim_enabled` variable accordingly. Change-Id: I3fbc9565e7e9b4e1c14a68f6a5fd779577045236 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-04ec/starlabs/merlin: Remove comment about OPWESean Rhodes
OPWE offset didn't exist, but it does now so remove the comment about this. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a1310c779002dfb00d01a22437ea223bb406609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04mb/starlabs/lite: Add Lite Mk IV variantSean Rhodes
Tested using upstream edk2: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starlite-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04src/mb/facebook/monolith: Remove IGNORE_IASL_MISSING_DEPENDENCYFrans Hendriks
CB:63244 solved the missing dependency on _PRS The config IGNORE_IASL_MISSING_DEPENDENCY can be removed. BUG=N/A TEST=build facebook monolith and verify no IASL warning is reported. Change-Id: I0d7c99e69d56aa8ebe08b52c91ef800390263185 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63245 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04src/mb/facebook/monolith/acpi/superio.asl: Remove _PRSFrans Hendriks
IASL reports warning on missing _SRS. Devices have fixed configuration which is always enabled. Remove _PRS for this fixed configuration. BUG=N/A TEST=built facebook monolith and verify no IASL warning is reported. Change-Id: I554d3497255c1e50cdbe74b1cffc9f2c59fbae77 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63244 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04mb/hp/z220_series: Convert z220_sff_workstation into variantDamien Zammit
No functional change, just refactoring to make room for CMT variant. Built with BUILD_TIMELESS=1 and no config included before and after. $ diff master.rom build/coreboot.rom $ TESTED: boots to SeaBIOS on HP Z220 SFF Flashed bios region internally, mainboard also has FDO (flash descriptor override) jumper that allows r/w to whole flash. Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04soc/intel/alderlake: Add new CPU IDLean Sheng Tan
Add new CPU ID 0x906A3 (L0 stepping). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63302 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan
Update ADL CPU IDs per correct steppings listed in Intel Doc 626774. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04src/mb/portwell/m107: Remove IGNORE_IASL_MISSING_DEPENDENCYFrans Hendriks
CB:63248 solves the missing dependency on _PRS The config IGNORE_IASL_MISSING_DEPENDENCY can be removed. BUG=N/A TEST=Build portwell M107 Change-Id: I2ed9fdd541ba9431e59364a42dd03f60b54b6720 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63249 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04src/mb/portwell/m107/acpi/superio.asl: Remove _PRSFrans Hendriks
IASL reports warning on missing _SRS. Device has fixed configuration which is always enabled. Remove _PRS for this fixed configuration. BUG=N/A TEST=build portwell m107 Change-Id: Idbc0a67136326c9231c168bfd8fadd2539da6745 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63248 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHzEddy Lu
Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz. BUG=b:207333035 BRANCH=none TEST=built and verified adjusted I2C speed around 1MHz Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63241 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-03soc/amd/cezanne/fw.cfg: provide default SPL table binaryFelix Held
Chause doesn't get to x86 bootblock without the SPL table binary in the PSP directory table, so I assume that Majolica won't get to x86 bootblock either, since the Cezanne SoC default is not to include any SPL table binary. This was caused by a combination of commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table) that caused a regression in amdfwtool and commit c5b912f788765560c1db08f3341826b9c548b865 (soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that removed the default for the Cezanne SoC. Fix this by adding the default SPL table file back to the fw.cfg file which will get ignored by amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another SPL table binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-02soc/intel/common/block/fast_spi: Refactor ROM caching implementationSubrata Banik
This patch removes different implementation to cache the SPI ROM between early and later boot stage where SPI ROM caching doesn't need even advanced implementation like `mtrr_use_temp_range()` as SPI ROM ranage is always mapped to below 4GB hence, simple `set_var_mtrr()` function can be sufficient without any additional complexity. BUG=b:225766934 TEST=Calling into `fast_spi_cache_bios_region()` from ramstage is able to update the temporary variable range MTRRs and showed ~44ms of boot time savings as below: Before: 90:starting to load payload             1,084,052 (14)   15:starting LZMA decompress (ignore for x86)   1,084,121 (68)   16:finished LZMA decompress (ignore for x86)   1,140,742 (56,620) After: 90:starting to load payload              1,090,433 (14)   15:starting LZMA decompress (ignore for x86)   1,090,650 (217)   16:finished LZMA decompress (ignore for x86)   1,102,896 (12,245) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63221 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02cpu/x86/mtrr: Delay removing `temp` variable range MTRR snapshotSubrata Banik
This patch delays removing `temporary` MTRR snapshots to avoid conflicts with other operations attached with same `BS_PAYLOAD_BOOT/BS_ON_EXIT` boot state. BUG=b:225766934 TEST=Having variable MTRR snapshot using display_mtrrs() is able to list only the permanent MTRRs and all temporary MTRRs are removed prior to boot to payload. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I602dca989745159d013d6573191861b296f5d3ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02{cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR countSubrata Banik
This patch replaces the implementation that is used to get the number of variable MTRRs with `get_var_mtrr_count()` function. BUG=b:225766934 TEST=Able to build and boot google/redrix board to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4751add9c45374e60b7a425df87d06f52e6fcb8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02cpu/x86/mtrr: Make useful MTRR functions available for all boot stagesSubrata Banik
This patch migrates a few useful MTRR functions as below from `earlymtrr.c` file to newly created common stage file `mtrrlib.c`. 1. get_free_var_mtrr 2. set_var_mtrr 3. clear_all_var_mtrr These functions can be used to perform the MTRR programming from IA common code SPI driver as `fast_spi.c` without requiring two separate implementations for early boot stage (till romstage) and for ramstage onwards. BUG=b:225766934 TEST=Able to build and boot google/redrix board to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2c62a04a36d3169545c3128b4231992ad9b3699d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02drivers/intel/fsp2_0: Add provision to extract FSP Performance DataSubrata Banik
This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp from FPDT (Firmware Performance Data Table) and display right after FSP-S exits (from `fsp_silicon_init()` function), based on SoC user selects the required `DISPLAY_FSP_TIMESTAMPS` config. The prerequisite to this implementation is to have FSP binary built with `PcdFspPerformanceEnable` PCD set to `TRUE` to allow FSP to populate the FPDT HOB. BUG=b:216635831 TEST=Able to dump FSP performance data with DISPLAY_FSP_TIMESTAMPS Kconfig selected and met the FSP prerequisites. +--------------------------------------------------+ |------ FSP Performance Timestamp Table Dump ------| +--------------------------------------------------+ | Perf-ID Timestamp(ms) String/GUID | +--------------------------------------------------+ 0 460253 SEC/52c05b14-0b98-496c-bc3b04b50211d680 50 460263 PEI/52c05b14-0b98-496c-bc3b04b50211d680 40 460274 PreMem/52c05b14-0b98-496c-bc3b04b50211d680 1 495803 9b3ada4f-ae56-4c24-8deaf03b7558ae50 2 508959 9b3ada4f-ae56-4c24-8deaf03b7558ae50 1 515253 6141e486-7543-4f1a-a579ff532ed78e75 2 525453 6141e486-7543-4f1a-a579ff532ed78e75 1 532059 baeb5bee-5b33-480a-8ab7b29c85e7ceab 2 546806 baeb5bee-5b33-480a-8ab7b29c85e7ceab 1 553302 1b04374d-fa9c-420f-ac62fee6d45e8443 2 563859 1b04374d-fa9c-420f-ac62fee6d45e8443 1 569955 88c17e54-ebfe-4531-a992581029f58126 2 575753 88c17e54-ebfe-4531-a992581029f58126 1 582099 a8499e65-a6f6-48b0-96db45c266030d83 50f0 599599 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 50f1 716649 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 2 728507 a8499e65-a6f6-48b0-96db45c266030d83 1 734755 9e1cc850-6731-4848-87526673c7005eee .... Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-04-02mb/google/skyrim: Fix ESPI communication issuesKarthikeyan Ramasubramanian
* Use dedicated ALERT pin to resolve NO_RESPONSE error/status while getting target configuration. * Configure the ESPI to operate at 16 MHZ since operating at 33 MHz causes boot stall. BUG=b:226635441 TEST=Build and Boot to OS in Skyrim. Ensure that EC <-> AP communication is working fine through Host Command debug logs in EC console, ectool version command. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/63286 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02herobrine: fix emmc and sd card clocksShelley Chen
Found an issue where emmc and sd clocks were being misconfigured due to using incorrect integer values when called instead of the defined enums. Fixing by splitting the clock_configure_sdcc() function into two (sdcc1 and sdcc2) as there was no commonality between the two cases anyway. As a result, we can also get rid of the clk_sdcc enum. BUG=b:198627043 BRANCH=None TEST=build herobrine image and test in conjunction with CB:63289 make sure assert is not thrown. Change-Id: I68f9167499ede057922135623a4b04202f4da9b5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-01mb/dell/snb_ivb_workstations: Choose correct PCH for OptiPlex 9010Angel Pons
The Dell OptiPlex 9010 uses a Q77 PCH, which is Panther Point. The only difference is the definition of the `CROS_GPIO_DEVICE_NAME` macro, which is not used for non-ChromeOS coreboot builds. Change-Id: I7ad07b464aef24f7749c3fe9300b7f7dd865e47b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-04-01mb/dell/snb_ivb_workstations: Fix SMBIOS slot desc for PCH PCIe portsAngel Pons
The PCH's PCIe ports do not support Gen3 speeds, only Gen1/Gen2. Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-04-01mb/starlabs/labtop: Disable legacy_8254_timer by defaultSean Rhodes
It was enabled due to known compatibility issues with Qubes OS. Since the release of R4.1.0, this issue is no longer present so it can be disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iab6048dc93112b9365f0c2b46225569073eb32f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-04-01mb/google/guybrush: Remove elog_gsmi_cb_mainboard_log_wake_sourceRob Barnes
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes eSPI transactions. If the SMI interrupts an ongoing eSPI transaction from the OS it will conflict and cause failures. Removing this call to avoid conflicts. This can be re-enabled after refactoring google_chromeec_get_mask to use ACPI MMIO. BUG=b:227163985 BRANCH=gubyrush TEST=No 164 errors detected during suspend_stress_test /sys/firmware/log output after resume before change: SMI# #1 ELOG: Event(B0) added with size 9 at 2022-03-31 19:52:51 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:52:51 UTC Chrome EC: clear events_b mask to 0x0000000000000000 after change: SMI# #6 ELOG: Event(B0) added with size 9 at 2022-03-31 19:50:19 UTC GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 ELOG: Event(9F) added with size 14 at 2022-03-31 19:50:19 UTC Change-Id: I3320e3fb8bd9e9e0db84332e1d147a0af25f7601 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63280 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/starlabs/laptop: Enable rtd3 for SSD on TGLStephen Edworthy
Enabling rtd3 reduces power consumption when the SSD is idle. Tested and verified on the StarBook Mk V (TGL), using PowerTop on Manjaro 21.2.5 GNOME at 20% Brightness. Signed-off-by: Stephen Edworthy <stephen@starlabs.systems> Change-Id: I0d8aa185a322bb8d1aba51ccaab03c521cec2770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-04-01mb/google/brya/var/nereid: Add separate VBT for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Cq-Depend: chrome-internal:4650256 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6a90d3d86b32f73ec0130e582539d1c5b045da62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01mb/google/brya/var/nereid: Disable C1 PMC mux conn for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I039c30f95d959dba489b24b6938d08da937c5e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01soc/intel/common/tcss: Check conn device enabled in tcss_get_port_infoReka Norman
BUG=b:226848617 TEST=With the following change, the nereid C1 PMC mux conn is disabled based on fw_config, allowing HDMI to work. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I487f3ca4be4ead0c5dfb46e9eb19de5ae9b9bda9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63237 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/starlabs/labtop: Add CMOS defaults for EC functionsSean Rhodes
Set the CMOS defaults for EC related functions: * Function Lock = Enabled * Trackpad = Enabled * Keyboard Backlight Brightness = Off * Keyboard Backlight State = Enabled Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I528c30893d2af87584a09f23b982b5f36b37a873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-01device/i2c_bus: Constify i2c_busdev and i2c_linkMatt DeVillier
Change-Id: If795087ecdaea24ad7834dcc6d5bf6a72f2aea8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-01mb/google/skyrim/var/skyrim: Add ELAN trackpad configKarthikeyan Ramasubramanian
Add support for ELAN trackpad on I2C0 bus. BUG=None TEST=Build and boot to OS in Skyrim. Perform evtest on Elan trackpad. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia1522af3f35ef131dda74c4aabecc4fa532dfbec Reviewed-on: https://review.coreboot.org/c/coreboot/+/63236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-01arch/x86/postcar: Use a separate stack for C executionArthur Heymans
Add a stack in .bss for C execution. This will make it easier to move the setup of MTRRs in C code. Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-01mb/amd/majolica/port_descriptors: clean up variable namesFred Reitberger
Removing unnecessary "czn" in variable name. Majolica is always a cezanne. TEST=Timeless build Change-Id: I490111ecea84c934585d0bbd623486fba76eb7f1 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63261 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/amd/chausie/port_descriptors: clean up variable namesFred Reitberger
Remove "czn" from the variable names since chausie does not use cezanne. TEST=Timeless build Change-Id: I8cc854f4c60707c7fec5cd7fef1c4550883cd45a Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-01soc/amd/sabrina/makefile: drop multilevel option in amdfwtool callsFelix Held
Since Sabrina uses the image slot header (ISH) that depends on the AMD A/B recovery scheme that depends on the multi-level PSP directory support, the multi-level support gets automatically selected by passing Sabrina as SoC name to amdfwtool, so passing the --multilevel command line switch to amdfwtool isn't needed. TEST=Timeless build results in identical binary for chausie Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-01soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltageFelix Held
The fch_i23c_pad_init implementation was written without looking at any reference code and turned out to not work properly on hardware. Before this function writes to the MISC_I23C_PAD_CTRL registers, the value read back is 0x3000003c which results in the I2C bus communication to work while the 0x300003fc the code writes to the register breaks the I2C communication. Removing the code that sets bits 6..9 fixes the I2C bus communication. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63234 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/sabrina/i2c: handle all I2C pads as I23C pad typeFelix Held
Contradicting the PPR #57243 version 1.56, the I2C3 pad control register in the MISC ACPIMMIO region is the same new I23C pad type as the corresponding registers for I2C0..2 and not the older I2C pad control register type used on Picasso and Cezanne. All I2C pads being of the new I23C type is in line with the GPIOMUX settings for the pins used by I2C0..3 that can alternatively connect the pins to an I3C controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitionsFelix Held
According to PPR #57243 version 1.56, the IOMUX setting 2 of the pins 19 and 20 is the I3C3 controller and not the I2C3 controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9688f1816aa840c64441495ed451997a474b306f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63232 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/common/block/i2c/i23c_pad_ctrl: invert and maskFelix Held
When masking out bits with an and mask, the bit mask needs to be inverted. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63222 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in defineFelix Held
I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers both bits 6 and 7. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/intel/alderlake: Add HID for DPTF Power ParticipantVarshit B Pandya
BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-01drivers/intel/dptf: Add support for Power participantVarshit B Pandya
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) Add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "INTC1060") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ixAlan Huang
Turn off the NFC power which is controlled by GPP_D3 to save power in S0ix states. For an USB device, the S0ix hook is needed for the on/off operations to take place. BUG=b:202737385 BRANCH=firmware-brya-14505.B TEST=measure the voltage of GPP_D3 in S0ix states Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-01arch/x86/Kconfig: Drop obsolete fixed ramstage symbolsArthur Heymans
On x86 ramstage is always relocated at runtime in cbmem so there is no need to have this configurable in Kconfig. Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200msCasper Chang
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times are greater than 500ms, which is the spec for Chromebooks. The actual kernel timing has been measured, and given the ACPI delay after deasserting reset in addition to the delay until the kernel driver accesses the device, delaying only 200ms in the ACPI method is also sufficient to meet the 300ms requirement. BUG=b:223936777 BRANCH=none TEST=build and test touchscreen function on DUT. TEST=suspend, wake DUT and check touchscreen function. Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1Reka Norman
C0 has no redriver, so enable SBU muxing in the SoC. C1 has a redriver which does SBU muxing, so disable SBU muxing in the SoC. However, this also disables AUX biasing when the pins are configured as NF6. So instead configure the C1 AUX bias pins as GPO. BUG=b:227259673 TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-01drivers/intel/fsp1_1: Reduce scope of functionsArthur Heymans
Reduce scope of get_next_hob and drop unused functions. Change-Id: I81007295ed2d1592c4d829cbb277c0726d89ea4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-04-01mb/clevo/tgl-u: add new board L14xMUMichael Niewöhner
Add new board Clevo L14xMU (TGL). GPIOs were configured based on schematics. Tested and working: - On-board RAM (M471A1G44AB0-CWE) - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1) - Graphics (GOP driver), including HDMI - Keyboard - I2C touchpad (including interrupt) - TPM (with interrupt on Windows, only polling on Linux [1]) - microSD Card reader - both NVME ports - Speakers - Microphone - Camera - WLAN/BT (CNVi) - All USB2/3 ports including Type-C - Thunderbolt detects my work laptop in TB Control Center (I couldn't test anything more due to security policy.) - TianoCore - internal flashing with flashrom on vendor firmware Note on TPM: The vendor sets Intel PTT to default-on in newer CSME images, which conflicts with the dTPM. Currently, there are two ways to make it work: 1) Boot vendor firmware once to let it disable PTT via CSME firmware feature override. 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to disabled. Boots fine: - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6) - Windows 10 21H2 (Build 19044.1586) Untested: - Thunderbolt (see above) - Type-C DisplayPort - S-ATA Doesn't work: - TPM interrupt on Linux [1] - All EC related functions - EC driver is WIP - WLAN/BT (PCIe) - gets detected but can't be enabled - 3G/LTE (not powered without EC driver) - Fn-Keys - S0ix - UCSI - Fan control - Battery info [1] https://lkml.org/lkml/2021/5/1/103 Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-01cpu/intel/fit: Clear the FIT table when setting pointerArthur Heymans
When rebuilding coreboot the empty fit table added to added to CBFS stays the same so the build process sees no reason to update the file. In the meantime ifittool did update that file for instance to add microcode update entries. So each time coreboot is rebuilt the entries are appended to the FIT table which runs out of space at some point. One way to deal with this is to clear the fit table when setting the pointer inside the bootblock. TESTED: Now running 'make' again on prodrive/hermes does not report an error with a filled FIT table. Change-Id: Ia20a489dc90a4ae704e9ee6d532766899f83ffcc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63036 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 14:19:06 +0000