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Tested on Thinkpad X201: PEG device hidden.
Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35744
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On these CPUs the MCHBAR window is 16KiB large. This code was just
copied from SNB.
Change-Id: I263cfc678a2eb8eeee8ab9157c749359064a9be8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This properly sets up the chipset initialization registers, instead of
replaying an RCBA dump.
The information is taken from the EDS and from the thinkpad x201
vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume
from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.
Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing.
Add them to make sure that the BAR0 doesn't change when running PCI
resource allocation.
Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The extra PCI bus RST# and 200ms delay there was workaround
for custom add-on hardware.
Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.
Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.
Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Minimize use of hard-coded value for acpi_table_header->revision to soft
code. Replace with macro defined in arch/acpi.h for FADT and with the
get_acpi_table_revision function for SSDT.
Change-Id: I99e59afc1a87203499d2da6dedaedfa643ca7eac
Signed-off-by: Sourabh Kashyap <Sourabhka@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35539
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Auto-discoverable PCI devices do not require field .enable_dev
of chip_operations to be set. They are matched with PCI drivers
by the use of PCI vendor and device ID fields.
The name given for the chip_operations struct must match the
pathname the way it is present in the devicetree.cb files. If
there was no match, util/sconfig would currently choose to
use the empty weak declaration it creates in static.c file.
Change-Id: I684a087a1f8ee4e1a5fd83450cd371fcfdbb6847
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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STACK_SIZE value needs to be changed from hex to decimal,
since -Wstack-usage doesn't recognize hexadecimal numbers anymore.
Change-Id: I73606d347194af5de5882a3387a4a5db17f9d94b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib8a08e9f854b2b0786c69943d6dbb66abe3ad4d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33438
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SPI flash component requirement for Kukui family is 8M so we should
update FMAP for that:
- Add more comments for alignment and size recommendation.
- Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M.
- BOOTBLOCK: 32K->128K, aligned with other ARM boards.
- Preserve RW_DDR_TRAINING for new calibration.
- Reorder the sections for better alignment.
- RW_MISC to contain RW sections that should be merged when creating AU image.
BUG=b:134624821
TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin:
# name start end size
RW_LEGACY 00700000 00800000 00100000
RW_SHARED 006f7000 00700000 00009000
RW_UNUSED 006f8000 00700000 00008000
SHARED_DATA 006f7000 006f8000 00001000
RW_SECTION_B 00580000 006f7000 00177000
RW_FWID_B 006f6f00 006f7000 00000100
FW_MAIN_B 00582000 006f6f00 00174f00
VBLOCK_B 00580000 00582000 00002000
RW_MISC 00577000 00580000 00009000
RW_ELOG 0057f000 00580000 00001000
RW_DDR_TRAINING 0057d000 0057f000 00002000
RW_NVRAM 0057b000 0057d000 00002000
RW_VPD 00577000 0057b000 00004000
RW_SECTION_A 00400000 00577000 00177000
RW_FWID_A 00576f00 00577000 00000100
FW_MAIN_A 00402000 00576f00 00174f00
VBLOCK_A 00400000 00402000 00002000
WP_RO 00000000 00400000 00400000
RO_VPD 003f8000 00400000 00008000
RO_SECTION 00000000 003f8000 003f8000
RO_FRID 003f7f00 003f8000 00000100
GBB 003f5000 003f7f00 00002f00
COREBOOT 00021000 003f5000 003d4000
FMAP 00020000 00021000 00001000
BOOTBLOCK 00000000 00020000 00020000
Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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ONBOARD_MICRON_MEM and ONBOARD_SAMSUNG_MEM are available.
These are used to determine if Samsung or Micron onboard memory is
assembled. This can not detected run-time.
Choice is replaced by one config.
Only oldest HW revision contains Samsung module, so set
CONFIG_ONBOARD_SAMSUNG memory to default No.
BUG=N/A
TEST=Boot and verified on Facebook FBG-1701
Change-Id: Id65e92bd4b8d4fe3a6b87dec9bf77e3a62e1be96
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Before oprom is executed, no check is performed if rom passes verification.
Add call to verified_boot_should_run_oprom() to verify the oprom.
verified_boot_should_run_oprom() expects and rom address as input pointer.
*rom is added as input parameter to should_run_oprom() which must be parsed
to verified_boot_should_run_oprom()..
BUG=N/A
TEST=Created verified binary and verify logging on Facebook FBG1701
Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Some VR parameter values for KBL-U with GT3 graphics are different from
values for other CPUs in this series [1]. However, GT3 iGPU will never
be detected, since the igd_id variable is compared with the LPC device
PCI ID. The patch fixes this bug.
[1] page 109, 7th Generation Intel(R) Processor Families for U/Y
Platforms and 8th Generation Intel(R) Processor Family for U Quad
Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
Document Number: 334661-006
Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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According to the documentation[1], the Loadline in the unslased GT VR
domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC).
[1] page 109, 7th Generation Intel(R) Processor Families for U/Y
Platforms and 8th Generation Intel(R) Processor Family for U Quad
Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
Document Number: 334661-006
Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35781
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds missing Intel HD/Iris iGPU PCI IDs for Kaby Lake processors and
updates the platform report for these devices.
These changes are in accordance with the documentation:
[*] page 10, Intel(R) Open Source HD Graphics and Intel Iris(TM) Plus
Graphics for the 2016 - 2017 Intel Core(TM) Processors, Celeron(TM)
Processors, and Pentium(TM) Processors based on the "Kaby Lake"
Platform. Programmer's Reference Manual. Volume 4: Configurations.
January 2017, Revision 1.0
Doc Ref # IHD-OS-KBL-Vol 4-1.17
[*] Linux kernel sources: include/drm/i915_pciids.h
Change-Id: I1cd1e4ab82f756141f8f13edf1c17f726166dffb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Adds missing Intel HD/Iris iGPU PCI IDs for Skylake processors
These changes are in accordance with the documentation:
[*] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM)
Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference
Manual. Volume 4: Configurations. May 2016, Revision 1.0
Doc Ref # IHD-OS-SKL-Vol 4-05.16
Change-Id: I0ba6e58ec3916dceea00519ac5a51503573e8935
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35493
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the DC Current Specifications [1], the current limit for
the graphical VR domain (Iccmax_gt) isn't same for different Kaby Lake S
CPUs. This value should depend on the iGPU model and processor TDP:
+---------------------+-----+------------+
| Segment | TDP | Icc_max GT |
+---------------------+-----+------------+
| Dual Core GT2/GT1 | 35W | |
| Dual Core GT2 | 51W | 48 A |
| Dual Core GT1 | 54W | |
+---------------------+-----+------------+
| Quad Core GT2 | 35W | 35 A |
+---------------------+-----+------------+
| Quad Core GT2 | 65W | 45 A |
| Quad Core GT2 K-SKU | 91W | |
+---------------------+-----+------------+
This patch adds the remaining Iccmax_gt current limit values from the
documentation [1].
[1] 7th Generation Intel(R) Processor Families for S Platforms and
Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1,
December 2018, Document Number: 335195-003
Change-Id: I19766e4f8fab6b48565b65ed4cf13efbc213e654
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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No support is available in mainboard.
Add support to mainboard:
- Add mb_log_list[]
- Add routine mb_crtm()
BUG=N/A
TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701
Change-Id: I5120ffb6af0b41520056e1773f63b7b2f34a2460
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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The vendorcode for verified boot is uploaded, but not used by a mainboard.
Add support to the mainboard for verified boot.
The items to be verifed are placed in board_verified_boot.c
BUG=N/A
TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701 rev 0-2
Change-Id: I3ea0a95287977df0dea13e05acedd5406538a6ee
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33463
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create verified boot support, which includes verifiication of bootblock.
This feature use the vendorcode/eltan/security/lib.
cbfs_locator is used to init the verified boot support.
vendor_secure_prepare() and vendor_secure_locate() are used to preform the
required action in each stage.
The next lists will be used for verification:
* bootblock_verify_list
* postcar_verify_list
* romstage_verify_list
* ramstage_verify_list
BUG=N/A
TEST=Created binary and verify logging on Facebook FBG-1701
Change-Id: If6c1423b0b4a309cefb7fe7a29d5100ba289e0b4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Create measured boot.
This feature uses the vendorcode/eltan/security/lib.
Measure boot can work with and without Verified boot enabled.
The function mb_measure() is starting point for the support. This
function will be called by the common Verified boot code.
BUG=N/A
TEST=Created binary and verify logging on Facebook FBG-1701
Change-Id: I7f880a17e240515dd42d57383b5ddddf576985b0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Add a SSDT on qemu and place BOOT0000 inside it to allow testing
the google firmware kernel module in qemu.
Tested on Qemu Q35.
Change-Id: Ibd1b2c2f4fc3db9ae8f338b0d53b2d00ea2c4190
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HIMANSHU SAHDEV <sahdev.himan@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Fix regression with commit d53fd70 intel/smm/gen1: Use smm_subregion().
The bitmask on SMRR register parameter was inverted for
selected models.
Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Don't set a default bus type for the Chrome EC on x86. The platform
must select the bus, typically LPC or ESPI.
BUG=b:140055300
TEST=Build tested only
Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Previously all boards using eSPI for the Chrome EC just called it
LPC as the code for the chrome EC is the same between the two
busses.
I'm adding a new Kconfig symbol to specify eSPI, so switch the
boards that actually use eSPI to that symbol and add the LPC
symbol to all the others.
The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default
to enabled for x86 platforms, so one symbol or the other needs to be
specified for each platform.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add new config option to validate the Intel firmware descriptor against
the fmap layout. This will prevent a firmware descriptor from being used
that could corrupt regions of the bootimage in certian circumstances.
BUG=chromium:992215
TEST=Build firmware image with mismached decriptor and fmp
Without VALIDATE_INTEL_DESCRIPTOR set firmware builds
With VALIDATE_INTEL_DESCRIPTOR set error is shown with mismached
regions
Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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An original code had a wrong register address 0x27 for AHCI BAR.
The value was aligned incidentally by the code specific of
the pci_read_config32 function to the correct address 0x24.
All 0x24 values in sata.c were changed to the symbolic name
PCI_BASE_ADDRESS_5 and the code was optimized.
An equivalent code was tested on a real hardware.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Connected 4K monitor is not configured at max resolution. The
framebuffer size is too small.
Increase the framebuffer size to 64MB. This is sufficient for max
configuration of 1 HDMI monitor combined with internal LCD panel.
BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add defines to have some more readable code for devcietree.cb.
BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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PCB version is determined using inb() in actual code.
Create function mainboard_read_pcb_version to read pcb version.
BUG=N/A
TEST=Boot and verified on Facebook FBG-1701
Change-Id: I7c16627f468d84ca4ad2aab8bf9fb555f50dc23c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These were unused and somewhat cryptic, assumed purpose was to store
pre-CBMEM timestamps in various PCI config space locations.
Change-Id: I074294446501d49a9bd3c823a2a794c33f443168
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.
Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When creating the IRQ routing, referenced device and
function number are always of the same PCI device.
Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG: None
TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>
Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function does not otherwise need dev.
Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.
Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Disable memory channel by HW strap pin. Using for factory
debug.
BUG=b:139773082
BRANCH=N/A
TEST=Rework HW strap pin and check /proc/mem_info
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Two fields of struct sdram_params are renamed for future CL of DRAM full
calibration. Field 'impedance' is also removed.
BUG=none
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TESTED on Asus P5QC.
Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be
calibrated with different vcore voltages to get correct parameters.
A new API is added to allow changing vcore voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vcore voltage with multimeter
Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread
on HyperThreading enabled platforms, to prevent race conditions and
resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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A missing definition of gameport base (PNP io 0x60) will cause
an automatic address assignment during PCI/PNP enumeration, which
won't obey limit 0x7ff. This will cause the enumeration to fail
as other devices already have the values enabled.
The symptoms are: not working USB, PS/2, garbled UART console,
not working PCIe GPUs and crashes. Probably because of wrongly
assigned IO ports.
Example of log (shortened):
Done reading resources.
Setting resources...
!! Resource didn't fit !!
aligned base 1000 size 1000 limit 2e7
1fff needs to be <= 2e7 (limit)
PCI: 00:1c.0 1c * [0x0 - 0xfff] io
!! Resource didn't fit !!
aligned base 1000 size 1000 limit 2e7
1fff needs to be <= 2e7 (limit)
PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io
!! Resource didn't fit !!
aligned base 1000 size 1000 limit 2e7
1fff needs to be <= 2e7 (limit)
PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io
!! Resource didn't fit !!
aligned base 400 size 10 limit 2e7
40f needs to be <= 2e7 (limit)
PCI: 00:1f.2 20 * [0x3080 - 0x308f] io
!! Resource didn't fit !!
...
ERROR: PCI: 00:02.0 14 io size: 0x0000000008 not assigned
...
ERROR: PCI: 00:1f.2 10 io size: 0x0000000008 not assigned
ERROR: PCI: 00:1f.2 14 io size: 0x0000000004 not assigned
ERROR: PCI: 00:1f.2 18 io size: 0x0000000008 not assigned
ERROR: PCI: 00:1f.2 1c io size: 0x0000000004 not assigned
ERROR: PCI: 00:1f.2 20 io size: 0x0000000010 not assigned
...
PCI: 00:1b.0 subsystem <- 8086/27d8
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 8086/27d0
PCI: 00:1c.0 cmd <- 107
PCI: 00:1c.1 brids70c01mcu0PeC: 0
dV0i8s0immicrocode: upd10a00000y0025 x666600CPU physiaB 0 0 e k
MTRR cheaeu60zeAttemfWaiting for 1st Sot AP: slot 1 apic_L0ecl0zsax a
aInitiNntt kac:oIG0 Ua dUrSGSGL Ct0C07fintel_vga_int15_h
VGA Option ROM wa7..Azalia0Azalia: codkAbCiPCI: 00:1c.0 init finished
We can see the ports probably started to collide after the activation
of 00:1c.0 device. A debug run with compiled SPEW shows the problem
with enumeration:
PCI: 00:1f.1 18 * [0x50b8 - 0x50bf] io
PCI: 00:1f.2 10 * [0x50c0 - 0x50c7] io
PCI: 00:1f.2 18 * [0x50c8 - 0x50cf] io
PCI: 00:1f.1 14 * [0x50d0 - 0x50d3] io
PCI: 00:1f.1 1c * [0x50d4 - 0x50d7] io
PCI: 00:1f.2 14 * [0x50d8 - 0x50db] io
PCI: 00:1f.2 1c * [0x50dc - 0x50df] io
PNP: 002e.7 60 * [0x50e0 - 0x50e0] io <-- gameport base
DOMAIN: 0000 io: base: 50e1 size: 40e1 align: 12 gran: 0 limit: 7ff done
Notice a weird base for DOMAIN, along with the limit.
Adding a definition of gameport (0x220) as a workaround fixes
the problems.
The gameport should be still disabled thanks to disable bits
(W83627THF datasheet is little bit chaotic). I didn't find any info
if the gameport is available on some pads of the motherboard.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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This is a PCI standard register, no need to alias its
definitions under different names.
Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Implementation of ich_pci_dev_enable_resources() used to have
a custom implementation to program PCI subsystem IDs for the
(legacy) PCI bus bridge.
With the local implementation removed, we no longer need the
custom .enable_resources callback.
Change-Id: I6f73fd0e4d5a1829d1555455c9a143f1d18a6116
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Petr Cvek <petrcvekcz@gmail.com>
|
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The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.
We have some use for PCI bridge configurations and
resets in romstages, so expose them.
Change-Id: Ia97a4e1f1b4c80b3dae800d80615bdc118414ed3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Many supported SST flashes use the AAI OP (0xad) to write.
TESTED on Thinkpad X60 with SST25VF016B, flashrom can use AAI_WRITE op
with locked down SPIOPS.
Change-Id: Ica72eda04a8d9f4e563987871b1640565c6e7e12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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This also reworks the interface to override OPs from the devicetree to
match the interface in sb/intel/common/spi.
Change-Id: I534e989279d771ec4c0249af325bc3b30a661145
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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* Disable SATA controller and related configs.
* Disable PCIe root ports 10 and related configs.
-> Board uses integrated CnVi for WLAN
* Disable PCIe root ports 12 and related configs.
-> Board uses WWAN intarfaced over USB
Change-Id: If9d49cef290dcccb114afccc3ac34cd072802ea4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35723
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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drallion uses below LPSS controllers:
I2C: 0/1/4
GSPI: None
UART: 0(Console)
BUG=b:141575294
Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
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While the list of prerequisities is not created with romcc,
we need to simulate it since different set of header files
will is used.
Change-Id: Ib799c872b5280e2035126f9660e04e51acc4b1a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35601
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Apparently romcc-bootblock just barely built without
XMM registers.
Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
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Allow to set a lower temperature limit, as the currently hard-coded
25C may be to low for a given temperature sensor. Also enable smoo-
thing, currently hard-coded to the maximum interval of 35s, and set
the hysteresis value.
Change-Id: I5fde1cf909e8fbbaf8a345790b00c58a73c19ef8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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We accidentally converted an `int` return value to an `unsigned`,
making it impossible to check for errors with `< 0`. Fix that by
using an `int` variable.
Change-Id: I5433c27e334bc177913e138df83118b128c674b7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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Fixes related GCC warnings.
Change-Id: I803fc0e005390ebd8a5e3ac6886ee968c56c3a34
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend
on VENDOR_LENOVO. Thus, it couldn't be selected by boards from
other vendors. So we add another Kconfig that selects it
here.
NB. It's still unclear how the two drivers in this directory
are related (at24rf08c and lenovo_serial). From the code, it
doesn't look like the latter belongs here.
Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger
EEPROM parts), then reads bytes up to a given length into a buffer.
Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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According to the documentation [1], SKL-H Halo GT4E (Iris Pro Graphics
P580) PCI ID should be 0x193B.
[1] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM)
Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference
Manual. Volume 4: Configurations. May 2016, Revision 1.0
Doc Ref # IHD-OS-SKL-Vol 4-05.16
Change-Id: Id62fe3ec26779d51b748efd271db565ade1e3ee0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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The new macro name contains the number of cores:
PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core
PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core
Change-Id: I190181b213d55865aa577ae5baff179fef95afde
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To support mt8183 power saving during suspend to RAM, this patch loads
SPM firmware to support SPM suspend. SPM needs its own firmware to do
these power saving in the right timing under correct conditions. After
linux PM suspends, SPM is able to turn off power for the last CPU and do
more power saving for the SoC such as DRAM self-refresh mode and turning
off 26M crystal.
BUG=none
BRANCH=none
TEST=suspend/resume passes for LPDDR4 3200
Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Make sure to match devices on the root bus only. This fixes an issue
where the SoC returned "MCHC" as ACPI name for devices behind bridge
devices, as the DEVFN matched.
Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI
path no longer contains invalid names.
Tested on Supermicro X11SSH-TF.
Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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This removes the "ifdef ACPI" which is not needed here as we currently
don't include gpio.h in any asl file.
Change-Id: I803bbee5933eda9423a9bc9fcaea9e905e3ac78e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35543
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This fixes the warning that power_on_after_fail could not be found,
adds a default config and adds the parameter hyper_threading.
Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35526
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The HWID in vboot GBB is an identifier for machine model. On Chrome OS,
that should be provisioned in manufacturing process (by collecting real
hardware information), and will be checked in system startup.
For bring up developers, they usually prefer to generate a test-only
string for HWID. However that format was not well documented and cause
problems. Further more, most Chromebooks are using HWID v3+ today while
the test-only HWID is usually v2. Non-Chrome OS developers may also
prefer their own format.
To simplify development process, the GBB_CONFIG now defaults to empty
string, and will be replaced by a board-specific test-only v2 HWID
automatically. Developers can still override that in mainboard Kconfig
if they prefer v3 or other arbitrary format.
BUG=b:140067412
TEST=Built 'kukui' successfully. Removed kukui GBB config and built
again, still seeing correct test HWID.
Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.
Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I959cdc08d43fea28f8bbc649cd46bab5656d6ca8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The typical do { } while (0) did not work, so
provide empty stub function instead.
Change-Id: Ieb0c33b082b4c4453d29d917f46561c0e672d09a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change in ssus_disable_internal_pull() is for romcc
compatibility.
Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.
Change-Id: Iee12a5d1781c869b20bc14a52ecbf23474caa3fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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If VBOOT is used on a mainboard based on fsp_broadwell_de then VBOOT
needs to be able to write to its NV data which may be stored on the SPI
flash. Enable write access to the SPI flash on SoC level. If the
mainboard does not use VBOOT the linker will drop the extra code. The
benefit is that this code is at least compiled and therefore build
tested with fsp_broadwell_de.
Change-Id: I90a2d30f5749c75df2b286dce6779f10dde62632
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cometlake pch EDS vol1 section 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on drallion platform, able to boot up into OS and stay
at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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BUG=b:141734594
Change-Id: I419f7d11dffebe6c44eefa05750834d07d19857b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Source files including this may have locally defined
__SIMPLE_DEVICE__ so this cannot be placed in <rules.h>.
Change-Id: I2336111b871203f1628c3c47027d4052c37899dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35653
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Source files including this may have locally defined
__SIMPLE_DEVICE__ so this cannot be placed in <rules.h>.
Change-Id: If700dd10fd5e082568cd6866bfd802fc2e021806
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is safe to assume this to be copy-paste from eg. i945
where registers of said PCI device were read.
Change-Id: I387b7fd6caf317543a6438f973d9e1d96e418de3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35668
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The filename chip.h has a special purpose with the generation
of static devicetree, where the configuration structure name matches
the path to the chip.h file. For example, soc/intel/skylake/chip.h
defines struct soc_intel_skylake_config.
The renamed file did not follow this convention and the structure it
defines would conflict with one defined soc/intel/common/chip.h if such
is ever added.
Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We can always PCI config accessors with pci_devfn_t.
Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Note that the code assumes mainboard code to configure
any PCI bridges prior to calling console_init().
Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We need the stub header file. If PCI was implemented, assume
generic MMIO mapped configuration space would work here.
Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I840131f91e79c740c0c8784c252723ae90ded458
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ide9df46b5ff47fea54b9de0e365638a6223c8267
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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BUG=b:141575294
Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Drallion uses UART 0 for console, change the config accordindly.
BUG=b:139095062
Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CONFIG_CBFS_SIZE should only be used as a parameter to generate the
default FMAP.
This also swaps around FMDFILE and CBFS_SIZE to avoid that the
CBFS_SIZE entry disappears when filling in the FMDFILE entry below it.
One advantage is that if code references CONFIG_CBFS_SIZE the jenkins
buildtest will most likely fail as many boards provide an FMD file.
Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Per google/stout.
Tested with SanDisk SSD U110.
Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Based on schematic and register dumps.
Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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