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2020-06-16arch/x86: Declare global_smi_enable()Kyösti Mälkki
The call made at mp_ops.post_mp_init() generally uses four different names. Unify these with followups. smm_southbridge_enable(SMI_EVENTS) smm_southbridge_enable_smi() hudson_enable_smi_generation() enable_smi_generation() Furthermore, some platforms do not enable power button SMI early. It may be preferred to delay the enablement, but fow now provide global_smi_enable_no_pwrbtn() too. Change-Id: I6a28883ff9c563289b0e8199cd2ceb9acd6bacda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16sb/intel: Remove spurious HAVE_SMI_HANDLER testKyösti Mälkki
There are no side-effects in calling acpi_is_wakeup_s3() and apm_control() is a no-op with HAVE_SMI_HANDLER=n. Change-Id: Ia9195781955cc5fa96d0690aa7735fc590e527e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41986 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
Attempts to write to APM_CNT IO port should always be guarded with a test to verify SMI handler has been installed. Immediate followup removes redundant HAVE_SMI_HANDLER tests. Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16sb/intel: Clean up some SMI enablesKyösti Mälkki
Change-Id: I191ad709fd3c6f906cd34b0053eeaebdb80d410d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-15i945 boards: Factor out MAX_CPUSAngel Pons
At least one mobile 945 series northbridge supports 4 threads, because the dual-core Atom 330 CPU supports Hyper-threading. Therefore, we use that as the default for this chipset. Change-Id: I899ed1644d9b2da4fc72f09233a421200770110d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41845 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15gm45 boards: Factor out MAX_CPUSAngel Pons
The gm45 northbridge supports at most 4 threads. However, the only two mobile Core 2 Quad models are not BGA956, so account for that as well. Change-Id: Ie198ac4c366ec0bd53ddb337b6f9c03c331c73f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-15pineview boards: Factor out MAX_CPUSAngel Pons
Pineview has at most 4 threads. Change-Id: I0f45f002d0bab0345bc061ac3c7a29237a536cc5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41843 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15haswell boards: Factor out MAX_CPUSAngel Pons
ULT only has 4 threads, but we are not changing it here to preserve binary reproducibility. Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15x4x boards: Factor out MAX_CPUSAngel Pons
LGA775 CPUs can have at most 4 threads, and Eaglelake supports them. As this socket is also used by other chipsets, temporarily place this symbol into the northbridge scope until all chipsets are factored out. Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-15arrandale boards: Factor out MAX_CPUSAngel Pons
Arrandale CPUs have at most 4 threads. Change-Id: Ifecbf5583011ff5e36c576d582a6276bc9b72803 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41840 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15sandybridge boards: Factor out MAX_CPUSAngel Pons
Also update autoport accordingly. Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15include: update cbmem_possibly_online for vboot_before_bootblockMartin Roth
cbmem is not online when vboot runs before the bootblock. Update the macro to reflect that. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I6fb4ad04f276f2358ab9d4d210fdc7a34a93a5bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15Makefile.inc: Remove all-y with CONFIG_ARCH_xx guardsMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. As a generalization, remove all-y for CONFIG_ARCH_xx guarded makefiles. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia7dcfed699ee1c0cd5a5250431c5f05bf6d8b9c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15vc/amd/fsp/picasso: Add AMD code to support psp_verstageMartin Roth
Add the AMD supplied code (modified to work with GCC) to the vendorcode directory. Verstage will be running on the PSP as a userspace application under the bootloader, which is what bl_uapp signifies. AMD is still working on documentation for the entire PSP userspace application interface. BUG=b:158124527 TEST=Build & boot psp_verstage on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie740c89afe2277eff279fc5c94f88ffd43a78a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15soc/amd/common/block/acpimmio: Update acpimmio for psp_verstageMartin Roth
Because the PSP maps the MMIO addresses that are used to non- deterministic addresses, the accesses need to be able to find the address at runtime. BUG=b:158124527 TEST=Build & boot with Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15console: Update for vboot before bootblockMartin Roth
Exclude pieces of console code from the vboot if running before bootlock. The PSP verstage code will re-implement some of these in its own code. BUG=b:123887623 TEST=Build with following patches Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41815 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15include/rules.h: Add vboot_before_bootblock to ENV_ROMSTAGE_OR_BEFOREMartin Roth
BUG=b:158124527 TEST=Build & boot Trembyle with PSP verstage Change-Id: I3f5cc4d396c678f1020409cbdcb5127b2e0e6d89 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42379 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15security/vboot: Add option to run verstage before bootblockMartin Roth
For AMD's family 17h, verstage can run as a userspace app in the PSP before the X86 is released. The flags for this have been made generic to support any other future systems that might run verstage before the main processor starts. Although an attempt has been made to make things somewhat generic, since this is the first and currently only chip to support verstage before bootblock, there are a number of options which might ultimately be needed which have currently been left out for simplicity. Examples of this are: - PCI is not currently supported - this is currently just a given instead of making a separate Kconfig option for it. - The PSP uses an ARM v7 processor, so that's the only processor that is getting updated for the verstage-before-bootblock option. BUG=b:158124527 TEST=Build with following patches Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I4849777cb7ba9f90fe8428b82c21884d1e662b96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15cpu/intel: Remove obsolete comment in CAR setupKyösti Mälkki
A looong time ago when cache_as_ram.S was built into romstage, the stage was also linked twice. First at a fixed low address and then again relocated at the final execute-in-place address. Change-Id: Ic624feef6794f2c24e38459a45583d84fc07a484 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-15arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki
The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15arch/x86: Remove XIP_ROM_SIZEKyösti Mälkki
When adding XIP stages on x86, the -P parameter was used to pass a page size that covers the entire file to add. The same can now be achieved with --pow2page and we no longer need to define a static Konfig for the purpose. TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and inspect the generated make.log files. The effective pagesize is reduced from 64kB to 16kB for asus/p2b giving more freedom for the stage placement inside CBFS. Pagesize remained at 64kB for lenovo/x60. Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-14soc/amd/picasso/graphics: implement map_oprom_vendev_revMartin Roth
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need different video BIOSes. This checks the vendor & device IDs along with the revision and selects the correct video BIOS to use. Also add the second VGA BIOS for Raven2-based SoCs and change all VGA BIOS IDs to the format including the revision number. Since SeaBIOS still expects the CBFS file name without the revision ID, it won't find the VBIOS any more. As a temporary workaround add the VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*. Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2040455 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14drivers/intel/fsp2_0: Add FSP 2.2 specific supportSubrata Banik
• Based on FSP EAS v2.1 – Backward compatibility is retained. • Add multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Add FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Add FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/volteer: Disable HDA PCI device when AUDIO=NONEDuncan Laurie
If there is no installed audio daughter board on volteer then the HDA driver in the kernel will crash on resume. In order to prevent this disable the PCI device when AUDIO=NONE probe match is true. BUG=b:147462631 TEST=boot on volteer and ensure that the PCI device at 0:1f.3 is gone Change-Id: I4a436e1b76418030bf635427e490b54a713fdd33 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/zork: Drop OEM_BIN configsFurquan Shaikh
Zork family does not use OEM binary and so this change drops the configs required for adding this binary. Change-Id: Id38c67030e4055ab16934d1a900ee1cea5843b54 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14mb/google/zork: Enable ELOG optionsFurquan Shaikh
This change enables following ELOG options for zork family: ELOG ELOG_BOOT_COUNT ELOG_GSMI ELOG_BOOT_COUNT_CMOS_OFFSET BUG=b:158875638 TEST=Verified that kernel reports GSMI loading correctly: [ 5.308982] gsmi version 1.0 loaded Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4f34a814e744e863f1fbfc19e37209cb7febbdcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14southbridge/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Modify southbridge/intel/common .asl files to comply with ASL2.0 syntax for better code readability and clarity BUG=none BRANCH=none TEST= Google Parrot platform coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ia11769d5ac6154ed79d967d7bab36e12a1db751a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42084 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso/aoac: Add wait_for_aoac_enabledRaul E Rangel
This way drivers can wait for their devices to be enabled. I also rewrote enable_aoac_devices to take advantage of wait_for_aoac_enabled. BUG=b:153001807 TEST=Trembyle builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8e653c857e164f90439e0028e08aa9608d4eca94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14soc/amd/picasso/aoac: Set the Target Device State when powering onRaul E Rangel
If the OS sets the target device state to D3, we need to clear it so we can reestablish register access. BUG=b:153001807 TEST=Boot trembyle with I2C powered off and see it power back on. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14soc/amd/picasso: Move aoac functions to new fileRaul E Rangel
This functionality is needed in the PSP and I can't include all of southbridge.c. BUG=b:153001807 TEST=Made sure trembyle still compiles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3a38c655588d7836e1bd033e958a505774de871e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso: Explicitly disable legacy UARTRaul E Rangel
The legacy UARTs are supposed to default to off according to the documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0 is enabled after reset. The PSP might be enabling it or the documentation might be wrong. Having it enabled causes problems though. We have ACPI nodes defining MMIO UARTs, and the kernel also probes for legacy UARTs. This results in two drivers accessing the same device, one via MMIO and one via IO. I suspect this was the cause of the garbage serial output. Before the change you would see the following in the console: [ 0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A After this change, we no longer see it. BUG=b:152079780, b:157858890 TEST=Boot trembyle and make sure serial is still working. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-14console, PCI: Remove EARLY_PCI_BRIDGE support in verstageKyösti Mälkki
The purpose of pci_early_bridge_init() is to temporarily configure PCIe rootport (or PCI bridge) on bus 0 to configure PCI device BARs on the secondary bus. Currently used and tested only with UART_OXPCIE. Since those BARs do not reset on stage changes, it is not necessary to redo those steps for verstage or postcar. Note that the option does not really work with many of the later platforms where PCIe pins/links/lanes are configured late in FSP-M or similar blob. Change-Id: I148f44c76c61edcfd8ab1c8c531cd2e6ca343130 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/volteer/var/terrador: Update dq/dqs mappingsDavid Wu
Update dq/dqs mappings based on terrador schematics. BUG=b:156435028,b:151978872 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGSJonathan Zhang
FSP_NV_STORAGE HOB is supported in CPX-SP FSP ww22 release. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ida06fa7f7c7937f4e66a83fdecbca8bc208d626f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42024 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso: correct MCFG ACPI tableAaron Durbin
The start and end bus number in the MCFG ACPI table is inclusive. Therefore, the number of buses decoded needs to be subtracted by 1. BUG=b:158874061 Change-Id: Ic773bc1e0ccaa99af45d1a53919f6480887fa37e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42329 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/volteer: Enable thermal sensor 4 in DPTF for volteerDeepika Punyamurtula
Enables the fourth thermal sensor for fan in DPTF for volteer BRANCH=None BUG=b:149722146 TEST= On volteer system check `cat /sys/class/thermal/thermal_zone5/type` for TSR3 Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-14dptf: Introduce new paradigm for configuring DPTF parametersTim Wawrzynczak
Currently, configuring and reviewing DPTF parameters is difficult because DPTF tables and methods are defined in static ASL files, and are littered with #ifdefs which both define parameters and influence behavior (e.g., whether a method is included or not). This patch train is an effort to bring DPTF support to our ACPI DSDT/SSDT generation framework. This first patch is very minimal, and includes only creation of the DPTF device (in the DSDT). BUG=b:143539650 TEST=compiles (later tests get more comprehensive). Change-Id: I14df9f422c911677aeea25552ac1822a9462c58a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41883 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/intel/tigerlake: enable CPU_INTEL_COMMONAlex Levin
Since we plan to use VMX, enable CPU_INTEL_COMMON. BUG=b:157388365 TEST=tested on Volteer Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: I5e7bdb4310947dd8a94ee554834a67ce94377ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-14soc/amd/picasso: Increase SMM_RESERVED_SIZEMarshall Dawson
Correct a message of "Error: Can't add stage_cache 57a9e101 to imd". ramstage is 0xffc90 and adding FSP-S (0x50000) failed. Increase the reserved region of SMRAM to accommodate both images. BUG=b:158704095 TEST=Boot Mandolin and check console log Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51595d80d4779e995ec2a26e395cf95d666a309e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42314 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/puff: add MST and LSPCON details to devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices. BRANCH=None BUG=b:156546414 TEST=Manual tested and able to see update on sysfs and ssdt table Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-14soc/intel/cannonlake/acpi: Capitalize hex number to unify with SkylakePaul Menzel
diff -ur src/soc/intel/skylake/acpi/pch_hda.asl src/soc/intel/cannonlake/acpi/pch_hda.asl --- src/soc/intel/skylake/acpi/pch_hda.asl 2020-05-12 11:17:42.780293920 +0200 +++ src/soc/intel/cannonlake/acpi/pch_hda.asl 2020-05-12 11:17:42.756294169 +0200 @@ -4,7 +4,7 @@ Device (HDAS) { - Name (_ADR, 0x001F0003) + Name (_ADR, 0x001f0003) Name (_DDN, "Audio Controller") Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) Change-Id: Ic8b874163ddede72a75e0dc94021683bca3e7859 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-14soc/intel/xeon_sp/cpx: configure FSP-M UPD parametersJonathan Zhang
Configure FSP-M UPD parameters. TESTED=Boot CPX-SP based server. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: add cpu entries in ssdtJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I4d057a7c385ca563bfcc7ad44f651ad1f8ca003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: fix MADT ACPI tableJonathan Zhang
Fix MADT table generation to keep IIO stack design in consideration. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: add IIO stack resources to DSDTJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Iec89551a8b88a683db5857e3a6ab4af5e446cb5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: add NUMA ACPI tablesJonathan Zhang
Add NUMA ACPI tables: SRAT, SLIT. TESTED=Boot CPX-SP based server, check /sys/firmware/acpi/tables for SRAT/SLIT tables. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I3374b802afd2d001e841afd85e7ae07bc27c01ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/41902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Tim Chen
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14mb/google/fizz: add variant chipset display initJeff Chase
The Endeavour variant does not have a DisplayPort input so there's no need to wait for it. BUG=b:147830399 BRANCH=none TEST=boot endeavour; check coreboot logs Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: I30c7c47f19a61ce66c6c923864d80870d2761859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-06-14mb/google/dedede: Enable early EC software syncMeera Ravindranath
BUG=none BRANCH=none TEST=Verify sysjump from EC console, EC sync in romstage in AP console and crossystem reflect ecfw_act as RW Change-Id: Ief96fe481c94acef3754881cf1f453699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/dedede: Select Recovery Cache Kconfig optionMeera Ravindranath
BUG=none BRANCH=none TEST=Boot WaddleDoo in recovery and populate the recovery MRC cache. The subsequent recovery boot should boot out of the stored recovery MRC cache and skip memory training. Change-Id: Ief86fe481c94abef3754881cf1f454699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41162 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14sb/intel/i82801ix: Fix SPDX license headerKyösti Mälkki
Change-Id: I4c8ef49f86f6d5344741ab92035e108cccfe30b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14mb/google/hatch: Switch USB2 port1 and port3 on NoibatEdward O'Callaghan
Switch USB2 port1 and port3 for noibat due to circuit change. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I711038624f3efe397be73c29a940b3e17802598f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1Furquan Shaikh
ALIB function 1 needs to be called every time there is a change in AC/DC state of the system. This change adds a wrapper method that can be called by PNOT (method to notify system power state change) to report to ALIB that system power state has changed i.e. AC <-> DC. Additionally, this change drops the call to ALIB from _INI method since the PWRS object might not be initialized correctly at that point. Instead EC makes a call to PNOT when PWRS is initialized. This wrapper also fixes the value of power state being passed into ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports 1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state before passing into ALIB. BUG=b:157752693 TEST=Verified that WAL1() gets called on AC connect/disconnect. Steps followed: $ echo 1 > /sys/module/acpi/parameters/aml_debug_output $ dmesg -w | grep ACPI [ 76.306947] ACPI Debug: "EC: AC DISCONNECTED" [ 76.307064] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01" [ 82.264946] ACPI Debug: "EC: GOT PD EVENT" [ 82.539833] ACPI Debug: "EC: GOT PD EVENT" [ 82.753721] ACPI Debug: "EC: GOT PD EVENT" [ 82.843676] ACPI Debug: "EC: GOT PD EVENT" [ 82.970596] ACPI Debug: "EC: AC CONNECTED" [ 82.970659] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00" [ 83.047598] ACPI Debug: "EC: GOT PD EVENT" [ 84.804733] ACPI Debug: "EC: GOT PD EVENT" [ 86.317934] ACPI Debug: "EC: GOT PD EVENT" [ 86.385920] ACPI Debug: "EC: GOT PD EVENT" [ 86.515830] ACPI Debug: "EC: AC DISCONNECTED" [ 86.515922] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01" [ 90.089062] ACPI Debug: "EC: GOT PD EVENT" [ 90.357914] ACPI Debug: "EC: GOT PD EVENT" [ 90.573812] ACPI Debug: "EC: GOT PD EVENT" [ 90.662744] ACPI Debug: "EC: GOT PD EVENT" [ 90.788706] ACPI Debug: "EC: AC CONNECTED" [ 90.788835] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00" [ 90.865675] ACPI Debug: "EC: GOT PD EVENT" [ 92.621793] ACPI Debug: "EC: GOT PD EVENT" Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14ec/google/chromeec: Call \PNOT () on initializing AC power stateFurquan Shaikh
This change calls \PNOT () method when AC power state is initialized to allow platform code to take appropriate action. BUG=b:157752693 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13cpu/intel/car: Use symbols for CAR MTRR setupKyösti Mälkki
Change-Id: I32d7337ccf8005c7fb65d2efea40c122093d4dd9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-13arch/x86: Add symbols for CAR MTRRs in linker scriptKyösti Mälkki
This allows to remove references to CONFIG_DCACHE_RAM entries in most cache_as_ram.S files. While Kconfig variable names appear for every stage, linker symbol names will only appear in stages they are valid in. Also, linker scripts have LOG2CEIL which comes in handy to enforce MTRR alignments. Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30872 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13soc/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Modify soc/intel/common .asl files to comply with ASL2.0 syntax for better code readability and clarity BUG=none BRANCH=none TEST= Deltan coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: I8f95cf88f499d9f9bdd8c80c95af52f8fd886cdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-13arch/x86: Include id.ld unconditionally in memlayout.ldFurquan Shaikh
Now that Picasso uses its own memlayout.ld, always include id.ld in arch/x86/memlayout.ld. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I04b59c2a273cad0a2e64dbc325c0b09fca254558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42266 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13arch/x86: Drop early_ram.ldFurquan Shaikh
Now that Picasso uses its own linker script, early_ram.ld from arch/x86 is unused and hence is dropped as part of this change. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ida83d40d005ddab789628a1581389fc487b10d4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13soc/amd/picasso: Place early stages and data buffers at the bottom of DRAMFurquan Shaikh
This change updates memlayout.ld for Picasso to place all early stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at the bottom of DRAM starting at 32MiB. This uses static allocation for most components by defining Kconfig variables for base and size. It relies on the linker to complain if any of the assumptions are broken. This also allows romstage to use linker symbols for _early_reserved_dram and _eearly_reserved_dram to store information in CBMEM about the early DRAM usage by coreboot before ramstage starts execution. This allows ramstage to reserve this memory region in BIOS tables so that S3 resume can reuse the same space without corrupting OS memory. BUG=b:155322763 TEST=Verified memory reported by coreboot: Writing coreboot table at 0xcc656000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000001ffffff: RAM 4. 0000000002000000-000000000223ffff: RESERVED 5. 0000000002240000-00000000cc512fff: RAM 6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES 7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE 8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES 9. 00000000cd800000-00000000cfffffff: RESERVED 10. 00000000f8000000-00000000fbffffff: RESERVED 11. 0000000100000000-000000042f33ffff: RAM 12. 000000042f340000-000000042fffffff: RESERVED Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13cbmem_id: Add CBMEM ID for early DRAM usageFurquan Shaikh
This change adds a new CBMEM ID (CBMEM_ID_CB_EARLY_DRAM) that can be used by platform code to stash details of early DRAM used by coreboot. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I913c744fdce2f9c36afdc127b2668fccf57dde58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13soc/amd/picasso: Add custom memlayout.ld fileFurquan Shaikh
This change copies src/arch/x86/memlayout.ld file to src/soc/amd/picasso/ and sets MEMLAYOUT_LD_FILE config variable to point to this newly added file. Unused elements from the memlayout.ld file are dropped and path to early_dram.ld is updated to include the one from src/arch/x86. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I59bf5f93b712407ddcc9fb8a46167936c6c28a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13mb/google/zork: update DRAM SPD table for vilbozPaul Ma
Add DRAM support for vilboz: Hynix H5AN8G6NCJR-VKC # 0b0000 Hynix H5ANAG6NCMR-VKC # 0b0001 Samsung K4A8G165WC-BCWE # 0b0010 Hynix H5AN8G6NDJR-XNC # 0b0011 Micron MT40A512M16TB-062E-J # 0b0100 Samsung K4AAG165WA-BCWE # 0b0101 Micron MT40A1G16KD-062E-E # 0b0110 BUG=b:157523051 BRANCH=none TEST=build Change-Id: I251fd9cc7bc51bfdeaa577f7034da750e684dc99 Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-12mb/google/volteer/var/voxel: Add memory parts and generate DRAM IDsFurquan Shaikh
This change adds memory parts used by variant voxel to mem_list_variant.txt and generates DRAM IDs allocated to these parts. This variant is not yet supported by coreboot but DRAM IDs need to be generated for it. In the coming days, variant voxel will be added to coreboot. BUG=b:157732528 Change-Id: I8780beec987deb8fed11bb8f84275dcba4768514 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-12vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSP-M: SkipCpuReplacementCheck PCH HSIO Tuning UPDs FSP-S: PcieRpHotPlug TccActivationOffset TccOffsetClamp TccOffsetLock TccOffsetTimeWindowForRatl USB3 HSIO Tuning UPDs BUG=none BRANCH=none TEST=build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib40d226dd2ecc4fb34965e1f2c416c53edef01d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/volteer: Customize PCH VR settings for better Sx power savingsVenkata Krishna Nimmagadda
For Volteer mainboard, this patch set optimized values for PCH external VR settings and ext rail voltage/current, to achieve better power savings in sleep states. v1p05 and vnn power rails can be used as an alternative source by-passing vccin_aux during Sx. This by-pass feature, enables us to shutdown vccin_aux rail which is higher voltage rail compared to v1p05 and vnn. These both rails were disabled by default in FSP. Changes in this patch are: 1. v1p05 and vnn rails are enabled and enabled supported voltage types in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default. 2. Icc Max for v1p05 changed to 500 mA from default 100 mA. 3. vnn rail's voltage is changed to 5 V from default 4.2 V. BUG=None BRANCH=None TEST="Build and boot volteer and check VR settings with Intel ITP-XDP debugger and verify approx 250 mW power savings in Sx" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42223 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda
For Tiger Lake platforms, this patch set provides a way to override PCH external VR settings and ext rail voltage/current through devicetree. This enables setting of optimal settings for FIVRs for a particular PCH type. BUG=None BRANCH=None TEST=Build and boot volteer. Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ic55472d392f27d153656afbe8692be7e243bb374 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41424 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/dedede: Add new variant botenPeichao Wang
Add initial support for boten variant board. BUG=b:158023819 BRANCH=None TEST=build Change-Id: I56fe901c6aec781fac217ab08f7583cc25788688 Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-12nb/intel/i945/rcven.c: Correct commentAngel Pons
The offset between registers has to be between different channels. Change-Id: Ic6d959c31c78073a3ecbf7a17dfb73ac36340599 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-12nb/intel/i945: Clean up raminit coding styleAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I17739a9663d809647c22c415a0998edb61c04484 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-12mb/google/hatch: Remove unused USB2 port from NoibatEdward O'Callaghan
This port isn't packed on the board, so remove from the devicetree. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12soc/amd/picasso: Reconfigure SPI speeds after FSP-S has runFurquan Shaikh
This change reconfigures SPI speeds after FSP-S has run since FSP-S is currently configuring the SPI frequency when it should not. Until FSP-S behavior is fixed, this workaround needs to be applied. BUG=b:153506142 TEST=Verified that em100 works fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id9b8330c6f82c7162ff91e8cc10160fdd8cfedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/42267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-12sb/intel/i82801ix: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Ie05f484cf4b346601e6128c95ff2b27ce59b995f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42188 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/puff: Update i2c[2] and i2c[3] rise and fall timesSam McNally
BRANCH=none BUG=b:158713330 TEST=Flashing the LSPCON firmware works Change-Id: Ib371f6954115145047c70cfd25262026cce087fd Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-12sb/intel/i82801jx: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11soc/amd/picasso/uart: fix possible out of bounds accessFelix Held
Found-by: Coverity CID 1429769, 1429777 Change-Id: Ide188379a34c769c929bf7832fd94a7004c09a64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structsFelix Held
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11mb/google/dedede: Add new variant drawciaWisley Chen
Add initial support for drawcia BUG=b:158540280 BRANCH=None TEST=build Change-Id: Ic775bb2a93581e422379ca90127e3581bbf3c89e Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-11mb/google/volteer: Update DPTF TSR2 sensor ID for volteerDeepika Punyamurtula
Update DPTF_TSR2_SENSOR_ID to 2. Fixes the issue where TSR1 and TSR2 have the same DPTF_TSR#_SENSOR_ID value causing them to report the same temperature under /sys/class/thermal and also swap TSR0 and TSR1 in DTRT to match physical sensor in volteer schematics BRANCH=None BUG=b:149722146 TEST=On volteer system check TSR1 and TSR2 temperatures, should report different values `cat /sys/class/thermal/thermal_zone[3,4]/temp` Also verify other TSRs using `cat /sys/class/thermal/thermal_zone*/temp` and `ectool tempsinfo all ; ectool temps all` Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Idc5f35e4faf59b0ee726eb32a08eab4654fb342d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42232 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10amd/picasso: Load x86 microcode from CBFS modulesZheng Bao
Combine the Ucode binaries for 3 revisions of CPU into one CBFS module. This should be moved to the AMD common code later. BUG=b:153580119 TEST=mandolin Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-10device/xhci: Add xHCI utility to enumerate capabilitiesRaul E Rangel
This will allow enumerating an xHCI controller to allow dynamically generating the ACPI device nodes. BUG=b:154756391 TEST=Boot trembyle and see capabilities printed on console xHCI Supported Protocol: Major: 0x2, Minor: 0x0, Protocol: 'USB ' Port Offset: 1, Port Count: 2 xHCI Supported Protocol: Major: 0x3, Minor: 0x10, Protocol: 'USB ' Port Offset: 3, Port Count: 1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3065c3fffad01b5378a55cfe904f971079b13d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-10mb/google/hatch: drop VBOOT_LID_SWITCH from hatch baseboardMatt DeVillier
Selecting VBOOT_LID_SWITCH under BOARD_GOOGLE_BASEBOARD_HATCH creates a requirement for VBOOT, and prevents building in the non-vboot/non-ChromeOS case. As this symbol is already selected by CHROMEOS below, there's no need for the baseboard (and only one of the two) to select it, so don't. Change-Id: I060e82185997bce451648173dd97dd6a3d5d237f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-10soc/intel/common: Replace cse_bp and ME with cse_lite in all console logsSridhar Siricilla
Replace 'cse_bp'(cse boot partition) and 'ME' with 'cse_lite' in all log messages in the cse_lite.c. TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3fc677c9ec1962199c91cc310d7695dded4e0ba0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41972 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb/google/dedede/variants/waddledoo: Adjust I2Cs CLK to meet specJohn Su
After adjustment on waddledoo Touch Pad CLK: 392.9 KHz Touch Screen CLK: 387.4 KHz Audio CLK: 350.9 KHz BUG=b:151302522 BRANCH=master TEST=emerge-dedede coreboot chromeos-bootimage measure by scope with waddledoo. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iec02a751f1effdbefbb2969db2fd57f27ecdd033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42187 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10nb/intel/i945: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I181f69372829cf712fd72887b5f2c7134bfcf15a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42190 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10sb/intel/bd82x6x: Use PCI bitwise opsAngel Pons
Some cases could not be factored out while keeping reproducibility. Also mark some potential bugs with a FIXME comment, since fixing them while also keeping the binary unchanged is pretty much impossible. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-10sb/intel/bd82x6x/pcie.c: Move `pch_pcie_acpi_name` upAngel Pons
The ASSERT() macro depends on the line number, so changing the line it appears in breaks reproducibility testing using BUILD_TIMELESS=1. Work around this problem by placing the `pch_pcie_acpi_name` function, which contains this macro, at the beginning of the file. This allows refactoring the rest of the code without affecting the ASSERT() macro. Change-Id: I2e0432ec9ae6c7d033fc7495afb3a71fe7e77729 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-10soc/amd/picasso: Enable APOB/MRC training data cacheFurquan Shaikh
Picasso doesn't really make use of the common mrc_cache driver because of the PSP/ABL requirements for APOB NV data. The APOB NV data gets consumed by PSP/ABLs before x86 comes out of reset. Hence, we cannot really add any metadata to this saved data or use multiple slots as done by the default MRC cache driver (CACHE_MRC_SETTINGS). Additionally, FSP-M requires access to this APOB NV data which coreboot needs to pass in from different locations depending upon boot mode: 1. Non-S3 boot: PSP/ABLs store APOB NV data in DRAM at predetermined location which is present in BIOS directory table. 2. S3 boot: PSP/ABLs do not store APOB NV data in DRAM. Thus, coreboot needs to set FSP-M UPD NvsBufferPtr as the DRAM location in non-S3 boot and the address of RW_MRC_CACHE on SPI flash in case of S3 resume. This change enables MRC cache support in Picasso in order to meet the above requirements. 1. NvsBufferPtr is set based on boot mode. 2. APOB NV data is not stashed to CBMEM. Instead it is written right away to SPI flash in romstage. BUG=b:155990176 Change-Id: I8661a4cf2d34502967e936bf22a13f6f1b88e544 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-10drivers/intel/fsp2_0: Allow SoC/mainboard to update NvsBufferPtrFurquan Shaikh
This change moves the check for NvsBufferPtr in S3 resume case to happen just before FSP-M is called. This allows SoC/mainboard code to set NvsBufferPtr if it doesn't use the default MRC cache driver. BUG=b:155990176 Change-Id: Ia272573ad7117a0cb851f0bfe6a4c7989bc64cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-10mb/google/zork: Set FMDFILE for zork familyFurquan Shaikh
This change sets FMDFILE for zork family so that coreboot builds pick up the right flash layout. BUG=b:155990176 Change-Id: Ia1673622ccd14a2ff7bde555ed33d5b51cf4272a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42106 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10soc/intel/cannonlake: Put braces around *else* branchPaul Menzel
From `Documentation/coding_style.md`: > This does not apply if only one branch of a conditional statement is a > single statement; in the latter case use braces in both branches: Change-Id: I5672949e587a9c0e4efa01521a659e4c224085d0 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10soc/intel/skylake: Remove space after type castPaul Menzel
Unify the file with the Cannon Lake version `src/soc/intel/cannonlake/smmrelocate.c`. Now they are identical. Change-Id: I8cae66038edb3966604c92597986839badd617c5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10soc/intel/skylake: Use unit macros KiB and MiBPaul Menzel
Unify the file with the Cannon Lake version `src/soc/intel/cannonlake/smmrelocate.c`. Change-Id: Id4815836e93081b61f4c09b8b3ed81199d3ff409 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-10arch/x86: Remove some x86_32 vs x86_64 noiseKyösti Mälkki
Change-Id: Ib98483e5d6fcd66fdc72f6157a5bf185fef13016 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-10binaryPI: Replace CONFIG(ARCH_xx) testKyösti Mälkki
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. Not strictly required for binaryPI boards, but do this for consistency. Change-Id: Id0bbbfb6f695c4bb920bc57a1e9362a23884efb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-10lib/program.ld: Replace CONFIG(ARCH_xx) testsKyösti Mälkki
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. For x86 we define .id linking explicitly elsewhere. Change-Id: I43f849465e985068cd0b8a1944213b7c26245b8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-10mb/google/dedede: Enable S0ix supportAamir Bohra
Change-Id: I4cadfe69e36f959b54e374800c32629a7481ea94 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-10mb/google/dedede: Add mainboard acpi support for GPIO PM configurationAamir Bohra
Setting the default values for GPIO community power management, causes issues in detecting TPM interrupts. So to avoid that GPIO PM has to be disabled in devicetree. But for S0ix it is needed. This patch implements a workaround in ASL code to enable GPIO PM on S0ix entry and disable it on S0ix exit. This patch adds the following three platform specific methods. 1. MS0X to enable power management features for GPIO communities on low power mode entry and disables it on exit. 2. MPTS to enable power management features for GPIO communities when preparing to sleep. 3. MWAK to disable power management features for GPIO communities on waking up. BUG=b:153847814 TEST=Verify S0ix is working. GPIO PM configuration is upadated on low power mode entry and exit. Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10soc/intel/tigerlake: Add Hot-Plug and PME event handlers for ThunderboltJohn Zhao
This change adds Hot-Plug and power management event handers(_L61 & _L69) respectively for Thunderbolt in the GPE scope. The _L61 method invokes sub-method HPEV to support Hot-Plug wake event from Thunderbolt PCIe root ports. This method intercepts Presence Detect Changed interrupt and make sure the L0s is disabled on empty slots. The _L69 method checks and clears root port's PME SCI status. BUG=b:156435065 TEST=Verified multiple hot plug successfully with Lenovo dock. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 03:48:00 +0000