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2018-10-14soc/amd/stoneyridge: Remove hudson EHCI debug controllersMarshall Dawson
Remove nonpreset controllers from the PCI device identifier function (ignoring any CONFIG_USBDEBUG_HCD_INDEX). The extra devices appear to be holdovers from the original sb/hudson source. TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and verify proper BDF is returned in romstage and ramstage. Change-Id: I2e819d5e998922ad427c4a094c29a590f249a0d3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-14soc/amd/stoneyridge: Remove errant parenthesis in southbridge.hMarshall Dawson
Delete an unmatched opening parenthesis in the definition for the EHCI hub config register definition. This wasn't causing a problem unless EHCI debug was enabled. TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and verify successful build Change-Id: I5f461d1573e416b5a8ee24329142e3c46b6a05e3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29073 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-14soc/amd/stoneyridge: Rearrange southbridge.h moreMarshall Dawson
Move the SPI base address register definition to D14F3. This was missed in: bba043 amd/stoneyridge: Rearrange southbridge.h Change-Id: Ia722339418c118bdf4b000bbf97ae4266e9b3be2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-12drivers/intel/fsp2_0: Hook up IntelFSP repoPatrick Georgi
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-12libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2Julius Werner
This patch adds the new, faster architectural register accessors to libpayload that were already added to coreboot in CB:27881. It also hardcodes the assumption that coreboot payloads run at EL2, which has already been hardcoded in coreboot with CB:27880 (see rationale there). This means we can drop all the read_current/write_current stuff which added a lot of unnecessary helpers to check the current exception level. This patch breaks payloads that used read_current/write_current accessors, but it seems unlikely that many payloads deal with this stuff anyway, and it should be a trivial fix (just replace them with the respective _el2 versions). Also add accessors for a couple of more registers that are required to enable debug mode while I'm here. Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2018-10-12amd/stoneyridge: Fix PmControl register size in SMI handlerMarshall Dawson
The AMD implementation of this register is only 16 bits. Change the source accordingly. TEST=Suspend/Resume a Grunt several times Change-Id: Ib900468cc1c790fa7d57bb6faa91aee012173f7a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Rename CGPLL_CONFIG definitionsMarshall Dawson
Shorten the names in the MISC CGPLL_CONFIG, and make the formatting match the surrounding source. Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Rename GppClkCntrl fieldsMarshall Dawson
Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file. Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Rearrange southbridge.hMarshall Dawson
Group definitions so they're near others of the same type, e.g. PCI, AcpiMmio, etc. Change-Id: Ia6ef21431db0e758eba0ea043b54c036ec6235fe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Remove dead GPIO definitionsMarshall Dawson
Delete definitions that are no longer used. Change-Id: I94c9c33f73c1a2d9308408e3e9ca526e876d6135 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Clarify XHCI_PM register definitionsMarshall Dawson
Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Fix SPI_CMD_TRIGGER coding styleMarshall Dawson
Make the whitespace match surrounding lines and remove unnecessary parentheses. Change-Id: I2ed02494ba69237c38af61317e435d9575cefe1c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Convert hex definitions to lower caseMarshall Dawson
Match the rest of the soc/stoneyridge source. Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Remove hudson register definitionsMarshall Dawson
Delete artifacts remaining from the original "hudson" and "yangtze" controller hub designs. Husdon devices had a configurable AcpiMmio base address, and a selection for I/O vs. MMIO decode. Modern products are fixed at 0xfed80000 in MMIO. Remove the flash control register definitions for the old generations. The manual reset register appears to not function as hudson. PMIO_DEBUG is named differently now, and not used, so remove its definition too. Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-11mb/google/poppy/var/nocturne: Provide override for ec eventinfoFurquan Shaikh
This change implements the callback to provide google_chromeec_event_info structure in nocturne variant and sets MKBP SCI based on board id. BUG=b:112366846,b:112112483,b:112111610 Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11mb/google/poppy: Allow variants to provide event info at runtimeFurquan Shaikh
This change adds a variant callback to read google_chromeec_event_info from variant at runtime to allow override of any events based on factors like board id. This callback is used in ramstage and smm to get google_chromeec_event_info structure for performing various actions like setting masks and logging wake events from EC. BUG=b:112366846,b:112112483,b:112111610 Change-Id: If89e904c92372530a0f555952f87702f068e0b03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11ec/google/chromeec: Add support for querying ec board id in smm stageFurquan Shaikh
This change adds ec_boardid.c to smm stage, which is required to allow mainboards to query the ec to get board version in this stage. BUG=b:112366846,b:112112483,b:112111610 Change-Id: Iccbba96ebb94a12745a62cbfe3496f9e6f921e3d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-10-11ec/google/chromeec: Get rid of __SMM__ guard for chromeec functionsFurquan Shaikh
There doesn't seem to be a reason why we would want to protect certain chromeec functions with __SMM__ guard. So, this change gets rid of it. If the functions remain unused, then they would be removed during linking. Change-Id: I8196406074b01fe8ea15173c55d45bb86384be1b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29006 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11src: Replace MSR addresses with macrosElyes HAOUAS
Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-11amd/stoneyridge: Indicate STAPM units in their nameRichard Spiegel
STAPM devicetree registers do not indicate the unit, which causes confusion. More importantly, the time was assumed to be in seconds when it's actually milliseconds. This caused early STAPM configurations to fail. BUG=b:117590953 TEST=Build grunt Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11mainboard/google/kahlee: Set PSPP setting to BalanceLowAkshu Agrawal
With correct stapm values audio issue is not observed with PsPPBalanceLow (Gen1 speed). BUG=b:117569918 TEST=audio playback multiple times Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/29028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11mb/google/kahlee: Set stapm parameters with time value fixedAkshu Agrawal
stapm_time passed to smu via agesa is in msec. With earlier value smu was getting stapm_time as 2.5 sec instead of 2500 sec and thus causing issue in S3, and audio in PsppBalanceLow state. BUG=b:117569918, b:117252463 TEST= 1.) audio works with PsppBalanceLow 2.) S3 cycles Change-Id: I673e7e673d042918dff47141f37bbca354f5c45c Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/29027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11tegra124_lp0: make sure to build with compiler.h includedPatrick Georgi
Fixes builds of that binary in clean trees. Change-Id: If5a995449a74c00da836fcf22bda44ebc8197518 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-11commonlib/storage: Make pci sdhci code compile in romstageBora Guvendik
In romstage malloc is not available, so use CAR_GLOBAL variable instead. BUG=b:78106689 TEST=Boot to OS Change-Id: If9438d0b707c6ffaa61db80bd1d385112bc91cfc Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/25067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11riscv: add physical memory protection (PMP) supportXiang Wang
These codes are written by me based on the privileged instruction set. I tested it by qemu/riscv-probe. Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28569 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11soc/intel/common/block/gpio: check for NULL using if statementBora Guvendik
Remove assert() and instead use if statement to check if comm->groups is NULL. Found-by: klockwork BUG=None TEST=Boot to OS Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11mb/google/octopus: I2C clock tuning for meepWisley Chen
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:117298114 TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11mb/cavium/cn8100_sff_evb: Only expose two UARTsPatrick Rudolph
Only two UARTs are connected to the FTDI UART USB chip. Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-10soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabledFurquan Shaikh
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform. Function to set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as well as S3 resume path (BS_OS_RESUME). BUG=b:117284700 TEST=Verified that no spurious wakes are observed on nocturne. Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-10mb/google/octopus: Drop I2C bus 0 clock frequency for Phaserpeichao.wang
Need to tune I2C bus 0 clock frequency under the 400KHz since this bus attached the Stylus EMR pen and need meet the spec. Bug=b:117297214 TEST=flash coreboot to the DUT and measure I2C bus 0 clock frequency whether under 400KHz Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28973 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10lib: increase part number size in memory_info/dimm_infoAaron Durbin
The dimm_info and memory_info structs are used in devices that don't strictly use DIMMs. Those platforms have the DRAM soldered down so there's no DIMM part number that encapsulates the DRAMs used in the DIMM. The full part number is desired to be exposed in the SMBIOS tables. As such extend DIMM_INFO_PART_NUMBER_SIZE to 33 to accommodate longer part numbers 'MT53B256M32D1NP-053 WT:C' is one of the longer part numbers that are desired to be maintained. BUG=b:115697578 Change-Id: I0c39dd1d1c2f0776d70d8c4d8d56719779ff82ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-10soc/cavium: dynamic UART initialization for cavium cn8100Jens Drenhaus
Now only those UARTs that are enabled in devicetree.cb are initialized. Tested on Opencellular Elgon. Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Signed-off-by: Jens Drenhaus <jens.drenhaus@9elements.com> Reviewed-on: https://review.coreboot.org/28975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-10mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPDChris Zhou
Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9) BUG=b:112679174 TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28974 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10mb/google/kahlee/variants/*/devicetree.cb: Reset I2C slavesRichard Spiegel
Use the new I2C slave reset function and reset all slaves connected to all 4 I2C. Do this in all boards. BUG=b:114479395 TEST=Added debug code. Build and boot grunt. Examined output, confirmed GPIO pins changing as required. Removed debug code. Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28575 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10soc/amd/stoneyridge/gpio.c: Create I2C slave reset codeRichard Spiegel
AMD's SOC do not wait for I2C transactions to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement SCL bang, using a devicetree register to define which I2C SCL lines needs to be reset. BUG=b:114479395 TEST=Build and boot grunt. Look at transactions on a scope. Change-Id: I7f74b7e45c509044825355874753969f074e2382 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28574 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10mb/google/kahlee: Add delan variantMartin Roth
BUG=b:117173908 TEST=Build delan Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-10mb/google/fizz: Prepare sharing directory for variantsDavid Wu
Clean up Kconfig file in order to support variants for fizz. Add BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants to use the common baseboard configs. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-10mediatek/mt8183: Init PLLs for DRAMTristan Shieh
Set up DRAM related PLLs. And update post divider table to fulfill all freqency settings. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/28667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-10-09soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik
This patch creates _PRT entires for each PCIE root port devices. TEST=Able to see PCIE wake device in cat /proc/acpi/wake list Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/acpi: Fix ACPI Namespace lookup failure, AE_ALREADY_EXISTS ↵Subrata Banik
issue This patch fixes below ACPI compilation issue: Found 1 external control methods, reparsing with new information Pass 1 parse of [DSDT] ACPI Error: [EPCS] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) ACPI Error: [EMNA] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) ACPI Error: [ELNG] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) Pass 2 parse of [DSDT] ACPI Warning: NsLookup: Type mismatch on EPCS (Integer), searching for (RegionField) (20160318/nsaccess-664) ACPI Warning: NsLookup: Type mismatch on EMNA (Integer), searching for (RegionField) (20160318/nsaccess-664) ACPI Warning: NsLookup: Type mismatch on ELNG (Integer), searching for (RegionField) (20160318/nsaccess-664) Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions) TEST=Able to build sgx.asl without any ASL error. Change-Id: If4e7d4c66b6aab6c081fa272d8c2c9a1f0651ef7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/block/pcr: Add NULL pointer check in pcr_execute_sideband_msg()Subrata Banik
This patch to fix KW issue due to msg, data and response pointers NULL check fail. Change-Id: I39324514079f240ba1683a04e579de85485299bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Disable Legacy PME for Root portsSubrata Banik
Legacy PME are enabled by default in FSP-S UPD. This policy sets PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt generation when RSTS.PS state has changed (either due to 0->1 transition or due to this bit being set with RSTS.PS already set). Due to this interrupt generation, system wakes from sleep immediately it enters. This patch overrides root port legacy pme upd policy from coreboot to ensure no false SCI is triggerd when system is in S3/S0ix state. BUG=b:113083354 BRANCH=none TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase without any failure. Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registersSubrata Banik
This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-09soc/intel/skylake: Ensure FSP don't override ITSS IPCx registersSubrata Banik
This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/pch: Select Kconfig for ITSS polarity configurationSubrata Banik
This patch selects Kconfig for Intel Core Platform in order to ensure proper ITSS IPCx programming. Change-Id: I81e75e17ceb23c364b78300c3950144be1580700 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timingsChris Zhou
After adjustment on Liara EVT H1: 392.03 KHz TP: 397.87 KHz TS: 397.71 KHz BUG=b:116309237 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-08mainboard/google/kahlee: Set PSPP setting to BalancedHighAkshu Agrawal
Setting default PSPP setting to BalancedLow was causing audio playback issue in most of the units. With BalancedLow either there was no sound or noise on playback. Switching to BalancedHigh as default option. BUG=b:116553085, b:112020107 TEST=Test playback and hear proper audio. Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/28967 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferencedSubrata Banik
This patch fixes KW issue due to pointer being NULL and will be dereferenced Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28948 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for BobbaPan Sheng-Liang
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 3 for DVT. BUG=b:115697578 TEST=verified it in Bobba EVT board which rework ram id. Change-Id: I0fb457d8772f5038e5d90188d7682956ddfad46b Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28891 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08smmstore: Add a key/val store facility in flash, mediated through SMMPatrick Georgi
It exposes an interface that is as generic as possible, so payloads and/or kernels can use it for their data. Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25182 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08mb/google/poppy/variant/nocturne: correct wifi wake registerNick Vaccaro
Wifi wake register is incorrectly set in devicetree. Set wifi wake to its correct wake source, GPE0_DW2_01. BUG=b:117330593 TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture, connect wifi to a hotspot, suspend device, echo freeze > /sys/power/state, and then shutdown the hotspot and verify device wakes. Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28938 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08mb/google/poppy/variant/nocturne: Disable WAKE# signalNick Vaccaro
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now floating and must be disabled. This change disables WAKE#. BUG=b:117284700 TEST=none Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-08nb/intel/{gm45,i945,pineview}: Use macro instead of GGC addressElyes HAOUAS
Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-06arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer
coreboot does not set up virtual memory anymore. Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06mb/emulation/*-riscv: Remove "UCB" from RISC-V board namesJonathan Neuschäfer
RISC-V is not a project of the University of California, Berkeley, anymore; it stands on its own feet now. Remove the "UCB" component from the RISC-V mainboards in the "emulation" directory, and don't set MAINBOARD_VENDOR to UCB, either. Change-Id: I301d9d0091a714e62375052e5af06a9197876688 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_* macros, this change uses lower case x for *RXD*. It helps avoid confusion when using the macros. Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06mb/google/poppy/var/ampton: Get rid of min board id for DRAM in CBIFurquan Shaikh
All ampton boards should have the DRAM info configured in CBI and so DRAM_PART_NUM_ALWAYS_IN_CBI is already selected for ampton. This change gets rid of the redundant minimum board id value for Ampton. BUG=b:117071184 Change-Id: I59f60b8c5aa34b55b8e473c06cc49ea7ae284d62 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06mb/google/octopus/variants/fleex: Disable I2C0 in devicetreeFurquan Shaikh
Fleex does not have any device on I2C0 and hence this change disables I2C0 device (16.0) in devicetree and gets rid of the I2C tuning parameters for I2C0. BUG=b:115600671 Change-Id: Ib799eae05b667cee2272bbd37f0ca44b7cec66cd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06mb/google/octopus: Disable I2C3 in devicetreeFurquan Shaikh
I2C3 is connected to the debug header and won't be required unless connecting the debugger. This change disables I2C3 device (16.3) in devicetree. Change-Id: I650fa040075119a21864c83d8470dd2155c9edb9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-10-06mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSDFurquan Shaikh
This change uses the generic device driver to provide DMIC properties in ACPI table to the OS driver. BUG=b:112888584 Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28797 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06drivers/generic: Add support for providing DSD propertiesFurquan Shaikh
This change adds support in generic device driver to add properties to DSD table. This driver can be used by all generic devices that do not need any special handling other than simply adding device properties to be used by OS. BUG=b:112888584 Change-Id: I0ca6614f1ef322397618676bbf6da898bef18990 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28796 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06soc/intel/common/block/hda: Enable static scanning of devices under HDAFurquan Shaikh
This change sets scan_bus operation for HDA to scan_static_bus to allow enumeration of static devices under HDA. BUG=b:112888584 TEST=Verified that devices added under HDA get enumerated on Nocturne. Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28807 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06soc/intel/.../hda: Add and use config for initialization of HDA codecsFurquan Shaikh
Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for initialization of HDA codecs only. This prevents adding of any static devices under the HDA device node. However, there can be boards which want to add devices under HDA node (e.g. nocturne that wants to provide DMIC properties to OS) without performing any codec initialization using the HDA. This change: 1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can be set explicitly by the boards that want to perform codec initialization. 2. Uses newly added config option is used to guard the initialization functions for the codec. Rest of the device operations can still be used by all the other boards without having to use HDA codec initialization. 3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in kblrvp which is the only board enabling HDA codec initialization using common block code. 4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC. Above changes need to be bundled and pushed in as a single change in order to avoid breaking existing users. BUG=b:112888584 Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-05soc/intel/skylake: check for NULL with if conditionPratik Prajapati
This patch removes assert() and checks if the dev is NULL with "if" condition only. Found-by: klockwork Change-Id: Icd2c8490c8bda14ecd752437d463a7110fe40aea Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/28888 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05mb/google/octopus: adjust Bobba I2C CLK under 400KHzPan Sheng-Liang
Need to tune I2C bus 0/6/7 clock frequency under the 400KHz for digitizer, touchpad, and touchscreen. Bug=b:117126484 TEST=flash coreboot to the DUT and measure I2C bus 0/6/7 clock frequency whether can <400KHz Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28907 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05tpm2/tlcl_send_startup: correct TPM2_Startup error logicJoel Kitching
BUG=b:114018226 TEST=compile coreboot Change-Id: Iffad582d5c19252dde1c9dc97fc7fd145944a3b3 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-05drivers/spi/winbond: Add new chipPatrick Rudolph
The W25Q128J is a QSPI flash chip, without ~HOLD and ~WP. Add the device id to make coreboot boot from it. Change-Id: I623fdf7d7e30eb28259bec6294785ad873f1f503 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-05src/lib/edid.c: Replace #if 1 with something usefulAngel Pons
Since `#if 1` is rather useless, and the code inside it is just several `printk(BIOS_SPEW)`, using `if (console_log_level(BIOS_SPEW))` instead seems more reasonable. Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-05mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE skuSeunghwan Kim
Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber test, but the root cause is unclear. Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal reset issue, so we would apply it until find root cause of this issue. BUG=b:117130599 BRANCH=poppy TEST=Built and passed on reliability test with modified coreboot Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28785 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-10-05atlas: control touchscreen power using ACPICaveh Jalali
This adds the ACPI controls for power sequencing the touchscreen. The initial setting is to keep the touchscreen powered off and in reset. When linux is ready to talk to the touchscreen, it powers it on and releases reset via ACPI. BUG=b:110286344 TEST=verified touchscreen is functional in chromeos Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28869 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05amd/stoneyridge: Comment PCI and AcpiMmio registers in ASLMarshall Dawson
TEST=Build Grunt BUG=b:77602074 Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-05amd/stoneyridge: Remove unused registers from ASLMarshall Dawson
Remove AcpiMmio and PCI config registers that are not used. TEST=build Grunt BUG=b:77602074 Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-05amd/stoneyridge: Remove SATA D0 on suspendMarshall Dawson
Remove the step of setting the SATA controller to S0 as the system is entering S3. This had been duplicated from AMD's FchCarrizo.asl file, but upon closer inspection, the conditions for this step to run cannot be met. This does not affect Grunt's behavior, as the SATA controller is disabled. TEST=Suspend and resume Grunt BUG=b:77602074 Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04mb/google/kahlee: Don't set stapm parametersMartin Roth
Setting the stapm parameters is causing S3 resume failures and performance issues. Removing these settings until more testing is done and the issues are solved. BUG=b:117252463, b:116870267 TEST=boot grunt Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-04google/grunt: Correctly extract OEM string from CBFSKevin Chiu
In CBFS layout: oem.bin size is 10 bytes. In cbfs_boot_load_file, buffer size will need to be larger than decompressed_size, otherwise CBFS data can not be extracted into buffer. Then we need to check buffer whether it's empty string separately. BUG=b:79874904 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I4f1bbb690ecca515ac920f5058ee19b5bfd8fa5e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04console: Enable CONSOLE_USB by defaultNico Huber
It seems to be the only user of the USB debug driver. So having to enable it separately seems wrong. It still depends on the selection of the EHCI debug driver. Change-Id: I5f5f38a912423d9b8f1e71ae875b6a14fdee651c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-10-04mb/intel/cannonlake_rvp: Move FSP param override function to separate fileRizwan Qureshi
Move the FSP param initialization function to a separate file, as being done on the SoC side and remove the empty romstage.c file. Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04soc/intel/cannonlake: Move the FSP related callbacks to separate filesRizwan Qureshi
Move funtions callbacks used to override FSP upd values to separate files. This serves as a base change for SoCs for which FSP is still under development, and hence the FSP header files are not available yet and in turn the UPDs cannot be referred. These newer SoCs will implement empty callbacks. The code will compile with basic header files which only include the architectural FSP structures. This allows plugging in these separate files for compilation in an environment where FSP header files are available. The fact is, FSP header files are not released externally until PRQ. However the teams at intel and some partners have access to the development version of these files. This code refactor helps to continue development on the pre-PRQ silicons and submit related code to coreboot.org. BUG=None BRANCH=None TEST=Build for cnlrvp Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04arch/x86: Make mb/romstage.c optionalRizwan Qureshi
Currently src/mainboard/*/romstage.c is mandatory for compiling, this makes having the file present even though there is nothing to initialize in romstage on the mainboard side. Eliminate the need to have empty romstage.c files using the wildcard function. BUG=None BRANCH=None TEST= build cannonlake_rvp after removing the romstage.c file. Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-04soc/nvidia/tegra124: Increase bootblock sizePatrick Rudolph
Increase bootblock size by 4KiB and reduce romstage by 4 KiB. Change-Id: I604fd9c63a4cf6fb7b18249a6d73cd637e184a71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04mb/google/poppy/variant/nocturne: update GPIO configurationNick Vaccaro
GPP_C19 is not being set as the code is incorrectly setting GPP_C16 instead, causing SAR sensor not to work, so this change sets GPP_C19 to NF1. GPP_E3 is not being initialized in the code. Initialize GPP_E3 to a no connect as documented in the board schematic. BUG=b:117124878 TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and verify that i2c transactions work for the left SAR sensor. Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28867 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variant/nocturne: increase touchscreen reset delayNick Vaccaro
Increase the reset delay for the touchscreen to 10 ms. BUG=b:116857433 TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, log in and execute the following two commands: echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind and verify the bind command does not echo back a "-bash: echo: write error: No such device" error. Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28803 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04soc/intel/common: add acpi_get_sleep_type to pmclibBora Guvendik
Change-Id: I3f4123657a375211f802a7d484a15353f9a256e9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-10-04amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 statusEdward Hill
Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers on boot. print_num_status_bits() was already using BIOS_DEBUG. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/28885 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04amd/stoneyridge: Prepare for vboot rebooting systemMarshall Dawson
Implement the function vboot_platform_prepare_reboot() which is normally a weak function. The SlpTyp field of the PM1 register is not reset to its default value when the APU restarts. This change prevents a failing condition if vboot decides to reset the system instead of allowing an S3 resume to continue. TEST=Resume Grunt when vboot attempts a reset, verify a fresh boot instead BUG=b:117089826 Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28877 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variants/rammus: Shorten oem_table_id to RAMMUSmarxwang
This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS" so that the audio topology file can be loaded properly by the operating system. BUG=b:112945714 BRANCH=master TEST=There is no error message like "failed to load topology firmware" in kernel v4.4 log. Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addressElyes HAOUAS
Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28847 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04sb/amd/pi/hudson: Remove #if 1Jonathan Neuschäfer
Change-Id: I4cf69dc3df2afaa8f33864374ea93548ab7ad810 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer
Clang doesn't understand -march=riscv64imac and -mcmodel=medany, so don't use them when running the clang static analyzer. On the other hand, __riscv and __riscv_xlen need to be defined in order to select some macros in src/arch/riscv/include/arch/encoding.h. __riscv_flen selects the floating-point paths in src/arch/riscv/misaligned.c. -mabi is moved with -march for consistency. A complete list of preprocessor definitions on RISC-V can be found at https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions With this commit, scan-build produces a useful result on RISC-V. Change-Id: Ia2eb8c3c2f7eb5ddd47db24b8e5fcd6eaf6c5589 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04cpu/intel/car: Fix typoElyes HAOUAS
Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-04mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for FleexIvy Jian
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT. BUG=b:116721822 TEST=Verified it in Fleex EVT board which rework ram id. Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQDuncan Laurie
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04ec/google/chromeec: Define a sync IRQ if neededDuncan Laurie
Some boards are adding a second pin used for synchronization between the EC and AP. This is a direct connection between the EC and the SOC that is intended to provide a lower latency interrupt signal for sensors on the EC. Currently the runtime EC interrupts assert an SCI before eventually resulting in a Notify() on the MKBP device that the sensor driver users. These extra layers add processing time and require additional EC communication to determine the event source. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh
In order to enable the OS SPI driver to use the software interface of this controller the OPCODE menu has to be set up properly before locking the controller. This is done on baseboard level so that all variants will get this done as well. Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>