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2015-03-29build system: remove intermediate link step in vbootPatrick Georgi
This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I5405c0ee6bee203281e723feaecaee57fad8f6cb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29mips: add verstage configurationPatrick Georgi
Change-Id: I79b4969c34500fd51b1ce2ad751bc0723ee0afa2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9147 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29arch/x86/boot/smbios: Rename fill_dimm_manufacturer and make publicTimothy Pearson
Change-Id: Ib85701965337bb6231d8df59d43789dfe8a036d3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9136 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-29arch/x86/boot/smbios: Add additional SMBIOS defines and enumsTimothy Pearson
Change-Id: I337584d1f4ce32094c24478a99418e0775cf9ab5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9135 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29mainboard/asus/kfsn4-dre: Enable BIOS recovery jumperTimothy Pearson
The ASUS KFSN4-DRE has a physical BIOS recovery jumper; force coreboot into fallback mode if that jumper is set. Change-Id: I513299c3e3261fc76133a49813685d48c53a172a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9156 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-29drivers/pc80/mc146818rtc_early: Honor Kconfig reboot count clear settingTimothy Pearson
Change-Id: I6426ea2ca1732a6edfae059fe5dbf4f398bc9b98 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9155 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28armv8/secmon: SECMON_SRC is really SECMON_BINPatrick Georgi
It points to a binary. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I164d7f717a9523d187e2c215083e176b59fd5acc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9113 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arch/x86: Guard option table specific rules with HAVE_OPTION_TABLEPatrick Georgi
This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: Ia22c9fcbf8c629d0eb3f1356f80c4565f117d8b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9110 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28build system: normalize linker script file namesPatrick Georgi
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9107 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-28arch/arm64: Drop extra commentPatrick Georgi
This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I362e2f6a978de23e72e6fc9c83bc99457cd76d9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arch/arm: drop extra commentPatrick Georgi
This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I8a5dc66d8c0dc4ccdb6dc3d66b8cdbf50dc976ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9111 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28pistachio: don't open code ramstage loadingAaron Durbin
Use the run_ramstage() function to load and run ramstage. Change-Id: I783801bf506fa2f9608eefe1cd20257292c80af5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28mips: fix API expectations that break buildsAaron Durbin
Add the approrpiate car* empty implementations as well as types included within the rest of coreboot to start building correctly. Change-Id: Ifaf10281f9a9e28f518f4694630cbffa3f8d187d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Aaron Durbin <adurbin@google.com>
2015-03-28storm: need larger CBFS cacheVadim Bendebury
With VPD blob of certain format, CBFS cache on storm proves to be not large enough. This patch makes it bigger, it is still well above the area preserved for the NSS. BUG=chrome-os-partner:32152 TEST=the system now boots with the VPD it used to fail booting. Change-Id: Iee1214b218ee3f8aca28797841501c227549affb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f19ca8cb9a2efa1d295f038730ed06ec9ceb8c4 Original-Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219572 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: fix SW_RESET signal polarityVadim Bendebury
The actual level required to take the ethernet switch out of reset is low, not high. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353 Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217416 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9121 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: deassert SW_RESET signal at startupVadim Bendebury
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet switch reset pit. The output stays low (or high-z) after power up, which holds the switch in reset. Deassert the signal at startup on hardware rev 1 and later. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154 Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217087 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9120 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: make sure board ID is calculated only onceVadim Bendebury
Figuring out board_id on storm requires reading tertiary gpios, which takes time. Let's calculate it once and reuse it when necessary. BUG=none TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2 respectively. Change-Id: I69f6afa3de8a175a1d723e95902efd15607e68b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 080c839c1c0c1b5e389b2382144ef67535bb4ff1 Original-Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217086 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: reset TPM properly on proto0Vadim Bendebury
The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22 pin instead of the system reset. This causes all kind of TPM behavior problems and requires frequent power cycles. Adding explicit TPM reset makes all those problems go away. BUG=chrome-os-partner:30705, chrome-os-partner:30829 TEST=tried resetting proto0 at different moments during boot up - the TPM does not fail anymore. Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6 Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211497 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: supply vboot GPIO settings in coreboot tableVadim Bendebury
Storm provides three real and two fake gpios. To keep things simple, define them all as active low and provide appropriate values for the fake ones. BUG=chrome-os-partner:30705 TEST=with the appropriate depthcharge change booted proto0, observed appropriate behavior following the dev switch setting Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210922 Reviewed-on: http://review.coreboot.org/9117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28blaze: update EMC BCT tableNeil Chen
This change updated the EMC tables with emc_reg_tool 5.0.18, for below memory SKUs: - Hynix H5TC4G63AFR-PBR 2GB, ramcode = 0 - Micron MT41K256M16HA-125 2GB, ramcode = 1 - Samsung K4B4G1646Q-HYK0 2GB, ramcode = 2 - Hynix H5TC8G63AFR-PBR 4GB, ramcode = 8 - Micron MT41K512M16TNA-125 4GB, ramcode = 9 - Samsung K4B8G1646Q-MYKO 4GB, ramcode = 10 BUG=chrome-os-partner:30963 BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Change-Id: Iee329ff09e35cddd3c868c0460a38ef56b2ac5bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 158872ff7c0dd5274cfa8d63ec17b4423a4592ce Original-Change-Id: I44adfdb5b433e37e2d25095acdcce3d9c14eb897 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210024 Original-Tested-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9116 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Add support for pmc_rst_status get and printFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully and pmc rst status POR is seen. Change-Id: Ic09cb46d9be7670e467543e42b251efb1a4313d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dbfae6bbc0f4f30e216e37b515f4120f7833a38 Original-Change-Id: Id0c2b208222deaf099b8938ba583551979588d52 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220721 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9106 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Replace use of clk_rst with CLK_RST_REGFurquan Shaikh
Also, get rid of unused clk_rst variables. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I6487162454159a81b31fe0d6d39c2bdbed3f859a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 030081fe85fc9609fdf2003cf51b7350e08f0429 Original-Change-Id: I880ae5c396c33006f6b184cca7f171e4373f4016 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220720 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: Add padconfigs for volup and voldown buttonsFurquan Shaikh
Both buttons are active low. BUG=chrome-os-partner:32517 BRANCH=None TEST=Compiles successfully and volup and voldown button presses are detected in pseudo keyboard driver in depthcharge Change-Id: If217a75f95042af8a831e7109d9b1acb10c55823 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c393e166a1ed0bc7920078aac6accf442abb5955 Original-Change-Id: I08f94972db53aa17a63f6e16cbaebe7af358cdc2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220687 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9104 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: measure romstage timingsAaron Durbin
Measure the MTS load time, MTS initialization time, and the ramstage verification/load time. BUG=None BRANCH=None TEST=Booted and noted timings. Change-Id: I1eb1e3a73316a3fa76ef8e73314bedde34c6c582 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b5b34a3abd388359b7d1cba5a858e4e5a402b476 Original-Change-Id: I71119689182e86406d5052f007908152d41e9092 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219715 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9103 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28rush: ryu: remove mainboard_add_memory_ranges()Aaron Durbin
There's no need to add DMA ranges for these boards as that memory is allocated within dpethcharge now. Additionally, the DRAM_DMA_* Kconfig options were removed resulting in 0 values. BUG=None TEST=Built rush and ryu. BRANCH=None Change-Id: I597437960e4fddbf6d26f0b15ddeefc4557adc8b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f26b503d759b2bac902e58e928d7c625c1a6c575 Original-Change-Id: I52bb8f760a56226c75611f7981570a44d56f242e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219710 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9101 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132/rush/ryu: Use CLK_RST_REG instead of &clk_rst->...Furquan Shaikh
BUG=chrome-os-partner:31821 BRANCH=None TEST=Built and booted to kernel prompt on ryu. Rush compiled successfully. Change-Id: I63ba55c53094c185d72dcb5c5d0d766461989806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a9aa565244bae5659e458ea90064eb5b803d574 Original-Change-Id: I5b00fbcb8e414c67563f1ad548f84c281898f939 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219392 Original-Reviewed-by: Tom Warren <twarren3959@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Clean up clock register writesFurquan Shaikh
Clean up functions to write to clk_enb and rst_dev registers and add clock_disable and clock_set_reset functions to provide a complete API for updating the registers. BUG=chrome-os-partner:31821 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles successfully on rush Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183 Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219191 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9099 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28arm64: remove EL and mode from secmon_paramsAaron Durbin
Since PSCI dynamically determines which EL to transition to based on SCR_EL3 there's no need to provide that information. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel with MP. Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add psci support to secmonAaron Durbin
The PSCI functionality initially includes CPU_ON and CPU_OFF functions. Upon entering secmon if the parameters are non-NULL then a PSCI CPU_ON action is done for the current CPU. BUG=chrome-os-partner:32112 BRANCH=None TEST=Booted kernel with PSCI support. Brought up all CPUs in kernel using PSCI. Turned CPUs on and off. Change-Id: I256fa45a1c9889ff9d7990eb1898df1ec241c117 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 689ba03e313e7e52e9b74aa774897b55cbd52748 Original-Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218923 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9097 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28arm64: Provide secmon trampoline for restartAaron Durbin
If an exception is taken that the secmon won't return to, there needs to be way to reset that cpu's state w.r.t. stack usage. Therefore, provide secmon_trampoline which will reinitialize the exception stack and SP_EL0 and start executing with SP_EL0 like the initial state of the secmon entry. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Also tested when PSCI is employed in the kernel. Change-Id: Ie9f5bbe715dcbcf8b67ea40f9a3a5088ac7aa2ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1f546ee3e9eca93baaa1ae0437351205bf548a5 Original-Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218922 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9096 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28Ryu: Move I2C6 init to ramstageTom Warren
BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I9b094e9d22726d67d41f2ce78088f361c73895fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c0bfb5f747f55009b7c2b2ba4b24d91443b1639 Original-Change-Id: Idd5b95cfec7d3ade7508393b81ab3049ce15a2fb Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: fix smc bugs in secmonAaron Durbin
Two things: 1. Not returning once setting the return state. 2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x)) With these 2 changes arguments and results are being processed correctly. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and brought up SMP using PSCI. Change-Id: If76a207e1a434a4c08faaa535f069d7386481e9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 42d540afd4e6ea2b34cf3632ad2c683fcaa063c8 Original-Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218847 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9094 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28Ryu: Rewrite I2C6 mux initTom Warren
Do the absolute minimum needed to allow the DPAUX mux ctl write for I2C6. This leaves HOST1X off (reset and clock disabled) to avoid a conflict with any kernel display driver init. I2C6 init/enable will be moved to ramstage in the next CL. BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I42106778a26c5a1d1483cc308b8314599c391539 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a9ebfda31c620b24e5c765dc950b87e3e5587b Original-Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9093 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add smc layer to secmonAaron Durbin
In order to process PSCI commands SMC instructions need to be serviced. Provide a simple way for users of SMC to register their handlers by function. The SMC layer hooks into the exception processing, however it only processes AARCH64 SMC calls. All others are ignored. BUG=chrome-os-partner:32112 BRANCH=None TEST=Added nop smc call to depthcharge. SMC handled and continue booting to kernel. Change-Id: I378f13c29220ff9f37040f094bf9cfb69259af0c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76d2febc50397348b68d38532b8f37e2b3cf6a30 Original-Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218846 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9092 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: initialize secmon environmentAaron Durbin
The exception vectors were not reinitialized in secmon yet. Add that as well as the split BSP vs non-BSP path. In doing so bring in the cpu.c semantics for determining bsp at runtime. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Also noted only one CPU printing messages. Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32 Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218845 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9091 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: provide entry points for BSP and non-BSPAaron Durbin
It's helpful to differentiate the startup paths for the BSP and the non-BSP. Therefore have c_entry be an 2 element array of function pointers. The non-BSP paths have an entry point one instruction after stage/module entry. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Change-Id: I40bb40462906f1b1eaf2db8584985095e8ac0bae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce10f954041b3fd581ad8a3d82dee567b68637fe Original-Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218844 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9090 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: split cpu.cAaron Durbin
The cpu.c contains some helpful construts as well as ramstage devicetree handling. Split the 2 pieces so that cpu.c can be reused in secmon. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted. Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218842 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9089 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: exception handler registrationAaron Durbin
In order to build upon the arm64 exception handlers need to be registered. This provides very basic support to register a handler for a specific exception vector. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel. Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218650 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9088 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28rush: use generic spin table supportAaron Durbin
With the generic spin table support in place, use that. BUG=chrome-os-partner:32082 BRANCH=None TEST=None Change-Id: I7c9ebd16cd7d5e938e686df2225c612581382983 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb0d79f89e27fcd51cc751a94008b3801f5c6d0b Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: Ic9949144ed1e9a952290d50b6726bf5891547896 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218657 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9087 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: use generic spin tableAaron Durbin
With the generic spin table support in place, use that. BUG=chrome-os-partner:32082 BRANCH=None TEST=Booted into kernel. Change-Id: I8644f8a81b24bf4e00f8fac1d1018f9db77c952f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1a4fe27070a80c8448051ec0565120901378673 Original-Change-Id: Id0832a4553101a366f011099e0744f6630d91924 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218656 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9086 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: remove private spin table implementationAaron Durbin
Support the generic spin table code instead of having the one-off implementation. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor. Change-Id: I8557298d1a159b70818cbd8864470ff0d8a46fb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d89af95a7919f0b8acc92d82f3abda965514ccf Original-Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218655 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9085 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add spin table supportAaron Durbin
There was a hacky and one-off spin table support in tegra132. Make this support generic for all arm64 chips. BUG=chrome-os-partner:32082 BRANCH=None TEST=Ran with and without secure monitor booting smp into the kernel. Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748 Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218654 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9084 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add cpu_is_bsp() conceptAaron Durbin
It's helpful to know if the current running CPU is the BSP. Therefore, provide that semantic. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: I18cb8ab5149c3337e22b1f6046b1af266be7e47c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b390dc70b658c207cd3b64408713ec4cddab3172 Original-Change-Id: I3d5518d1f6d6a78b14f25bb7ef79727605064561 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218653 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9083 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: provide run on all cpu but self semanticsAaron Durbin
In order to provide richer semantics for running code on all CPUs add an all-but-self construct. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: If8dd28ff7f34d93592ab2025a65a2fd665e4e608 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4622f63a065f620f0c92ef92eeb2aa5c2b441d Original-Change-Id: Id18dc0423bcb0016ed36ace659b3f858e824c46c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218652 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9082 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Add secmon supportFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and secmon loads and jumps to payload successfully. Change-Id: I929cf2c938fb5d8c20e13fbd1fdbd349378914ff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2e5d6adc63c4d820417985e34f1f04810b38422b Original-Change-Id: I442546178ad945e7639a99dd2943d13a69b06d09 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214372 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9081 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for secure monitorFurquan Shaikh
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Adapt stage_entry to make it usable by secmonFurquan Shaikh
stage_entry is the best place to enter for secmon, since it sets up all the stacks right. The only need we need to take care is losing out on the parameter passed to secmon. This patch adds an entry point for secmon rmodule and moves the argument from x0 to x25, which is restored just before the jump to c_entry BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I9638e9716b3bd5bff272e88fe9d965528d71e394 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ffedb03208bafab6d5886db0259ec205dd20588f Original-Change-Id: I74a7a609fbc08692d68708abe132cd219c89b456 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217570 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9079 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: initialize SCR_EL3 on all CPUsAaron Durbin
Provide SCR_EL3 initialization on all CPUs. This settings were chosen in such a way that nothing would need to be done if EL3 is abandoned after transitioning to EL2 or EL1. If persistent EL3 program is used those SCR policies can be updated within that program. BUG=chrome-os-partner:31634 BRANCH=None TEST=Built and booted through kernel. Printed out SCR setting for each CPU. Change-Id: Ib44acd8ae40dbca590740340632f5b72998e9dd8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f77b903afbafad7d439ec50fc48f1eaa37827d90 Original-Change-Id: Id659f0a98360fe8bbc80e5a623eba1526e81b400 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218300 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9078 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: use generic GIC driverAaron Durbin
As the arm64 boot flow handles initializing the GIC by way of the driver provide the SoC support for that driver and use it. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel on ryu. Change-Id: I6ba20339be8fc823e241b4299ad6c3deb82799fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 582cd9cef58e27aef2ce9c9b4fba4a78365bec6e Original-Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217514 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9077 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-28arm64: initialize GIC for each CPUAaron Durbin
For every CPU that comes online initialize the GIC for that CPU. This allows the per-cpu register state to be initialized for every CPU that comes online. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted to kernel on ryu. Change-Id: I467ca38d51ac67ffc19b1b4fc6fafa9394a876c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b2faf33fad80fd7ecb884d3ad40917f5a629a5b2 Original-Change-Id: I58d0ffcfe65cffc6a4dd2678c041219e1e698aaf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217513 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9076 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-28drivers: add GIC supportAaron Durbin
The GIC is ARM's "Generic Interrupt Controller". This change essentially implements the rudimentary support for a GICv2 implementation that routes all interrupts to Group1. This should also work for GICv1 with security extensions. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel using the code. Change-Id: I9c9202c1309ca9e711e00d742085a6728552c54b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d1cd9b6b76035af107b7dc876f90777698162d34 Original-Change-Id: I4c5b84bfe888ac33fa01c8d64a3dffe1b5ddc823 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217512 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9075 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-28arm64: Switch to EL2 for libpayload jumpFurquan Shaikh
CQ-DEPEND=CL:216826,CL:218300 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and we are able to start execution of libpayload in EL2 and reach kernel login prompt Change-Id: I233f9867470a4723f320dc0dcaa670a56dcf0f5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 169948a2afeeb7848daeb37600963bd503527f1a Original-Change-Id: I336d73085f08ca03e533555a10b88f20d74b4347 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217826 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28rush: Get rid of coreboot setting up DMA areas for libpayloadFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: Ife5300db8721a158f8a3b027aca4c51e4ea513a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 02bcdc7069e271563b7fd1893b92fb4d33cf8529 Original-Change-Id: I59e0f8d26d50baf68561b38f370195dea98881e1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217572 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9073 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: Get rid of coreboot setting up DMA areas for libpayloadFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and dma areas are setup fine by libpayload mmu Change-Id: I6d2d1dbcfc9bdeea94c89a9a3fce486203269642 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0425e87f21bcb92861240d6437769a5b28e9929b Original-Change-Id: I1034a4dcf6c9ee56bee4ea5d18e91a8d51895429 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217571 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Make exceptions use the transition libraryFurquan Shaikh
Transition library acts as a common interface for handling exceptions. The only thing that needs to be implemented by exception.c is the exc_dispatch routine to handle the exceptions as required. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and exceptions are tested using test_exc Change-Id: I90b4861909189adfe8449b9d4590965e6b743c00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b83c9404407dd4dd2dda4e4eaed0b443f0f58425 Original-Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217143 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for transition libraryFurquan Shaikh
Transition library provides the following functionalities: 1) Setup the environment for switching to any particular EL and jump to the loaded program at that EL. In short "Execute program X at exception level Y using the state Z" 2) Provides routines for exception entry and exception exit that can be used by any program to implement exception handling. The only routine required by the program would be exc_dispatch which handles the exception in its own required way and returns by making a call to exc_exit. On exc_exit, the transition library unwinds the whole stack by popping out the saved state of xregs BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and exceptions are tested for ramstage on ryu Change-Id: I8116556109665e61a53e4b3987d649e3cfed64a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ab888e8cae0c5f1e79b0e16ca292869f16f1cca Original-Change-Id: I90f664ac657258724dc0c79bd9f6ceef70064f90 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216375 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9070 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add useful macro definitions for register bitsFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Coreboot compiles successfully Change-Id: I1fba44974314effa1065e3637aaa5430584a4cc6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a4791232de764ebe40d9b3de5c63479dec7da003 Original-Change-Id: I95fdff5d1580faf4cb4f85d6acae7a834b8ff0bf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218031 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Reinit free_idx to 1 in mmu_initFurquan Shaikh
If mmu_init is called more than once then, free_idx should be reset to 1. Here, the assumption would be that mmu_init will not be called more than once. However, this is not necessarily true. Thus, free_idx should be reset to 1 every time we are initializing ttb from scratch. BUG=None BRANCH=None TEST=Compiles sucessfully and boots to kernel Change-Id: I5ac0af43346a492583380b0f15101390fc98d182 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 398a68c3b08d82cfa521d235af2c1922629bdf56 Original-Change-Id: Idb7424df7dd577f263f12d1527dbd7fb89216d40 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216906 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9068 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28rush: Add cpu devices to devicetreeTom Warren
Rush builds were throwing a _sync_sp_el0 exception due to commit 65af2f3d (tegra132: support arm64 SMP bringup). Fixed by copying over the rush_ryu devicetree.db, which adds all the CPUs to the device tree. Basically the same as commit 8f61ca2da but for rush. BUG=None BRANCH=None TEST=Booted rush OK, brought up rush kernel from USB. Change-Id: Ia91260ed36364ae1cfdd28932f09df9486c7e638 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 649391a402527cef1465d5a948323ad95c77917d Original-Change-Id: Ic9e34494ec8e6ad82e6020df6ad6fecd8763ac7e Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217792 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9067 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: check for NULL bus on DEVICE_PATH_CPU_CLUSTER devicesAaron Durbin
If there are no devices underneath a device in a devicetree the bus pointer in a struct device is NULL. Check for this condition before proceeding in walking through the children devices. BUG=chrome-os-partner:31761 BRANCH=None TEST=Ran through coreboot w/o any devices under the cpu_cluster device. No more exceptions. Change-Id: I9aedbc0dffc638b878bd0ffacfa318b6eb30d504 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d21e181077eba3c5ee03afca1738a24c21a8fc19 Original-Change-Id: I891aeb36319dce67ce9e431156c85c74177c7ab7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217511 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Replace CONFIG_* variables with {read/write}_currentFurquan Shaikh
Instead of relying on config variables to determine the current el, use {read/write}_current macros for accessing registers. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and boots to kernel login prompt Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564 Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217148 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions for writing sp_elxFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932 Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216905 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions with el argumentFurquan Shaikh
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for read and write registers at current EL in assemblyFurquan Shaikh
In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I51749b6e4ae7b1ffbaae28d915cd100a28959f26 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c11c7287f507fa398cbbee75abc2bd11140ef19b Original-Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: update MTS version formattingAaron Durbin
Nvidia tracks their MTS versions using decimals. Update the format so there isn't an extra step in communicating versions while debugging things. BUG=chrome-os-partner:31864 BRANCH=None TEST=Booted and confirmed decimal print out. Change-Id: I8d8b8a6e9b80548509dd8a30abb17c9970afdead Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7deb04a1deed41e1a54713320a29f6731401b35 Original-Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217260 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: remove bring_up_secondary_cpu chip optionAaron Durbin
Now that there is cpu devicetree support retire the bring_up_secondary_cpu option as the devicetree is the way going forward to do other CPU bring up. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted with 2nd core. Change-Id: I3e8812cd2183f2126c11c36ff4844c15b3cbfc1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7eab33b763d33d6be210ddb69e3c67411bad0fd0 Original-Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216929 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9060 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: remove bring_up_secondary_cpu from devicetreeAaron Durbin
Now that arm64 and tegra132 has cpu devicetree support stop using the bring_up_secondary_cpu option. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and brought up 2nd core. Change-Id: I3ffca6c1fa0932d8aafea30a160608b5593ae154 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c45b22ce9fd0345c3e599fd814993db66e2b96cc Original-Change-Id: I210bea73f8249de15f99d0c062600e789184eefd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216928 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9059 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27cbfs/rmodule: add architecture specific operations at stage loadIonela Voinescu
Two weak functions were added so that architecture specific operations on each segment of payload or stage can be performed. Each architecture must define its own operations, otherwise the behavior will default to do-nothing functions. This patch has been updated by to fit more in line with how program loading is currently being done. The API is the same as the original, but all call sites to stages/payloads have been updated. This is known to break any archs that use rmodule loading that needs cache maintenance. That will be fixed in a forthcoming patch. Also, the vboot paths are left as is for easier upstreaming of the rest of the vboot patches. Original-Change-Id: Ie29e7f9027dd430c8b4dde9848fa3413c5dbfbfa Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239881 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit c82c21ce87a4c02bd9219548a4226a58e77beef0) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ifcee5cd9ac5dbca991556296eb5e170b47b77af7 Reviewed-on: http://review.coreboot.org/8837 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-27northbridge/amd/amdfam10: Properly implement SLIT generationTimothy Pearson
Change-Id: I973abf2224762bf7a53d71177544ade15db50cba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8856 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-27broadwell: add support for smbios type17 in broadwellKane Chen
This change also depends on mrc due to changes in pei_data.h Report smbios type 17 for each memory CQ-DEPEND=CL:210005 BUG=None BRANCH=None TEST=Compiles successfully See smbios type17 in OS by dmidecode Original-Change-Id: If83c99364726cd17c719a59ed8ac993736c63b9a Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210399 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 6da6b4ffb3a45fdd766b88220c2adb168b3c5e10) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I39ea9ef9b342239fe26846ab0a928f6a680c21e8 Reviewed-on: http://review.coreboot.org/8956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-27smbios: add funtion for smbios type17Kane Chen
Add smbios type 17 which can optionally be implemented at the platform or mainboard level In order to create SMBIOS type17, you will need to fill memory_info data BUG=None BRANCH=None TEST=Compile successfully on rambi and samus Boot to chromeOS on samus and rambi Original-Change-Id: Ie4da89135c879d7a687305d423103fcfcbb96e3f Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210005 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 634b899ba41242caa800d7b570f3a339c738db77) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I61d1e8b1d32d43f0011b0f93966d57646ea0eb63 Reviewed-on: http://review.coreboot.org/8955 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-27mips: Remove superfluous menu entryPatrick Georgi
Change-Id: Iaf8167839f8506bd2ab08c2ba9f8317ba2437f28 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: Paul Menzel Reviewed-on: http://review.coreboot.org/9054 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-27rk3288: Add GPIO() macroJulius Werner
The static gpio_t initializers are stylish, but they are still a little too annoying to write and read in day-to-day use. Let's wrap that in a macro to make it a little easier to handle. BUG=None TEST=None Change-Id: If41b2b3fd3c3f94797d314ba5f3ffcb2a250a005 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 102a5c0a800f43d688d11d1d7bbc51e360341517 Original-Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220250 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9052 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27rk3288: Add missing #include and use uniform typesDavid Hendricks
This updates timer.h to #include the header necessary for u32, and to change the one instance of uint32_t to u32 to be uniform. BUG=none BRANCH=none TEST=compiled Change-Id: I4d67045206fd94985774b8d46a307bbb2e337f30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ff2629fdf3c69c203fa61ec894bb4895990cb5e Original-Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220612 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27pinky: Add mainboard-specific bootblock initDavid Hendricks
This adds a mainboard-specific bootblock function that will be used to set up some board-specific parameters which are currently set up in the SoC bootblock function. BUG=none BRANCH=none TEST=built and booted on Pinky Change-Id: I86c90f7ade824fb9d6b71ca3349d1ce9eb4772fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 03e0bb2eaca7a54c3df95b21d856ef4114d3c833 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibee7076ebd6080f04b0697067e85ce8b6b2230e4 Original-Reviewed-on: https://chromium-review.googlesource.com/220399 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9050 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27soc/imgtec/pistachio: Add IMGTEC SPI controller driverIonela Voinescu
The Serial Peripheral Flash Interface (SPFI) block allows communication with various devices over the SPI bus. It uses a configurable transaction interface and it clocks the bus according to the configured command, address, gap (aka dummy) and data lengths. This controller requires the SPI_ATOMIC_SEQUENCING flag set (write and read done in the same transaction) as it cannot directly control CS and will assert/de-assert CS at the beginning/end of a transaction itself. Note that the size of any transfer cannot be greater than 64KB - 1, as this is configured in a 16-bit field. The SOC has 2 SPFI interfaces each of them providing 5 slave select lines. SPFI 0 supports single and dual modes, SPFI 1 supports single, dual and quad modes. For SPFI interface 0: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi0clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set - CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim0_d0_txd MFIO_MIPS_10 0 spim0_d1_rxd MFIO_MIPS_9 0 spim0_mclk MFIO_MIPS_8 0 spim0_cs0 MFIO_MIPS_2 1 spim0_cs1 MFIO_MIPS_1 1 spim0_cs2 MFIO_MIPS_55 1 MFIO_MIPS_28 1 spim0_cs3 MFIO_MIPS_56 1 MFIO_MIPS_29 1 spim0_cs4 MFIO_MIPS_57 1 MFIO_MIMPS_30 1 For SPFI interface 1: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi1clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set - CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim1_d0_txd MFIO_MIPS_5 0 spim1_d1_rxd MFIO_MIPS_4 0 spim1_mclk MFIO_MIPS_3 0 spim1_d2 MFIO_MIPS_6 0 spim1_d3 MFIO_MIPS_7 0 spim1_cs0 MFIO_MIPS_0 0 spim1_cs1 MFIO_MIPS_1 0 MFIO_MIPS_58 1 spim1_cs2 MFIO_MIPS_2 0 MFIO_MIPS_55 2 MFIO_MIPS_31 1 spim1_cs3 MFIO_MIPS_56 2 spim1_cs4 MFIO_MIPS_57 2 BUG=chrome-os-partner:31438, chrome-os-partner:32441 TEST=Tested as bare-metal driver on Pistachio FPGA Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91 Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217320 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9049 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27urara: use proper SOC nameVadim Bendebury
Danube has become Pistachio, let's rename all instances where this SOC is mentioned. BUG=none TEST=board urara still builds Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78 Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220401 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/9048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27urara: introduce board skeletonVadim Bendebury
Not much is happening yet, when the board is enabled (in the next patch), all three components build successfully, the map files show them placed where expected and the bopotblock is wrappeed in a BIMG header. BUG=chrome-os-partner:31438 TEST=when config is enabled, emerge-urara coreboot succeeds. more extensive testing to come later Change-Id: Ib7396189f4bee0fdd6a8ce5c9ab1277806cb5dcc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1ca9efe59a7fcb99412410d509a7f9a91b6ef3ec Original-Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214600 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9047 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove soc_secondary_cpu_init()Aaron Durbin
The original purpose of soc_secondary_cpu_init() was to provide a way for the SoC to run code on the secondary processors as they come up. Now that devicetree based bringup is supported there's no need to have this functionality. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP into linux. Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216927 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: support arm64 SMP bringupAaron Durbin
Use the formal devicetree way for bringing up each of the cpus. This includes providing a cpu_driver as well as calling arch_initialize_cpus() with the proper operations to start the cores. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP on ryu. Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216926 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9043 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27armv4: Build in SMP settings with non-SMP armv4 CPUsPatrick Georgi
There are some ARMv8/ARMv4 SoC where the ARMv8 part needs to be SMP aware but the ARMv4 part does not. Until we need real SMP on ARMv4, work around that situation with stub defines. Change-Id: Iec5b4302b19c17fe2b3f677b84a8edf4b4902946 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add devicetree based CPU startupAaron Durbin
This adds SMP bring up support for arm64 cpus. It's reliant on DEVICE_PATH_CPU devices in the devicetree. Then for each enabled device it attempts to start then initialize each CPU. Additionally, there is a cpu_action construct which allows for running actions on an individual cpu. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted both cores on ryu into linux. Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216925 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: split cpu.h headerAaron Durbin
Add a cpu-internal.h for internal prototypes to the architecture specific code. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted. Change-Id: I12a379f86056a9a2007a7c036d65b5e08e558d0e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dcd488326f6496d80eb1fe1ff4414ebba1280e9 Original-Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9041 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add spinlock implementationAaron Durbin
Provide a simple spinlock implentation for arm64. A value of 0 is unlocked and a value of 1 is locked. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup on ryu. Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216923 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9040 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: move spinlock.h to proper placeAaron Durbin
The spinlock header file was not residing in the correct place. It needs to live under 'arch/smp'. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with SMP. spinlock.h found. Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0 Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216922 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9039 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add more barrier supportAaron Durbin
The load-acquire/store-release operations (including exclusive variants) form a basis for atomic operations. Also remove the dmb, dsb, and isb functions from lib_helpers as barrier.h already included these. Lastly, utilize barrier.h. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup using barriers. Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118 Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216921 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9038 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove printk() before console_init()Aaron Durbin
printk() shouldn't be called until the consoles have been initialized. This just so happened to work by luck. Once CONFIG_SMP is enabled that breaks because of spinlock usage in uncached memory. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with CONFIG_SMP and ramstage doesn't hang early. Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0 Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216920 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9037 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: remove printk() before console_init()Aaron Durbin
printk() shouldn't be called until the consoles have been initialized. This just so happened to work by luck. Once CONFIG_SMP is enabled that breaks because of spinlock usage in uncached memory. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with CONFIG_SMP and ramstage doesn't hang early. Change-Id: I4bf5d98e409840cf07a7759e9273d770f3bbf8bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ec672e52eda69f2b5abb747807a496bb973088f Original-Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216429 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9036 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: update cpu.c licenseAaron Durbin
The code should be GPL. Update accordingly. BUG=chrome-os-partner:31761 BRANCH=None TEST=None Change-Id: I051ceb3f12e9938819b513413aae43cbf51d9b86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdff53ebf4c1a1d86d68054c2d25dce45b69ff48 Original-Change-Id: I26a40a239afd851d351dbda0d716ef992b88b6c8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216428 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9035 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: add cpus to device treeAaron Durbin
Add all the CPUs to the device tree. BUG=chrome-os-partner:31761 BRANCH=None TEST=Brought up 2nd core on ryu in kernel. Change-Id: I4cc51f30897e3bd6c1b275a95d5da34ce7ae320e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 485de634a49d606dc6e7168f047eb9365e26415f Original-Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216426 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9034 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Fix clock apisFurquan Shaikh
Instead of directly using the clk_src_id based on enum for clock source, every device needs to have its own set of clk source ids defined. This prevents accidentally selecting a wrong clk source if the ids are different from host1x's. Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for handling the common clock sources based on id to get the proper frequency in software. [pg: integrated a later commit to fix the build] BUG=chrome-os-partner:31821 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5d40fb49b81e8838b2be071d32c466213215e0d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27d5d6a34d1c826c6095c18368efb78c228d4ca8 Original-Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216761 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Commit-Id: 13c30c50a9e8a7f3c48673a2f6c144ba546129b6 Original-Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217342 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9033 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add midr_el1 accessor functionAaron Durbin
Provide access to the MIDR_EL1 register to obtain the main id for determining CPU implementer and part/revision information. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and printed the output of this function on ryu. Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216423 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: remove call to soc_configure_i2c6pad()Aaron Durbin
This function is breaking display bring up in the kernel. While this functionality may be needed it's not until there is a necessity to beep and/or bring up the display in firmware. BUG=chrome-os-partner:31820 BRANCH=None TEST=Sean ran with this patch and the display indeed did come up. Change-Id: I5cf8a6c6e6941ee138991933215f96f5562382be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038bc1d53028409d0640c78fb62c7025ba12dcb9 Original-Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216421 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9031 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: Remove old/unused BCT cfg filesTom Warren
These are not needed/were never really used. SDRAM init will now be done in sdram.c, not the BootROM. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built rush_ryu AOK. Change-Id: Id046592415574badb97026224e1e525c174eece4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7 Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/215863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9030 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add LPDDR3 SDRAM init in coreboot.Tom Warren
Expanded sdram.c to add support for LPDDR3 init. This code can be used with matching BCT .inc files to have LPDDR3 SDRAM initialized by coreboot instead of the T132 BootROM. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built for rush and rush_ryu. Change-Id: I53801d9399dbf67fd86d0a2521174f0668567620 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 60e130c47c1894925a12f251af5b83a1fa144d57 Original-Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: fix power button polarityAaron Durbin
The power button signal is driven from the silego part. It's active high when the button is pressed. BUG=None BRANCH=None TEST=Booted with power button pressed. vboot saw the press and requested a shut down. Change-Id: Ifff1bd8d4340849e0c218812fd401b61c90c5743 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b6bd7c0de38e1078b85f1671493c6d2948d43149 Original-Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214847 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9028 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27rush: use names for gpiosAaron Durbin
Instead of calling out the gpio index and port numbers use real names. It's semantically clearer and there's only one place to adjust the hardware values. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted. Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215542 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9027 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: configure plld for display usageAaron Durbin
The kernel doesn't have the logic for bringing up the plld. Therefore, configure it in the firmware. The clock used is an interim value until the display controller sequencing is fully implemented. BUG=chrome-os-partner:31640 BRANCH=None TEST=Noted configured freq is close to requested. Also, no more plld errors observed from the kernel. Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9026 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: return actual plld frequencyAaron Durbin
Depending on the requested frequency the plld cannot necessarily obtain the exact clock. Therefore provide the closest configured frequency as a return value. This is equivalent to the t124 patch. BUG=chrome-os-partner:31640 BRANCH=None TEST=Built and noted plld actual value close to requested. Change-Id: I9aaba81222fb97d9fbbb4156af3a7476ba654c10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc928db8197b465220e53b4d0ba5896b3c06a863 Original-Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214843 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9025 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: No need for Kconfig variables for stacksFurquan Shaikh
With the latest changes to include stack storage within ramstage, we no longer need to define Kconfig options for ramstage/exception stacks in arm64. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel on ryu Change-Id: I7361d8f567453e775240151fd1180c49025141b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9aaa89115a67606fcb66eb354741043f7f2094bf Original-Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214607 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9023 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>