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Disable unused TCSS PCIe port1
BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage
Change-Id: I2bdfdb23d010a1e24c986ab52b5cef6eedcb674e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Windows complains on missing drivers for these ACPI devices. Hide them
from OS as it doesn't influence the hardware operation. Linux can
still probe the drivers correctly.
TEST=Boot Windows 11 and see there are no devices with missing drivers.
Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are
still probed.
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Vell has a keyboard MCU connected to USB2 port 7. This patch enables
the port.
localhost# usb_updater2 -f
Found device.
found interface 0 endpoint 1, chunk_len 64
READY
-------
start
target running protocol version 6 (type 1)
maximum PDU size: 4096
Flash protection status: 0000
version: prism_v2.0.12137+c4ae1432f5
key_version: 1
min_rollback: 0
offset: writable at 0xc000
Current versions:
Writable prism_v2.0.12137+c4ae1432f5
BUG=b:203664745,b:211496726
TEST=Run 'usb_updater2 -f' on Vell.
Change-Id: Iad2140dbdf5e34332388f3f43b3ede3d22e73087
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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ChromeOS considers the WWAN devices to be untrusted, therefore enable
the new DmaProperty in the WWAN's _DSD to indicate to the OS that these
devices should have IOMMU restrictions applied to them.
BUG=b:215424986
BRANCH=brya
TEST=dump SSDT
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Similar to commit 09c047c, the WWAN device might be considered an
untrusted device by some platforms, therefore add an option to add the
same `DmaProperty` to the WWAN _DSD.
BUG=b:215424986
BRANCH=brya
TEST=dump SSDT, see new property
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If485ac5314fae6e6faefac43fcfcea4f4cdd02c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
broke jinlon boards without an electronic privacy screen (EPS) by
disabling the parent device (iGPU) instead of the EPS when determined to
be not present via SKU ID.
Commit c5a3a4a6
[mb/google/hatch (baseboard): add ACPI backlight support]
broke EPS detection by adding a duplicate iGPU device to the devicetree,
resulting in the EPS entry being skipped.
Fix both of these issues by assigning the device alias to the EPS child
device, not the parent (iGPU). Rename the alias for clarity, and combine
the duplicate device definitions for the iGPU.
Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.
Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 017b5c453a72f57ec785da1764939e24651ac5eb
[ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config]
broke tablet mode on google/caroline and cave in mainline Linux kernels
by changing the inclusion of the ChromeEC tablet mode ACPI handler. Fix
this by addding it back (using the updated name guarding the inclusion
of the tmbc ACPI).
Test: build/boot google/cave under Linux 5.16, observe tablet mode
handled correctly.
Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The patch uses Kconfigs for Descriptor Region and Descriptor Region
size instead of locally defined macros
TEST=Build and boot Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3f9461c8604383f995a4438f45286b14fb94deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
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The patch defines Kconfigs for FMAP Descriptor Region and Descriptor
Region size. The Kconfigs will be used by follow-up patches.
TEST=Build Brya code
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia3481acefbda885617607675aef2afbb81c21c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BT didn't work due to commit 03c0853f4d58c73.
Commit 03c0853f4d58c73 accidentally set the Bluetooth USB2 port
to "empty", therefore re-enable USB2 port 9.
BUG=b:217238553, b:222238381
TEST=build and verfied BT work/suspend successfully
Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change is to move MPTS (Mainboard Prepare To Sleep) method from
wwan_power.asl to SSDT.
MPTS is mainboard-specific method, while wwan_power.asl is meant for
WWAN from its name.
Having fixed MPTS method (i.e. DSDT) can not cover the case where device
only presents and certain CBI bit(s) is(are) set.
In Redrix and Brya, there are SKUs with or without 5G, 4G device. For
those with 4G, MPTS method should be different. For those with no WWAN
device, no MPTS is needed.
Having MPTS generating in SSDT also eliminates the need for introducing
Kconfig flags to support different devices in the future.
MPTS method is created inside mainboard_fill_ssdt function in which the
corresponding variant function is called.
This will generate the following for the mainboard:
Scope (\_SB)
{
Method (MPTS, 1, Serialized)
{
Local0 = \_SB.PCI0.RP01.RTD3._STA ()
If ((Local0 == One))
{
\_SB.PCI0.RP01.PXSX.DPTS (Arg0)
}
}
}
Test:
Check the SSDT for MPTS method under \_SB after boot to OS
Use shutdown command and check the GPIO pins from logical analyzer
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add HID driver for i2c-1 for Ilitek touchscreen.
BRANCH=None
BUG=b:187289163
TEST=Build and flash coreboot; confirm an entry for hidraw for I2C-1 for
Ilitek touchscreen.
Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd
Signed-off-by: Rehan Ghori <rehang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This revert commit acb17fec34a609c5b674ad0d2af04d47800530e2.
This issue was fixed in the OS, therefore the workaround can be
reverted.
BUG=b:210497855
BRANCH=firmware-brya-14505.B
TEST=build coreboot and boot into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ic836e0cf53c2f9d30bd12851be285d864b2256b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move some structures to common folder (CB:61293), so we need to update
header version.
BUG=none
TEST=dram calibration pass
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Id82cbef9cb10dba71489ea96f67c329de9aadc49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Move some structures to common folder (CB:61293), so we need to update
header version for this.
BUG=none
TEST=dram calibration pass
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I8cf12f4967af116eaef88c1f688567f1da9fa6e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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SMMSTORE needs to have 64k size (minimum) and have 64k alignment as
enforced by asserts added in commit 1ba6049
[drivers/smmstore/store.c: Add static assertion based on fmap].
Adjust size and alignment of SMMSTORE region in FMAP to ensure those conditions are met.
Test: build google/morphius without asserts being tripped for above conditions.
Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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GPP_S6 was accidentally configured twice instead of configuring GPP_S7.
So configure GPP_S7 according to the schematics.
BUG=b:222218450
TEST=WCAM DMIC works on nivviks
Change-Id: I5de36aaa504a8856803c783564162c36416b50b7
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62511
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Infineon TPM 1.2 used on glados boards doesn't use a PIRQ;
Linux only works with 'tpm.tis_interrupts=0" and Windows fails to
init the TPM citing a lack of available resources. With the PIRQ
removed, both Linux and Windows are happy / the TPM is available
for use.
Test: build/boot Linux 5.16.x and Windows 11 on google/chell
Change-Id: I544695505291bbebe062df636cc8ddd139c08c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change loglevel prefix "BIOS_ERR" to "BIOS_DEBUG".
BUG=b:220639445
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ie3de63fc13e7a5ed6a4b4617542851782fbb6f00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62508
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In the northbridge's and root complex' read_resources function, the
GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index
which might be misleading. Instead use idx++ as a unique index for this
resource.
TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:
Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed)
After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8061364879d772469882fc060f92676de6f600a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In the northbridge's and root complex' read_resources function, the
mmconf resource used the number of the MMIO_CONF_BASE MSR as index which
might be misleading. Instead use idx++ as a unique index for this
resource.
TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:
Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed)
After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In order to align with established standards for establishing DMA
boundaries[1] from ACPI, the UntrustedDevice property has been renamed
to DmaProperty, which follows Microsoft's implementation. After
discussions with Microsoft, they have agreed to make the `UID` property
optional, so it is left out here, and instead it can be applied to:
1) Internal PCI devices
2) PCIe root ports
3) Downstream PCI(e) devices
[1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
BUG=b:215424986
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id70e916532e3d3d70305fc61473da28c702fc397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Stoneyridge with the other AMD SoCs. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=None, but equivalent change on Picasso was verified to not break
anything on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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After the patch that moved the generation of the PPKG object to
Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Picasso with Cezanne and Sabrina. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=Mandolin still boots successfully to Linux desktop and dmesg
doesn't show any any possibly related problems.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design
Capacity), only report the design capacity. This handles cases where
the battery calibration is incorrect, and the battery runs out before
the OS thinks it's empty.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Disabled G2touch driver and add ELAN touchpanel driver for vell.
Due to incorrect BIOS setting, touch screen IC FW can't update and work.
According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10
BUG=b:221340736
TEST=emerge-brya coreboot and can flash touch screen FW
Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
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Since we want to read the non-x86 CBMEMC from SMM we need to be stricter
on where we read from. This change forces the verstage binary and x86
code to agree on the CBMEMC transfer buffer location and size.
BUG=b:221231786
TEST=Boot guybrush and verify verstage transfer buffer still ends up in
cbmem
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Configure GPIOs according to schematics
BUG=b:218786363
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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We don't need to force the caller to look up and cast the transfer
region. We can do it in the function.
BUG=b:221231786
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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I want to reuse the transfer buffer methods in SMM, so I need to add
them into their own file. I renamed `setup_cbmem_console` to
`replay_transfer_buffer_cbmemc` so it has a more descriptive name. I
also fixed the comment on `verify_psp_transfer_buf`.
BUG=b:221231786
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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We need to save the transfer buffer so we can transfer the cbmem
console and timestamps into x86 DRAM.
BUG=b:221231786
TEST=Boot guybrush and verify S0i3 resume works. Also dumped the
transfer buffer from the OS and verified the console contents got
transferred.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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All SoCs/chipsets that select ARCH_X86 will end up using the
implementation in cpu/x86/lapic/lapic.c, so to avoid confusion, drop the
unused weak implementation that returns a different value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffcd8c80260f9a7d81dda41a0ad08bffc7620c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.
Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Both the secondary and subordinate bus numbers are configured in this
function but it's not easy to search for in the tree as the PCI writes
are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate
variables and PCI config writes to improve the readability.
Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.
This implementation is according to chapter 5.13 in MT8186 Functional
Specification.
BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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RTC_GPIO_USER_MASK is not used in any drivers, so we remove them.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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google/brask is using SODIMMs for DRAM. Reading spd data is
surprisingly slow (~170 ms), therefore enable the SPD cache.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=run on the device and measure the boot time decrease.
Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Align the setting with the adlrvp
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and works correctly in the brask
Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes Rcomp settings. In MRC design, it checks if the
Rcomp settings from the board is 0 or null, if so, it uses the
recommended Rcomp values. Otherwise, it uses the Rcomp settings passed
from the UPD. From the change history of MRC, we're chasing a moving
target. This RCOMP setting in coreboot is an old setting while the
Rcomp settins in MRC are optimized settings. Moving forward, if there
is a new stepping, it might be changed again which increases the
maintenance effort in coreboot. IMHO, we should let MRC to set the
optimized RCOMP values for the design.
BUG=b:219378758
TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and
PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are
filled properly by MRC.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.
BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
test reboot 30 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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If an AMD FSP binary has no valid image revision information, print a
warning instead of an error.
Change-Id: Ie9c5a387b81205fe93382778090260e41e261776
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Chausie doesn't have recovery mode buttons so it's impossible to
manually enter recovery mode to enable developer mode. This means we
need to force developer mode.
BUG=none
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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In order to abstract bus-specific logic from TPM logic, the prototype
for two vendor-specific tis functions are added in this
patch. tis_vendor_read() can be used to read directly from TPM
registers, and tis_vendor_write() can be used to write directly to TPM
registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I939cf5b6620b6f5f6d454c53fcaf37c153702acc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Instead of using raw integers to indicate success/failure, enum cb_err
can be used to makes things clearer, so this patch converts most
functions to return that instead of int.
TEST=boot to OS on google/dratini, no TPM errors seen
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifb749c931fe008b16d42fcf157af820ec8fbf5ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable STT and decrease sustained_power_limit_mW to 12W
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
update the thermal setting value by measurement and
pass the thermal performance test
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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coreboot should skip sending EOP during S3 resume since CSE doesn't
require EOP in resume path.
Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage
which doesn't get called during S3 resume.
In case EOP is moved in earlier stage, coreboot might send EOP in S3
resume as well. This patch adds check before calling cse_send_eop.
BUG=b:211085685
BRANCH=None
TEST=Check by moving EOP to earlier stage. EOP sending is skipped during
S3 resume.
Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e965513d5888398834cab8c8445e97372f2b115
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder
Lake N RVP from devicetree.
Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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This will allow linker flag customization for rmodules.
BUG=b:221231786
TEST=Build guybrush with patch train and verify ldflags are passed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Include chausie EC and EFS only in the RO region when building with
vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B
regions.
Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Currently the LPIT Get Constraints _DSM subfunction returns a package
containing the path to a nonexistent device (\NULL). This is used to
work around an issue with Windows, where returning an empty package will
cause a BSOD. However, using this non-existent device can also cause
confusion, as on Linux, it shows an error in dmesg, e.g.
ACPI Error: AE_NOT_FOUND, While resolving a named reference package
element - \NULL (20200925/dspkginit-438)
Therefore, this patch modifies this returned package slightly to include
the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on
Intel platforms that use the PEP driver.
Tested on google/brya0 on ChromeOS 5.10 kernel
Tested with current Windows 11 ISO
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
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This will allow to migrate all platform to the parallel_mp init code
and drop the old lapic_init code.
Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58700
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kano changes load switch of touch screen to TPS22914C (is not with
discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms
to fix DUT can't enter S0ix issue.
BUG=b:220811619
TEST=Boot kano to OS and run S0iX test 2500 cycles.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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BUG=b:214414301
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Configure D2 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for D2 device and enable the required
config items.
BUG=b:214414776
TEST=Build
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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BUG=b:214413613
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:214417045
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers.
BUG=b:214414677
TEST=Build
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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BUG=b:214414851
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The USB port configuration was derived from the PPR and schematics.
This board has 6(some multi-purpose) ports.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras
1 Bluetooth transceiver
BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Add xhci 2 controller support for additional USB port/ Dummy setting
BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add DPTS (device prepare to sleep) method that is to be called in
mainboard's \_SB.MPTS, which is called in _PTS.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie308f74940a33711a398bc11d0550cb06b55cdcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(),
it's our virtual `domain` device.
Expecting a PCI device above bus 0 resulted in undefined behavior for
all boards with PCI. Only boards with a PCI device 00:00.0 that looked
like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake).
Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add wifi sar table for kano
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
BUG=b:214393458
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Add wifi sar for pasara
BUG=b:216411442
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214416935
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:214414501
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214415048
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable ESPI SCI events
BUG=b:214416630
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214415408
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214413613
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214414033
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214415401
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add GPIO initialization and ACPI generation for tables
BUG=b:214415303
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This fixes no practical problem, especially for coreboot where only
one process should access the SPI controller. It makes the code look
more spec compliant.
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
Software must initiate the next SPI transaction when this bit is 0.
Add non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.
BUG=b:215255210
TEST=Able to boot brya and verified SPI read/write is successful.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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We print these out in the normal flow, so lets add them for S0i3 resume
as well.
BUG=b:221231786
TEST=Perform suspend/resume cycle on guybrush and verify we get the new
POST codes.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This feature was never used. Let's remove it to keep things simple.
BUG=221231786
TEST=Boot test guybrush and morphius and verify transfer buffer is
correctly passed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.
BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.
Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass
Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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- Add configurability using FW_CONFIG field in CBI, to enable/disable
I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion
board
Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on
expansion card
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This code only worked when the payload (a packed struct) was 4 byte
aligned. With gcc11 this happens to not be the case.
Change-Id: I5bb4ca4b27f8554208b12da177c51091ea6a108f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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coreboot uses port index which is 0 based for all PCIe root ports.
In case of PCIe remapping logic, coreboot reads LCAP register from PCIe
configuration space which contains port number (mostly 1 based). This
assumption might not be true for all the ports in coreboot.
TBT's LCAP registers are returning port index which are based on 2.
coreboot's PCIe remapping logic returns port index based on index 1.
This patch adds variable to pcie_rp_config to pass lcap_port_base to the
pcie remapping function, so coreboot can map any n-based LCAP encoding
to 0-based indexing scheme.
This patch updates correct lcap_port_base variable for all PCIe root
ports for all SOCs, so that function returns correct 0-based index from
LCAP port number.
BUG=b:210933428
BRANCH=None
TEST=Check if code compiles for all ADL boards
Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie92bd54b072d545944b3d0251e9727ce493bb864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use the definition from arch/x86 instead of a local redefinition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If172cde267062a8e759a9670ac93f4e74e8c94d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I875916488a99af768d087691549a93f6fd5169ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but
the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in
acpi/acpi.c, so define this option in arch/x86/Kconfig to have it
defined in all cases where the function that ends up using this
information gets called. Since we now have the type information for this
Kconfig option in a central place, it can be dropped from the Kconfig
file of the Intel southbridges that change the default value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using read32p to get the contents of the first 4 bytes of the HPET MMIO
region instead of a pointer dereference should clarify what's done in
that piece of code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecf5452c63635666d7d6b17e07a1bc6aa52e72fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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