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2023-05-24mb/siemens/mc_ehl1: Enable pi608gp I2C driverJan Samek
Add devicetree and Kconfig entries to enable additional configuration of the Pericom PI7C9X2G608GP PCIe switch on this board variant. The amplitude is being adjusted to 425 mV and de-emphasis level to 6.0 mV. BUG=none TEST=Read out the PCIe config space values of the switch and check if they match with the ones configured over SMBus. Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-24mb/siemens/mc_ehl4: Double payload size to 256 bytes for PCIe RP #2, #3Mario Scheithauer
To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and root port #3 (00:1c.2) set the max payload size to 256 bytes for both root ports. Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-24soc/intel/elkhartlake: Make PCIe root port max payload size configurableMario Scheithauer
The data payload size of PCIe root ports can be set to either 128 (default) or 256 bytes. A bigger payload size can improve PCIe data throughput on the given port. FSP-S provides a parameter to configure this value. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-24mb/google/nissa/var/uldren: Add fw_config probe for touchscreenDtrain Hsu
Use fw_config to probe touchscreen. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5d8129b3af3aa09e5bc31160de82d9ef7af0dd59 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-23mb/intel/archercity_crb: Add EWL Hob processing for MRC errorJohnny Lin
Override the weak function mainboard_ewl_check() and select OCP_EWL. Select IPMI_KCS_ROMSTAGE and IPMI_OCP for OCP IPMI commands which are needed for OCP EWL driver, but they are Meta-specific BMC commands and don't really work for AC, this change is just for a demonstration with AC. Note that FSP UPD promoteWarnings needs to be disabled so that FSP won't block and can return to coreboot for EWL processing when memory EWL type 3 error occurs. Tested=On Intel AC, connected with a faulty DIMM can see EWL type 3 error being generated and halted with coreboot log: [DEBUG] Number of EWL entries 3 [ERROR] EWL type: 3 size:32 severity level:1 [ERROR] Major Warning Code = 0x29, Minor Warning Code = 0x04, [ERROR] Major Checkpoint: 0xb7 [ERROR] Minor Checkpoint: 0x74 [ERROR] Socket 0 [ERROR] Channel 4 [ERROR] Dimm 0 [ERROR] Rank 0 [ERROR] IPMI: ipmi_get_board_config command failed (ret=3 resp=0xc1) [DEBUG] ipmi send memory training error [DEBUG] EWL type: 1 size:19 severity level:1 [DEBUG] 0x6392e968: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04 [DEBUG] 0x6392e978: 00 00 00 [DEBUG] EWL type: 1 size:19 severity level:1 [DEBUG] 0x6392e97b: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04 [DEBUG] 0x6392e98b: 00 00 01 [EMERG] Memory Training Error! Change-Id: I4602ae356aa6e55ed0611b8ac9a206db127c297c Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23drivers/ocp/ewl: Enforce MRC when there's EWL type3 errorJohnny Lin
If Fastboot is enabled, the next boot will skip MRC and won't be able to detect MRC error via EWL and still continues booting. Enforce FSP MRC training in the next boot. Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23soc/intel/xeon_sp: move and rename set_cmos_mrc_cold_boot_flagJohnny Lin
1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag in case a certain platform may not support this via CMOS data, and the function could in turn calls mainboard defined method in the future. Move the code into soc_util.c. 2. Remove redundant static get_system_memory_map() from cpx/romstage.c and call the soc_util.c one. Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23soc/intel/common: Add RPP-S PCI IDsJeremy Soller
Add PCI IDs to support Raptor Point PCH. Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2) Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-23mb/google/skyrim/var/winterhold: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=untested, but same error/fix as frostflow variant. Change-Id: Ic498afcc8b8e0224f344f405e2f1ef6184df1d6b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75340 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23cpu/x86/smm_stub.S: Fix commentArthur Heymans
The comment got stale because a few elements from the struct got dropped. Change-Id: I83469e24dfab82b9182accb549960dd06d81e02f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-23cpu/x86/smm_stub.S: Update commentArthur Heymans
%ebp is used for the stack frame on which the fxrstor address is pushed. entry64.inc does not trash it so that's fine. Change-Id: If027437dccac9ad507ceb534c6aae77ea43bdfda Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68896 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-23mb/google/skyrim/var/markarth: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=untested, but same error/fix as frostflow variant. Change-Id: Ie40541ada508acfa5771ea800249b8a57b168e3b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/skyrim/var/frostflow: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=build/boot frostflow, verify error no longer present in dmesg. Change-Id: I0b87af6b2c04f9354e6f394a8f987fa660e49134 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75338 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/nissa/var/yavilla: Generate LP5 RAM ID for K3KL6L60GM-MGCTShon Wang
Generate the RAM ID for Samsung K3KL6L60GM-MGCT. DRAM Part Name ID to assign K3KL6L60GM-MGCT 6 (0110) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I05a2cd5f2235702dea8fd706349ebda6a9ffa2ef Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-23src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header filesSrinidhi N Kaushik
This change updates Intel Copyright License for all header files under Sapphirerapids dir Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-23mb/starlabs/starbook: Add ramtop to CMOS layoutSean Rhodes
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23nb/intel/haswell: Allow using Broadwell MRC.binAngel Pons
This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell non-ULT CPUs (for which more magic is required). Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that the system remains on after 30 seconds. Apparently, something Broadwell MRC.bin does results in the ME being unhappy, as there is no such issue when not using MRC.bin at all (native RAM init). S3 resume is working. Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23mb/google/rex: Add FW_CONFIG and device for VPUEran Mitrani
BUG=b:282912666 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-23mb/google/rex: Add FW_CONFIG for TOUCH over SPIEran Mitrani
TEST=set the corresponding cbi bit, and saw SPI0 under sysfs BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I7099cde14cff90ad63e9164769f9913a8284a805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-23mb/google/skyrim/var/markarth: Update DPTC and STT settingsJohn Su
According to Thermal table 0518, adjust DPTC and STT settings. BRANCH=none BUG=b:273636128 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-05-22mb/amd/majolica: Add default setting PSP_INIT_ESPIZheng Bao
The board needs this setting to boot. Change-Id: I7f507c2478b63daf891430e95b008747b9b95a51 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-22soc/amd/mendocino: Unmap hash table after usageKarthikeyan Ramasubramanian
Earlier the entire SPI ROM is mapped at the start of verstage and then unmapped at the end of verstage. With CB:74606, this behavior has changed. So unmap the hash table CBFS file after usage. BUG=b:240664755 TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and suspend/resume cycles for 50 iterations each. Ensured that there is no impact to boot time. Change-Id: I5c605f8ba8bbd571b589b3cdf91e9cc71d711c1c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75092 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22soc/amd/common/psp_verstage: Map/unmap boot device on need basisKarthikeyan Ramasubramanian
Currently the SPI ROM is mapped completely when the boot device is initialized. That mapping remains active throughout the execution time of PSP verstage. Every 1 MiB of mapped SPI ROM region consumes 1 TLB Slot in PSP for use during memory mapped or DMA access. With 16 MiB of mapped SPI ROM + FCH devices + 4 reserved TLB slots, 31 out of 32 total TLB slots is consumed. This leaves almost no scope for future expansion. With upcoming programs possibly using 32 MiB SPI ROM, PSP will run out of TLB slots to support 32 MiB. Hence instead of mapping the entire SPI ROM upfront, get the SPI ROM SMN address during the boot device initialization. Update the boot device region operations to map and unmap the SPI flash with the desired offset and size using the SVC call. Then anytime a memory mapped SPI ROM access is performed: map the required area, read the data and immediately unmap the area. There is no update required when using CCP DMA, since the concerned SVC call performs mapping and unmapping of the required SPI flash area implicitly. With these changes, maximum of 8 slots(size of RO section) might get used at any point in time during the PSP verstage execution. BUG=b:240664755 TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and suspend/resume cycles for 50 iterations each. Ensured that there is no impact to boot time. Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74606 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training errorShelly Chang
Add sending Meta's BMC SEL for memory training error occurred in EWL type 3 error. The detail definition of EWL (Enhanced Warning Log) can be found in the specification document -- BIOS Data ACPI Table (BDAT) Interface Specification v4.0 Draft 5: https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%20Draft5_0.pdf Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69147 Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/system76/rpl: Add Gazelle 18Tim Crawford
The Gazelle 18 (gaze18) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots - M.2 NVMe SSD slot - M.2 SATA SSD slot - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.6 Not working: - Discrete/Hybrid graphics Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-05-22soc/amd/common/psp_verstage: Always build unsigned PSP verstageKarthikeyan Ramasubramanian
Currently unsigned PSP verstage binary is copied from ELF file only when required in amdfw*.rom. If a signed PSP verstage binary is supplied while building amdfw*.rom, then it is dropped. Copy the unsigned PSP verstage binary always so that it can be used for signing directly from the CI build infrastructure instead of a locally built binary. BUG=None TEST=Build Skyrim BIOS image and ensure that the unsigned PSP verstage is part of the build artifacts. Change-Id: If797dcfd20aa2991f3517904ef862406b9b9875c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75334 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/google/nissa/var/pujjo: Add WWAN_5G power on sequenceLeo Chou
Pujjoteen5 support WWAN 5G device, use variant.c to handle the power on sequence. BUG=b:279835626 TEST=Build and check WWAN 5G power on sequence. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I7dc72f2c705bcb41745f4bf08bef286773fe8b13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75327 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/google/nissa/var/yavilla: Config I2C frequencyTony Huang
Measured the I2C frequency meets spec 1. I2C0 (TPM): 976.1 Khz 2. I2C1 (TouchScreen); 394.0 Khz 3. I2C2 (WCAM); 377.9 Khz 4. I2C3 (Audio): 390.0 Khz 5. I2C5 (Touchpad): 389.3 Khz BUG=b:283374537 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and check all I2C devices measurement result Change-Id: If6e3a4a2b1ac642561015a290e6579238c3c2b1b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-22mb/google/skyrim: Enable DmaProperty on WLAN deviceMark Hasemeyer
Set the DmaProperty in the device's _DSD so that the OS can treat the device as untrusted. BUG=b:278310256 TEST=cat /sys/bus/pci/devices/<wifi>/untrusted == 1 iperf3 -c <iperf3-server> -t 60 (No performance regressions seen) Change-Id: I06369a19afa5b881b26f5c1eb243e2db41a9bb36 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75095 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-22soc/intel/common: Add an error for missing ramtop CMOS entrySean Rhodes
Show an error if an option table is used, and the ramtop entry is not defined on a platform that uses it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie48f0766b29be8e1fb0c1f71c4b2ce6ed20e6207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-22lib/ubsan.c: Restore Jonas' copyrightMartin Roth
During the cleanup of copyright lines, this file was incorrectly changed to remove the copyright line. It is not originally a part of the coreboot project, having been pulled in and adapted for use in coreboot. As such, and with the ISC license specifying that the copyright line should be maintained, the copyright line has been restored. See coreboot ticket # 479 for more information. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia234cebd0a6d49d03e40c5a57cd346a07f3e4b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-22mb/msi/ms7d25: Re-enable GpioOverrideMichał Żygowski
Set all GPIOs to their target functions and do not depend on FSP to configure them. The board support has stabilized and was tested with many PCIe devices. There is no need to detect CLKREQ signals so we may hardcode them. TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock PM features' state on PCIe root ports are the same before and after the change. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I01dc83ce23ca27525b8905665da942510f249824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22mb/google/corsola: Disable backlight before turning on bridgeRuihai Zhou
Disable backlight before turning on bridge, otherwise the bridge will initialize failed. Fixes: d5c1e1(mb/google/corsola: Add support for MIPI panel) Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I7d10bf9e8675b2fb03bfd1e294af66207b9b0620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75354 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-05-22mb/google/rex/var/screebo: enable fingerprintSimon Zhou
BUG=b:278156430 TEST=verify the fingerprint on screebo Change-Id: I986e470b28145f7b17427e794055929a4283c721 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-22mb/google/hatch/jinlon: Add HID to gfx ACPI nodeKornel Dulęba
The upstream kernel privacy screen driver uses HID GOOG0010 to look for firmware node to use. This method is used on other boards, e.g. redrix. See: drivers/platform/chrome/chromeos_privacy_screen.c in linux sources. Update jinlon gfx ACPI node to work with that. BUG=b:279092050 TEST=privacy protection screen works with 5.15 and 4.19 kernels Change-Id: Icba41e7f2be7292f713fea10dbe69b3ca128bde7 Signed-off-by: Kornel Dulęba <korneld@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75289 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-22mb/google/nissa/var/yavilla: Disable unused gpio with fw_configRobert Chen
Disable unused gpio for LTE daughter board, WFC and stylus. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc61321cd96a10dd34ff6cd9fcabe85a64bbfa9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75293 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/msi/ms7d25: Disable PCIe hotplugMichał Żygowski
The support for the board has stabilized and PCIe ports have been tested with many devices. Although hotplug is not commonly used and it seems pointless to keep it enabled, so disable it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I338c55cb57d971badd08235b71626a710fafb829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21drivers/emulation/qemu/bochs: Fix the MMIO access to the VGA ioportsBin Meng
The Bochs graphics adapter remaps the legacy VGA ioports (0x3c0 -> 0x3df) to its MMIO region at offsets 0400 - 041f. Currently bochs_vga_write() calculates a wrong offset when accessing these ioports, which causes the boot splash image not displayed when using the legacy-free pci variant of the Bochs graphics adapter. TEST=Build coreboot for QEMU x86 i440fx with a boot splash image included, boot coreboot.rom with QEMU with '-device secondary-vga' and verify the boot splash image is correctly displayed. Fixes: efaf1b32ba1e ("drivers/emulation/qemu/bochs: Rewrite driver") Signed-off-by: Bin Meng <bmeng@tinylab.org> Change-Id: I4acc71e3d6ef5161ab62e6714c94b7643c4c0972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75146 Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21Kconfig: Get rid of named choice LAPIC_ACCESS_MODEMartin Roth
The named choice isn't needed here, so get rid of it. This fixes the build notice: build/auto.conf:notice: override:reassigning to symbol LAPIC_ACCESS_MODE Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I70628007319a0ee2830dc4c9cb3b635d8190264b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75133 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-21mb/lenovo/x200: Add VBT files by defaultNico Huber
Select INTEL_GMA_HAVE_VBT so VBT files are added by default. This board has two specific VBT files that are hard-coded in the Makefile. Hence set an empty INTEL_GMA_VBT_FILE string. Change-Id: I0508c8016da06b401d6fbefd6e5cec1af018a5c8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21nb/intel/gm45/gma: Fix debug note about missing panel dataNico Huber
Reformat the string, fix whitespace, add single-quote before genitive `s`, and correct the GPU tool name `intel_reg`. Change-Id: I277603063806927837867a454ae0875578228109 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21nb/intel/gm45/gma: Centralize call to gm45_get_lvds_edid_str()Nico Huber
There is only a single place where we need the LVDS EDID string. Let's call gm45_get_lvds_edid_str() right there. This simplifies the API and helps to follow the execution flow. The function is moved to avoid a forward declaration. Change-Id: I86f3a88e6b661bcf60319edbe301e70304924727 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21nb/intel/gm45/gma: Use res2mmio() directly for GTT accessNico Huber
This is how res2mmio() is supposed to be used and there was no other use of the `mmio` variable left anyway. Change-Id: Ifa4645bcc9ae971966587d9b67662b9dc8bae3d0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21nb/intel/gm45/gma: Probe PCI resource once and firstNico Huber
The PCI resource should only be probed as part of the device .init process. We can simply do that first and know that we can use the global `gtt_res` from then on. This simplifies the signature of gm45_get_lvds_edid_str(), and makes changes to the API user (lenovo/x200) necessary. Change-Id: I6c96f715abfa56dcb1cd89fde0fbaef3f1cb63ae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21soc/intel/meteorlake: Add `.final` to check FSP reset pending requestSubrata Banik
This patch adds an API to check FSP reset pending requests. This information is useful to understand if FSP would like boot firmware to issue any reset to complete the silicon initialization. As per recent debug it has been found that, FSP is accumulating all platform resets and executing a single reset from FSP Notify Phase. As coreboot skipped calling into the FSP Notify APIs hence, it might have missed the scope to issue the platform reset. BUG=b:282266168 TEST=Able to build and boot google/rex and able to detect FSP reset pending request. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf7c996f09affa099c9124773fe2d581f370d1a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-20soc/intel/quark: Drop supportFelix Singer
As announced in the 4.20 release notes, support for the Intel Quark SoC is moved to the 4.20 branch and dropped from master. Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-20mb/intel/galileo: Drop supportFelix Singer
As announced in the 4.20 release notes, support for the Intel Galileo mainboard is moved to the 4.20 branch and dropped from master. Change-Id: I132adf2782721738c954252665fdcd7bb8e1a1cd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-19soc/intel/common: Correct the check for ramtop lengthSean Rhodes
The `ramtop_table` is 10 bytes long, so adjust the check to account for this. Also, adjust the wording to make it clear what is required to fix it, should the error be shown. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2898c4bb22abb1779035aadc08f32898e9a096b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19mb/google/nissa/var/yaviks: Generate LP5 RAM ID for K3KL6L60GM-MGCTWisley Chen
Generate the RAM ID for Samsung K3KL6L60GM-MGCT. DRAM Part Name ID to assign K3KL6L60GM-MGCT 6 (0110) BUG=b:281928906 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia5193d3ab3d654f25d519ad9a954f2ca8a15a978 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75152 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@google.com>
2023-05-19mb/google/brya/acpi: Update GC6 sequencesEran Mitrani
GC6 - Low power mode for system idle on Nvidia GPU In GC6I Before ramp of PEXVDD: Deassert FBVDDQ Enable, no delay is needed before or after. In GC6O After ramp of PEXVDD: Assert FBVDDQ Enable, no delay is needed before or after. BUG=b:280467267 TEST=built for Hades and Agah, tested on Agah Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I0277772b1d2f6f4e6a3f74b92035e8b36f2670ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/75302 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19mb/google/rex: Enable stylus supportDinesh Gehlot
This patch enables stylus support by configuring the "GPP_D08" irqs for rex SoC. This allows the SoC to detect a stylus device, when in use. However stylus is not a wake up source for the rex. BUG=b:282256460 Test=Stylus is detected on proto1 device. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19soc/intel/jasperlake: Add PsysPmax configChia-Ling Hou
Enable PSYS capability. PSYS is required to safeguard the system stability if no charger IC. BUG=b:281479111 TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196 Reviewed-by: Reka Norman <rekanorman@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19soc/intel/meteorlake: Add igd deviceWon Chung
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in SSDT. BUG=b:277629750 TEST=emerge-rex coreboot then check SSDT on DUT Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id7a136b5234cf5c0f60ecf253ee78c123f1f573b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19nb/intel/i440bx: Roll sdram_set_spd_registers() into parentKeith Hui
Being a static function, compiler is already putting its contents in sdram_initialize(), its only caller. Change-Id: Ie74d2283ef672a267d6a0c66d94aa0610f36c4f1 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74033 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19nb/intel/i440bx: Compact debug messagesKeith Hui
With RAM init debug messages enabled, debug messages take up a lot of flash space in romstage, with many repeated verbiage. By breaking them up and factoring out the common verbiage, made possible with printk(BIOS_DEBUG, "%s", ...), compiler can help deduplicate things and make the romstage smaller. When building for asus/p2b-ls with CONFIG_DEBUG_RAM_SETUP, this patch shrunk romstage by 152 bytes. Change-Id: I66e39e7901efbeb5ab72494ac02fc4d5e687c3a3 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-19device/Kconfig: Reduce PCIe hotplug bus numbers and IO resourcesArthur Heymans
The rationale behind this change is that multiple nested bridges using a lot of bus numbers and IO resources is not likely to be a common hotplug setup. When there is a large amount of hotplug ports using 32 subordinate busses results in boot failures (e.g. make qemu). 8K IO busses for hotplug devices is also excessive in most use cases when only 64K is available in total (again make qemu results in failure to allocate resources but does boot to payload). Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I8371958037d479e7d2053f49814735e15461ca6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74774 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-19soc/intel: Extend fsp_get_pch_reset_status() to all FSP APIsSubrata Banik
This patch drops the assert check around `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config to ensure `fsp_get_pch_reset_status()` can be used by all other FSP APIs to know the status of the pending reset. As per recent debug it has been found that, FSP is accumulating all platform resets and executing a single reset from FSP Notify Phase. As coreboot skipped calling into the FSP Notify APIs hence, it might have missed the scope to issue the platform reset. Going forward coreboot needs to implement the corresponding logic to be able to identify any pending platform reset request and execute to complete the silicon initialization flow. BUG=b:282266168 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2c9e37fadc27eab820a3121e47e09529de34d10e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75309 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-18vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoCFelix Held
Phoenix has one more Type C port and two more USB2 ports which are used as the legacy USB part of the two USB4 ports. The USB struct version numbers have also changed, since it's a newer and incompatible version of that struct. TEST=After changing FSP to not hard-code the USB PHY config, but use the configuration provided by coreboot, and applying this patch, the USB connector on the USB2 port 4 lines works. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If52934595dd612154b97e7b90dbd96243146017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-18cpu/qemu-x86/cache_as_ram_bootblock: drop duplicated post codeAlexander Goncharov
Before the bootblock stage starts setting up the CAR mode, it sends `POST_BOOTBLOCK_CAR` POST code. However, before the definition for `POST_BOOTBLOCK_CAR` was introduced in the commit 0d34a50a360228138ade623e799b03eaba83b0a5 , the value `0x20` was used. At that point, `0x20` means "entry into CAR mode" and `0x21` means "the cache memory region is cleared". Right now we are sending the same POST code twice, which makes no sense. So we can do the following (todo: drop me after we decided which one is more appropriate): 1) Drop it (current patchset does exactly that) 2) Introduce POST code similar to POST_SOC_CLEARING_CAR and use it before the cache memory region is cleared. Change-Id: I5d9014c788abdf5a4338c9e199138d1e514450b3 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-18mb/amd/birman: Don't select the console UART, default to yMartin Roth
Things with prompts should not use selects, but should instead default to y. If there's a reason they need to be selected, they should be able to be hidden when they're selected. This isn't one of those cases where a select is needed, so set the default to y instead. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6de339c3a1ceb3cd71008402bba49b5efc4af3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-05-18Myst: Update Makefile to remove SPD injectionMartin Roth
The SPD format in the APCB has changed for Phoenix, and the injection tool 'apcbtool' needs to be updated to match. Until this happens, the APCB will be built containing the correct SPD. BUG=b:281983434 TEST=Build Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If575f98511c796e93c5a12cd450a3a7985e39806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-17nb/intel/i440bx: Clear memory errors before ending raminitKeith Hui
i440BX datasheet says all memory errors reported during RAM init should be ignored. Do as it says. Change-Id: Iaf85fde813aa083ae62218a2df5aec303e3c9f8c Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73952 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17nb/intel/i440bx, mb/asus/p3b-f: Abolish disable_spd()Keith Hui
This hook is specifically for asus/p3b-f so its mainboard code has a chance to put SPD away after RAM init completes. What it intends to do is done when GPO gets programmed in ramstage (and it's safe to do so), and no other board needs this hook, so drop it. Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-17acpi: Warn on timeout in write_delay_until()Cliff Huang
Make ACPI code print a debug warning message when a timeout is detected in a loop waiting for a condition. This timeout message won't be displayed when this function is used as delay loop (ie. without checking variable condition). The following is required to get this log in kernel log buffer: echo 1 > /sys/module/acpi/parameters/aml_debug_output Here is an example of generated code when waiting for variable L23E to be 0. Local7 = 0x08 While ((Local7 > Zero)) { If ((L23E == Zero)) { Break } Sleep (0x10) Local7-- If ((Local7 == Zero)) { Debug = "WARN: Wait loop timeout for variable L23E" } } BRANCH=firmware-brya-14505.B TEST=Boot to OS and check that the Debug print is added to the function. Change-Id: I3843e51988527e99822017d1b5f653ff2eaa7958 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73348 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-17mb/google/nissa/var/pujjo: Add GPIO setting for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, add GPIO setting for WWAN 5G device BUG=b:281943398 TEST=Build and check serial log Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ie2e0ea34c54a453645d626f892f50654ef5064ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75195 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17mb/google/nissa/var/pujjo: Enable PCIe port 3 for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, enable PCIe port 3 for WWAN 5G device BUG=b:281943398 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6d2e8eaecae968ed51095d9497beab492ba7e0c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-17mb/google/brya/variants/hades: Set up internal pull-up for GPIOsEran Mitrani
BUG=b:280843816 TEST=builds Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I55a85335a34eee227abb6ff355719f7ca2cbf04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-17console: Add format-checking __printf() to die()Nico Huber
Code changes are necessary because `-Wformat` warns about empty format strings by default. Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17soc/intel/xeon_sp/spr: Fix format specifier for __LINE__ (%d)Nico Huber
Change-Id: I1384a02fa2931002ddd629acef0a4368435cfeb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17ec/google/chromeec/ACPI: Set TBMC status based on motion sensor presenceMatt DeVillier
Use ECRAM field MTNS to determine if motion sensor present, and set TBMC device status accordingly. TEST=build/boot google/{jinlon,drobit}, verify ACPI status for TMBC correct for both devices with and without tablet mode. Change-Id: Ic06ab6d721f0a3435e6dfd7b5e130f378096afec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-17mb/google/volteer: Use FW_CONFIG to determine correct SOF audio profileMatt DeVillier
Use AUDIO PROBE to determine speaker amp config, set SOF driver profile accordingly. TEST=build/boot Win11 on Delbin and Drobit, verify correct audio profile selected, drivers loaded and functional. Change-Id: I13d787cb5ccb74d2774151ccd5deeb45b3364319 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-17drivers/sof: Add support for max98373a using port SSP2Matt DeVillier
Some devices using the MAX98373a smart amp have the speakers connected to port SSP2 vs the default SSP1, so add a configuration item to be able to specify that. TEST=tested with rest of patch train Change-Id: I11d8011c54946aa72a83c73fa88456b4bb5d7d95 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75231 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17drivers/sof: Use topology enums where appropriateMatt DeVillier
Also correct switch intendation, remove excess empty lines. Change-Id: I86026e7f6c0c1c7f3dc6a473bb3afe2f6d32a247 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75230 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-17soc/intel/common: Don't hardcode ramtop offsetSean Rhodes
The `ramtop` can be obtained from the `option.h`, so remove the hardcoded value. Keep the check for the value being byte aligned. Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74511 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-17soc/intel/alderlake: Handle FSP logo paramsSubrata Banik
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I421da2b4dadb892f17a859ce0ec586a2880469eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/75294 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17soc/intel/meteorlake: Handle FSP logo paramsSubrata Banik
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting Intel Meteor Lake RVP with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaba187456dd4dfb2f69d3532e83a3850f31783ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/75198 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16cpu/amd/pi/00730f01/Kconfig: use hexadecimal CPU number in ACPIFelix Held
To match the rest of coreboot, also change this ACPI_CPU_STRING Kconfig setting to use hexadecimal CPU numbers for the ACPI CPU objects. Since this SoC has a maximum of 4 cores, this change will make no difference in the runtime behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58f9c4672f34de0defafc300d2d291f4ad6196ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/75251 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16soc/amd/*/Kconfig: change ACPI_CPU_STRING to use hexadecimal CPU numbersFelix Held
Both the AMD AGESA reference code and the default coreboot ACPI_CPU_STRING use hexadecimal numbers in the ACPI CPU object names, so change the ACPI_CPU_STRING format string in the both the Stoneyridge Kconfig and the common non-CAR AMD SoC config Kconfig which covers all other AMD SoCs in soc/amd. All platforms where the P state and C state SSDT from binaryPI (Stoneyridge) or FSP (Picasso) was used in coreboot before it got replaced by native code, had at most 8 cores/threads, so the mismatch never became apparent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d6822c5df01786ee541ce90734b75ed1a761fca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75250 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16ec/google/chromeec: Use host command APICaveh Jalali
Update the chromeec driver to use the EC host command API. Large blocks of repetitive code to set up EC calls are replaced with single function calls to perform the same operation. BUG=b:258126464 BRANCH=none TEST=booted on rex Change-Id: I0317405b1ed0c58568078133c17c8cfbc7c21d80 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73325 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16ec/google/chromeec: Add ec_cmd_api.h, update ec_commands.hCaveh Jalali
The new util/chromeos/update_ec_headers.sh utility is used to update ec_commands.h and introduce ec_cmd_api.h from the chrome EC repo. ec_cmd_api.h is a new file from the chrome EC repo which defines the API for communicating with the EC. It is a companion to the existing ec_commands.h by defining functions corresponding to EC host command opcodes and request/response struct definitions. See $EC/docs/ec-host-command-api.md for details. Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 3e35858003 ec: Add another #line directive The original include/ec_cmd_api.h version in the EC repo is: 59de61f2db zephyr: Add support for RNG devices BUG=b:258126464 BRANCH=none TEST=none Change-Id: I30f20e34d31b7e19cf03f65fefd58ae64eef1d41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16lib: Perform display init in normal boot mode if BMP_LOGO is setSubrata Banik
Traditionally, display init during vboot "verified/secure/normal boot mode" relies on the VB2_CONTEXT_DISPLAY_INIT. This is the default behavior for vboot, meaning skip display init during verified boot mode. However, if the intention is to show the OEM splash screen (using BMP_LOGO config) during boot, then the policy enforced by vboot needs to be overridden. This can be done by setting the BMP_LOGO config flag. If BMP_LOGO is not enabled, then the vboot policy will be followed and display init will be skipped. This change was made to allow OEMs to show their splash screen during boot, even if the system is in verified/secure/normal mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice1f02ad5c02a6a7e74a97ed23c5f11c7ecfb594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75197 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16acpigen: Add printf-like function for debug stringCliff Huang
Generate formatted string and ACPI code to print debug string. For example (with pcie_rp = 1): acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp); generates the following ACPI code: Debug = "calling _ON for RP: 1" With this new function, the following functions are not needed anymore and therefore are removed by this patch. - acpigen_concatenate_string_string() - acpigen_concatenate_string_int() - acpigen_write_debug_concatenate_string_string() - acpigen_write_debug_concatenate_string_int() BRANCH=firmware-brya-14505.B TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot. Check the debug messages is in the kernel log when /sys/modules/acpi/parameters/aml_debug_output is set to '1'. Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16x86: pci_io_cfg: Make constant unsigned to fix out of bounds shiftPaul Menzel
Fix the error below when running a coreboot image built with `CONFIG_UBSAN=y`. PCI: pci_scan_bus for bus 00 shift out of bounds src/arch/x86/include/arch/pci_io_cfg.h:13:20 ubsan: unrecoverable error. GCC with `-fsanitize=shift` also flags this: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' So, make the constant unsigned. TEST=emulation/qemu-i440fx with `CONFIG_UBSAN=y` stops later with [ERROR] unaligned access src/lib/rmodule.c:152:27 [EMERG] ubsan: unrecoverable error. Change-Id: Ib05d225ab9f22078d765009b4ee6ef0c63231eed Found-by: UBSAN Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-16soc/intel/xeon_sp: Drop dummy FADT entryKyösti Mälkki
Specifying types without addresses for PM1B events is not useful. Change-Id: I839208eaecf689a32484b9154647fc66633e5eef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-15device/allocator: Fix format string for resource flags (%lu)Nico Huber
Change-Id: I56ffb82ec417530527ea1ea7e97a593e5bf6b756 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/google/brya/var/taniks: Update SOF speaker topologyMatt DeVillier
Taniks uses a 4-channel output config, rather than 2-channel. Update the SOF speaker topology accordingly. TEST=build/boot Win11 on taniks, verify speaker output functional. Change-Id: I3c08b12b11464dcada014289174e0cc468d1c39d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-15drivers/sof: Add support for max98357a with 4-ch outputMatt DeVillier
Will allow boards using this speaker configuration to correctly specify their output type. TEST=tested with rest of patch train Change-Id: Iefcfc928e2611f533af1a2962ec2761ec1b7bf3a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-15commonlib: compiler.h: Add __printf macroJeremy Compostella
This patch adds the `__printf' macro to comply with checkpatch following warning: Prefer __printf(1, 2) over __attribute__((format(printf, 1, 2))) BRANCH=firmware-brya-14505.B TEST=Successful compilation with `__printf(1, 2)' instead of `__attribute__((format(printf, 1, 2)))' Change-Id: Ic2d90478ab0955c2ad0955e8cff5be76bfb2e741 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75159 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/google/myst: Re-organize the FMAP layoutKarthikeyan Ramasubramanian
By moving certain FW UI assets from RO to RW sections, 4 MiB is sufficient for RO section. Split the resultant available 4 MiB equally between 2 RW sections. This will help in getting to 16 MiB SPI flash for the mainboard. BUG=b:281567816 TEST=Build Myst BIOS image with the updated layout. Cq-Depend: chromium:4519688 Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-15mb/msi/ms7d25: Update USB port macrosMichał Żygowski
Update USB port macros: - change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1, HUB to USB 2.0 headers, HUB to rear USB 2.0 - change USB type C header to LONG which caused hard lockups on the port making it unable to enumerate in UEFI Payload and Linux - add empty definitions for USBr ports Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbiSheng-Liang Pan
copy from dibbi since taranza base on dibbi,this is only for first initial configuration, will update the more setting afterward. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-05-15mb/google/dedede/var/taranza: Generate SPD ID for supported partsSheng-Liang Pan
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14acpi/acpigen: add comment about byte 0 in acpigen_resource_*wordFelix Held
Since it's not obvious, add comments to acpigen_resource_word, acpigen_resource_dword and acpigen_resource_qword to clarify out what the magic number in byte 0 means. The most significant bit of byte 0 indicates if it is a small or large resource data type. In the case of the MSB being 0, it's a small resource data type (aka type 0), and the other bits encode bit the type and size of the item; if the MSB is 1, it's a large resource data type (aka type 1), and the other bits just encode the type and there are two separate bytes to encode the size. Beware that the large resource's data type values in the ACPI specification don't include the MSB that's set, but only the 7 lower bits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-14arch/x86/ioapic.c: Increase the number of bits for ioapic IDArthur Heymans
In practice hardware can use larger numbers. Change-Id: I6e9ddd1ebd396c37e25eb3019f981d45d9c5e062 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-14mb/google/rex: Add variant specific SOC chip config update functionAnil Kumar
This patch adds support for variant specific chip config update similar to commit 061a93f93d2 ("mb/google/brya: Add variant specific soc chip config update"). Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-14mb/google/rex/var/screebo: Add initial devicetree configKun Liu
add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14mb/google/corsola: Add support for MIPI panelRuihai Zhou
The detachable Starmie will use MIPI panels, which require reading serializable data from the CBFS. So we add MIPI panel support to the display configuration and align the configuration sequence with the panels that use MIPI bridges. The PMIC Datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:275470328 BRANCH=corsola TEST=emerge-corsola coreboot chromeos-bootimage and display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-14mb/facebook/fbg1701/board_mboot.h: Remove config from mb_log_listFrans Hendriks
Error message ´Cannot map compressed file config without cbfs_cache' is reported. Compressed parts of CBFS can not be used during bootblock stage. Remove config from mb_log_list. Will be added to verified items by CB:74752. BUG=NA TEST=booting and verify log on facebook FBG1701 Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14mb/google/nissa/var/uldren: Add wifi sar tableDtrain Hsu
Add wifi sar table for uldren BUG=b:279679700 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e3d7a06beb673b204f2dfe8e7beb919730aa885 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-14screebo: fix the lp5ccc config from 0x55 to 0xaaSimon Zhou
BUG=b:278022971 TEST=verified on screebo Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 20:06:39 +0000