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Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus
variants) changed the GPE mappings to accomodate for WiFi wake
pin. However, this resulted in TPM interrupt pin being removed from
the GPIO to GPE mapping. Since we do not support true interrupts in
coreboot, GPE_STS registers are used to identify if an interrupt has
triggered. Change in GPE mapping resulted in this information to be
lost when talking to TPM thus resulting in "Timeout wait for tpm
irq".
This change fixes the above issue by assigning GPIO block for TPM
interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to
DW3. DW3 was mapped to NW_31_0 which only has debug header pins and
CNVI pins (none of them are used for reading GPE_STS or as wake
sources).
BUG=b:109824918
TEST=Verified that there are no "Timeout wait for tpm irq" messages
when talking to TPM.
Change-Id: I30768177a838a684948f7485d760c8b83c3190f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
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pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TPM over SPI/I2C config selection got changed in
https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the
same.
BUG=None
BRANCH=None
TEST=Build for Soraka & make sure that TPM is probed over I2C interface
rather than SPI.
Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26890
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since there are two cameras on Nami and only one camera on Sona.
We need to disable rear camera/DMIC on all Sona sku.
BUG=b:109710674
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Sona
Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Since there are two cameras on Nami and only one camera on Pantheon.
We need to disable rear camera/DMIC on all Pantheon sku.
BUG=b:109720689
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Pantheon
Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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As we suppress output now before console_init() is done, the log level
read at start of ramstage is always -1.
Change-Id: Ia078d647c47aaa41ca9f2df9cf8506148ef86538
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch moves uart, timer and cbmem code which can be reused into a
common directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch refactor cbmem and timer code which will be reused among
similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26881
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch fix whitespace and formating issues:
1. Using two spaces between code and single line comment.
2. No space after asterisk.
3. Fix checkpatch error.
4. Remove spaces after cast operators.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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TSEG can be used as a stage cache and SMM can be relocated here.
Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25593
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TSEG can be used as a stage cache and SMM can be relocated here.
Tested on Intel D945GCLF, still boots.
Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25592
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds a common function to decode the TSEG size from the ESMRAM
register. This will come in handy when SMM in TSEG is implemented.
This function is used both in romstage and in ramstage.
Change-Id: I4e163598752fb6cd036aec229fce439ebad74def
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23448
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Check whether device is enabled before calling smbios ops.
BUG=None
BRANCH=None
TEST=Build & boot Soraka.
Change-Id: I79681c10679e1de3a2d177503f29239968d0c157
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/26864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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For enable_resource & set_resource, use default DEVICE_NOOP so that they
are not reported as missing during enumeration.
BUG=None
BRANCH=None
TEST= Build & boot soraka.
Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/26869
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Update GPIOs in baseboard to match latest schematics:
1. Get rid of STEST GPIOs(GPIO_{62,84-89})
2. Get rid of SD_CD_ODL(GPIO_134)
3. Get rid of KB control GPIOs(GPIO_{144-146})
4. Configure GPIOs for pen eject (GPIO_{144,145}). Additionally, fix the
configuration for other pen GPIOs.
BUG=b:109764138
Change-Id: I8e40dd90b2784596f055538e57ea67482c4c517a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26874
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These files are directly extracted from the vendor firmware.
Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path
to point to the mainboard dir and to select
INTEL_GMA_ADD_VBT_DATA_FILE by default.
Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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All boards except those with NO_RELOCATABLE_RAMSTAGE
or explicit select already had this feature built.
Change-Id: I838e12141243ec49c2555c09269e07476eb0cfad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Choose codepath as if ROMCC_IF_BUG_FIXED was set.
Change-Id: I74b4fe4a915b70f63ea018035381b64f53af3c7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Tested and working:
- Wi-Fi
- Ethernet
- WWAN ? (interface is created in linux, didn't actually test it, should work)
- Bluetooth
- Speakers
- Internal mic
- SD card reader
- Suspend and resume
- Keyboard, touchpad, trackpoint
- Fan
- Webcam
- 4 RAM slots
- All USB ports
- mSATA
- VGA ROM (FIXME: black screen after resume from s3)
- Native graphics initialization (FIXME: probably incorrect panel frequency, etc. in GRUB; in linux everything's fine incl. resume from s3)
- libgfxinit
- GRUB payload
- SeaBIOS payload
- Internal flashing using flashrom
Not tested yet:
- Fingerprint reader
- Colorimeter
- Smart card reader
- Docking station
- VGA output
- Optical disc drive
- Discrete graphics
TODO:
- Test BDC detection
Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/26136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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To flip the Kconfig default, flag some platforms with
NO_RELOCATABLE_RAMSTAGE.
Change-Id: I72c6d07e5a60789bbe0e068a0130d7e3bd07a1d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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With RELOCATABLE_RAMSTAGE, variables RAMBASE and RAMTOP
have no meaning any more.
Change-Id: I711fe98a399177c2d3cb2a9dcdefba61031fb76d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Chip sections must be covered by a PCI device.
Fixes chip_ops not being executed and TPM shows up in OS.
Change-Id: Id0ecd2f2f3e303f2228743369a8025b327bee61d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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When the normal termination is None, the standby termination is
none also as per Doc# 572688. So when termination is only needed in
standby, use the IOSSTATE setting that drives low/high via the
Tx mode instead.
Also disabled Speaker in Standby state to save power.
BUG=b:79874891, b:79982669
BRANCH=None
TEST=Compiled and flashed image on Bip. Checked that suspend_resume cycles
pass. Checked that bluetooth is functional on resume. On Yorp, checked
that speaker is functional after a suspend/resume cycle.
Change-Id: I6a3852548f944176a80feb32e9885b03b8af25db
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Issue observed on the board is: too many jack interrupts.
cat /proc/interrupts | grep da7219
58: 84292 15709 0 0 IO-APIC 58-fasteoi da7219-aad
Updated pad configuration for Jack IRQ pin to fix the issue.
BUG=b:109655907
TEST=Jack insertion & removal detection is working.
Change-Id: I41ef9d40325677b01ca94ec3215e7feded76dcc3
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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During measurement of signals during Elan touchscreen power on, saw
that the enable_gpio delay was not sufficient as there is a +1.5 ms
delay during power on. Adding more delay to take this into account.
BUG=b:78311818
BRANCH=None
TEST=probe power on signals to ensure meet timing requirements
Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Power off does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/power off.
BUG=b:78311818
BRANCH=None
TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled
Make sure delays are consistent with spec
Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Remove the last bits of building romstage with romcc.
Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Name i2c device structure based on that in devicetree.cb
Now log looks like:
I2C: 01:0a (WCOM Touchscreen)
I2C: 03:13 (Realtek RT5663)
I2C: 03:39 (SSM4567 Right Speaker Amp)
I2C: 03:3a (SSM4567 Left Speaker Amp)
BUG=None
BRANCH=None
TEST=Build & boot Soraka
Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/26830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I7d5843aada364b557e0618268ad48c650aa54d1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/i2c.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/gspi.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a glue layer between SOC and common block IPs in terms
of PCH. All common IP blocks now can be selected based on
SOC_INTEL_COMMON_PCH_BASE config option.
BUG=none
BRANCH=b:78109109
TEST=Build and boot Cannonlake RVP and EVE.
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch is intended to make Intel common PCH code based on
Gen-6 Sunrisepoint PCH (SPT).
All common PCH code blocks between Gen-6 till latest-PCH should be
part of soc/intel/common/pch/ directory.
A SoC Kconfig might select this option to include base PCH package
while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Now addition to that
SoC might only selects required base PCH block to include those
common IP block selections.
BUG=none
BRANCH=b:78109109
TEST=soc code can select PCH config option
Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change enables wake-over-wifi functionality for all octopus
variants by making the following changeS:
1. Configure GPIO_119 as SCI active-low
2. Update GPE0_DW1 to include the group that GPIO_119 falls under
3. Add wake property to wifi device
BUG=b:77224247
TEST=Verified that wake-over-wifi works on yorp.
Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds missing entries in PMC to GPIO route mapping for GLK.
BUG=b:77224247
Change-Id: I66cadaa23b8bd4518a199733c8fba81168e60323
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit
64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect
this.
BUG=b:77224247
Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Since Vayne added one more skuid 3A67, we need to disable rear
camera/DMIC for vayne skuid 3A67.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Vayne
Change-Id: I9131b4c41bf189829be4e7e6bfaf4a96765cfa15
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26855
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for APL and GLK.
Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for CNL.
Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical
`&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise
`&`.
Also fix off-by-one error with the bitmasks.
Change-Id: I7d7720121d4730254542372282f5561739e7214b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20808
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2cce52561d30e30e1c81752cd2a455e7211006eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
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There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.
Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on Google Peppy (Acer C720).
Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26793
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also removes some non-POSTCAR_STAGE functions, since those are unused
now.
Change-Id: I439bffbe39411186355d374eed7d5efd63fb02e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26792
Reviewed-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin.
Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This improve the following:
- Improve readability for clearing fixed MTRR's
- Compute PHYSMASK high during runtime
- Cache the whole ROM_SIZE instead of XIP_ROM_SIZE
Change-Id: Ifaed96b41fab973fa541de1c4f005d6f0af5254f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Prepare a common cache as ram for CPU's featuring a Non eviction mode
MSR.
Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26789
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26788
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This changes the following:
- compute amount variable MTRR's during runtime
- Wait for all CPU's to be in Wait for SIPI state after sending init
INIT IPI to all AP's
- compute the PHYSMASK high during runtime and preload it to the
MTRR_PHYS_MASK msr's
Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Split of the model_6ex cache as ram to support POSTCAR_STAGE, which is
also needed for future C_ENVIRONMENT_BOOTBLOCK.
When using POSTCAR_STAGE the p4-netburst/exit_car.S is using since it
is identical.
Change-Id: Ibe9f065fdf1d702b73333ea7bb32daca15ba1293
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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After FSP-S, a device on PCI function n will be function swapped
to function 0 if there is no device presnet on function 0.
It needs some modification for DT and causes mismatches between
software configuration and hardware schematic. This patch is
from d779605, which swaps the devfn of the first enabled device
in DT and function 0 resides in a PCI device.
BUG=b:80105785
BRANCH=None
TEST=Make sure the device is still enabled after coalescence with
device on bus 0 and w/o device on bus 0. Test with suspend
and resume and ensure it's consistent.
Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/26479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I08c28862cc66956bdcab6ac9362b3d50bb64e78f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ibe16242d98531ff8e8a696f571496c6f46ea964b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I6994b48b48fb7177b9ae32825dcd9af099b85410
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested on Lenovo T430:
The TPM is advertised through ACPI tables and the version can be
read using tpm_version, tcsd and tpm_tis.
Change-Id: I0b0c39e7aa1be4a479325d4b5eff5892a7e2f69f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This allows to lock down spi among other things
Mostly copied from bd82x6x.
Tested on Intel DG41WV with the MRC_CACHE driver write protecting the
mrc_cache region.
Change-Id: If9c3a6118f4586d51c093edec896c347ba904b8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Based on Nicola Corna's work.
This allows for CONFIG_CONSOLE_SPI_FLASH to be used, which writes the
console output to the SPI flash.
TESTED to still work in ramstage on x220 (correctly writes MRC CACHE),
the option CONFIG_CONSOLE_SPI_FLASH compiles for targets using the
common Intel SPI code (untested though).
Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: Id41279a1cdc7c68d3dcc44e238863f2f4a452499
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: Ia36b4ef7d66c50a044bc51f452ac8b7c7ff14323
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: I6db25850d46ea3a940ea2a6f263303d4b5304cb3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: Ifadb894f98ce60cf0778de7fbcec67d125e48fd6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: Ibf21100eb2232932ea52740bd5250319d3c9adfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: Idf47ea3b29c3fab7256d7a6722c7978594001d8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib47cc1ee617aae74a8cfbcb25c1d0c083196f417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I5ace69f9a624da9556a14c498a592305a3b1c89f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I0aefe25e3af61c747c06629e365b8e27459181aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ic501f5f9e8cd79774eb2a8d8902f01853d746470
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ia9ca055679c0332613afb2bb2ed86df165de3baf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I2829e4cb1445f8412f57da10fda6b92c92e56ea0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I9d35bc706b0daac1e234441c86286cb2957f89ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib06f771b6b50f2ad1af440c8019e8cca38d2a4f0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I490091e7dec5a46040e8ba7cd5cd6c244b017e30
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Id2622e473959dcf105bfeeaebddd582593a3c274
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ic334f65e5c27d4f773f81fc1c9e3df7d63d47a11
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I52fe5a67e6b914426943c3499904e0546c3ea623
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I958fe66655cc3c589ce6709b83c56a9472628324
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I335dda11d0c1ee58bd2728580c48c41cef574654
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Icc7d7fee38e41f4bfda685fd42bf504a788b440c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I750ec788b7526ee2a7aa803bffb93805cedfb2ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I8e21843e11498438e115f1f82f94f2944ae7a3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I3f85e2ef0682b808f6e99dc406bccb88badcb82c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iacbd72e1c60573f4bb5ffa40717141e9fbca01bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I0b0a09098bd4185ae36f1468ebc151e39668ee86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib7068f381971d1270b22cb03937f1e7fa30acb46
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I0a4b7d774db1b2b486f44bd7363555c15d464484
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I0458e4fe08e32daf0b880e0a29752297e8159fe6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I085a5b7dca252943590a30c1afe6ad776dac6c97
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I299c579c996da4e0e9fa1fc4d8b40706356509f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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