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2019-10-09soc/mediatek/mt8183: Change argument type of mt_set_emiYu-Ping Wu
Since struct dramc_param has been defined, we can pass the struct directly from mt_mem_init(). BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35846 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09soc/mediatek/mt8183: Run DRAM full calibrationHuayang Duan
Load the calibration params from flash first and check the correctness of the params. If the params have correct format, perform DRAM fast calibration with these params to reduce bootup time. Otherwise, load the DRAM blob and perform DRAM full calibration. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-09soc/mediatek/mt8183: Use cached calibration result for faster bootupHuayang Duan
Load calibration params from flash. If the format of the params is correct, use these calibration params for fast calibration to reduce the bootup time. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09soc/mediatek/mt8183: Add the shared 'dramc_param' moduleYu-Ping Wu
The dramc_param module simplifies the communication between coreboot and MTK DRAM full calibration blob, and is shared by both implementations to ensure the same format of parameters. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-09soc/mediatek/mt8183: Simplify usage of dramc_engine2_endYu-Ping Wu
Since we always write to &ch[chn].ao.dummy_rd after calling dramc_engine2_end(), this write could be merged into dramc_engine2_end() to simplify code. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35749 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstageArthur Heymans
This is now done during the romstage. Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-09mb/google/drallion: Enable UART console for arcada_cml and sarien_cmlBernardo Perez Priego
Drallion uses UART 0 for console, other two variants remain as UART 2. BUG=b:139095062 TEST=emerge-drallion coreboot chromeos-bootimage. Console should be visible. Change-Id: I520a07ad6f755bc2e6481329fc69bef9a36e31e2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35785 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09mb/google/hatch: Remove pen device for dratini/dragonairWisley Chen
Dratini/Dragonair doesn't support pen insertion/ejection feature, so remove it. BUG=b:142159117 TEST=emerge-hatch coreboot Change-Id: I64859a162d8dc75ffe55d98b72a056dd72e8de75 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-09mb/[google/intel/lenovo]/*: fix posix shell bug with SPD filesGreg V
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape in the same way bash/zsh do. As a result, the decoded files ended up with ASCII numbers instead of the decoded binary data. Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-09ec/google/chromeec: fix format security warningGreg V
Change-Id: I7a7bcb56523d595e8d4f32849aac53d66d416a12 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35866 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09drivers/spi: ignore -Wvla on clang tooGreg V
Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-09acpi_table_header: Replace hard-coded length via sizeof(acpi_fadt_t)Himanshu Sahdev
Minimize use of hard-coded value for acpi_table_header->length to soft code. Replace length of acpi_header_t with sizeof(acpi_fadt_t). Change-Id: Ibcae72e8f02497719fcd3f180838557e8e9abd38 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-09mb/google/hatch: Set FPS as wake sourceShelley Chen
BUG=b:142131099 BRANCH=None TEST=powerd_dbus_suspend, ensure DUT in S0ix touch fp sensor and ensure DUT wakes up in S0 Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-09SMBIOS (Type 17): Add HBM device type and DIE form factor valueElyes HAOUAS
Add High Bandwidth Memory, High Bandwidth Memory Generation 2 and new form factor value (Die). Change-Id: Ia174e09bffdadeed4a18d443f75e2386d756e9bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35893 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09SMBIOS: (Type 9) Add PCI Express Gen 4 valuesElyes HAOUAS
Change-Id: I616a435d80715bee6f7530d7318319556a7580e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-08superio/it8772f: use pnp_ops.h for pnp register accessFelix Held
Change-Id: I983249fb54b6fbccc4339c955cb5041848b21cf8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08superio/winbond/w83627*: use hwm5_conf.h for HWM setupFelix Held
Change-Id: Id78042606f02e02035dc917d162d0c98c9de38a4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08intel/dcp847ske: use functions from hwm5_conf.h for HWM setupFelix Held
Change-Id: I67de5260a756fc7b1cf0ec1903bee0058a2dcb06 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08superio/it8772f: use HWM access functionality from hwm5_conf.hFelix Held
Change-Id: I12ac8dd0503f3c46fdb50e49df60c01387128b55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08superio/hwm5_conf: factor out HWM access from ITE env_ctrlFelix Held
Nuvoton and Winbond use the same off-by-5 indirect address space to access their hardware monitor/environment controller in the SIO chip, so move this to a common location and replace the inb/outb calls with the corresponding inline functions from device/pnp.h Change-Id: I20606313d0cc9cf74be7dca30bc4550059125fe1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08asus/f2a85m_pro: Fix superio type in devicetreeKyösti Mälkki
The superio driver that was linked in is nct6779d but static devicetree expected symbol superio_nuvoton_nct5572d_ops. Change-Id: I648b7680bb39b9ff5b38cc3bd5147bd336e0b282 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-08device: Use scan_static_bus() over scan_lpc_bus()Nico Huber
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08device/root_device: Consolidate common _scan_bus() functionsNico Huber
scan_usb_bus() and root_dev_scan_bus() had the very same implementation. So rename the latter to scan_static_bus() and use that for both cases. Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08arch/x86: Don't allow separate verstage to boot from romcc bootblockArthur Heymans
CONFIG_VBOOT_SEPARATE_VERSTAGE has a dependency on C_ENVIRONMENT_BOOTBLOCK so Kconfig already guards against this. Change-Id: I8f963a27f9023fd4c6ebc418059d57e00e4dfb4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35824 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08arch/x86: Add a choice for selecting normal/fallback cbfs prefixArthur Heymans
Setting the cbfs prefix is prone to error. Therefore add a Kconfig choice for 2 common values, fallback and normal, while still keeping the ability to specify an arbitrary value. Change-Id: I04222120bd1241c3b0996afa27dcc35ac42fbbc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-08device/dram/ddr4: Check spd_bytes_total and spd_bytes_used valuesElyes HAOUAS
The value stored to 'spd_bytes_total' is never read. Now it is fixed. This is spotted using clang-tool v9. Also add a check if spd_bytes_used and/or spd_bytes_total are reserved and make sure that spd_bytes_used is not greater than spd_bytes_total. Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-08mb/lenovo/t60: Switch to override treePeter Lemenkov
Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34779 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08mb/lenovo/{t60,z61t}: Convert to variant boardPeter Lemenkov
Change-Id: I0a3076780ac5cf183235f06e4c56d0707bf5e6ca Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-08device/mmio.h: Add more bit field helpersHung-Te Lin
For fields with single bit, it's easier to declare as DEFINE_BIT(name, bit) Change-Id: If20e6b1809073b2c0dc84190edc25b207bf332b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2019-10-08mb/google/drallion: Add detect pin for Wacom touchscreenFrank Wu
Add the missing detect pin to fix Wacom touchscreen function. BUG=b:140415892,b:138082886 BRANCH=N/A TEST=N/A Change-Id: I8a1b48d4d502945b88e38393383512d30b684fa4 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35790 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08mb/google/kohaku: Assign GPP_A19 as reset_gpio of stylusSeunghwan Kim
Applying reset_gpio config of stylus for kohaku. GPP_A19 has been assigned in the latest schematics. We would keep GPP_A10 as output high for old revision devices temporarily. BUG=b:141914474 BRANCH=none TEST=verified stylus works internally Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b Reviewed-on: https://review.coreboot.org/c/coreboot/+/35748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-07mb/google/hatch: Preserve MRC training data across FW updateShelley Chen
Add PRESERVE to UNIFIED_MRC_CACHE so that we don't retain the memory training data upon a FW update unless we need to. We have had users complaining that a 15 second memory training upon update makes them believe that their device is not booting, thus many of them hard resetting before bootup. BUG=b:142084637 BRANCH=None TEST=flash RW_SECTION_A, RW_SECTION_B, and WP_RO sections and make sure memory training doesn't occur on following bootup. Change-Id: Ia5eb228b1f665a8371982544723dab3dfc40d401 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-07mb/google/octopus/variants/fleex: Adjust I2C0 CLK to meet specJohn Su
After adjustment on Grob360S I2C0 CLK: 389.9 KHz BUG=b:141729962 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage measure by scope with Grob360S. Change-Id: I6a30257b7978cc8899a55f9fd6ffffe01cb2a851 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-10-07src: Capitalize Super I/OElyes HAOUAS
Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-07device: Rename scan_static_bus() -> enable_static_devices()Nico Huber
The new name should reflect better what this function does, as that is only one specific step of the scanning. Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/nm10: Fix enabling HPETArthur Heymans
RCBA_HPTC needs to be read back to consistently enable HPET. This ought to fix raminit failing sometimes and SeaBIOS endlessly waiting for user input. TESTED on Intel D510MO, Fixes SeaBIOS waiting for input, without a timeout. Change-Id: I20a25fd97cd09fedb70469262c64d8d3828bb684 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35758 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06mb/ocp/monolake: Add GPIO table to initialize custom configsJingle Hsu
Add a GPIO table for Monolake to initialize GPIOs with custom board configurations. Tested on Monolake. Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-06device/pci: Enable full 16-bit VGA port i/o decodingNico Huber
So, the PCI to PCI bridge specification had a pitfall for us: Originally, when decoding i/o ports for legacy VGA cycles, bridges should only consider the 10 least significant bits of the port address. This means all VGA registers were aliased every 1024 ports! e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. However, it seems, we never reserved the aliased ports, resulting in silent conflicts we preallocated resources. We neither use much external VGA nor many i/o ports these days, so nobody noticed. To avoid this mess, a bridge control bit (VGA16) was introduced in 2003 to enable decoding of 16-bit port addresses. As older systems seem rather safe and well tested, and newer systems should support this bit, we'll use it if possible and only warn if not. With old (AGP era) hardware one will likely encounter a warning like this: found VGA at PCI: 06:00.0 A bridge on the path doesn't support 16-bit VGA decoding! This is not generally fatal, but makes unnoticed resource conflicts more likely. Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35516 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06cpu/intel/model_2065x/bootblock: Remove dead codeArthur Heymans
This codepath is never takes as it checks if the CPU is at least ivybridge. Change-Id: Id064385f0c8bb0b094714129df6d8ba36c87a307 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06mb/{lenovo/x201,packardbell/ms2290}: Remove unused ACPI symbolsArthur Heymans
Change-Id: I3a3174cf20cea60d8b2c4d0311a48ce9ffe1a8a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06nb/intel/nehalem: Don't run graphic init on S3 resumeArthur Heymans
The assumption is made that an ACPI aware an OS does not rely on firmware to initialize the display. TESTED on a Lenovo Thinkpad X201 with Linux 5.2, display still works after S3, more than 200ms in time saved (dropped from 411ms to 182ms in total in one test). Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-06nb/intel/nehalem: Move PCH init to sb/intel/ibexpeakArthur Heymans
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06nb/intel/nehalem: Move romstage boilerplate to a common locationArthur Heymans
Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks. Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06nb/intel/nehalem: Don't link walkcbfs.S in romstageArthur Heymans
Change-Id: I5bb0c38353d340cc5d356fba299a4460e3f5bddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35770 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/ibexpeak: Don't clear PMBASE regs in romstageArthur Heymans
X201 boots fine without it. Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35769 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/ibexpeak: Implement USB current settingsArthur Heymans
This is based on the sandybridge settings. The current lookup table comes from the x201 vendor lookup table. Tested: USB mouse and webcam still work and current registers are the same as before. USB IR are not but the code follows EDS instead of the register replay. Change-Id: Icea9673623a62e7039d5700100a2ee238478abd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35762 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06intel/ibexpeak boards: Remove undocumented reset defaults from RCBA replayArthur Heymans
The values read back in those ranges are identical before and after this change and the Lenovo Thinkpad X201 still boots fine. Change-Id: I406510e0573ac97003da7d97181abdfbfd2a872f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35760 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06intel/ibexpeak boards: Remove handled RCBA entries from replayArthur Heymans
The RCBA registers 0x3400-0x3500 are all handled elsewhere in the code, so no need to have a 'replay' of those. The remainder now consist of USB setup and undocumented bits that should likely not be touched at all. Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06sb/intel/ibexpeak: Fix enabling HPETArthur Heymans
RCBA_HPTC needs to be read back to properly work. This fixes SeaBIOS endlessly waiting for input instead of booting the default entry. Linux already fixes this itself. Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/ibexpeak: Implement PCH function disable in chip_opsArthur Heymans
This does the following: - implement a PCH disable function that will be called by the PCI drivers as part of their chip_ops - removes the iobp_x calls as those don't exist on ibexpeak - complete the devicetree with to be disabled PCI devices for the chip_ops to be called - Clean up some code copied from bd82x6x Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06nb/intel/nehalem: Remove bogus GT PM initArthur Heymans
This was simply copied from sandybridge/gma.c. All these registers read back 0xffffffff or 0 or don't respond to reads. Change-Id: I094e7caa889a3175477aa78b91545ca804d423c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35746 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06nb/intel/nehalem: Disable PEG and IGD based on devicetreeArthur Heymans
Tested on Thinkpad X201: PEG device hidden. Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35744 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06nb/nehalem: Remove bogus MCHBAR writesArthur Heymans
On these CPUs the MCHBAR window is 16KiB large. This code was just copied from SNB. Change-Id: I263cfc678a2eb8eeee8ab9157c749359064a9be8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06sb/intel/ibexpeak: Add CIR initializationArthur Heymans
This properly sets up the chipset initialization registers, instead of replaying an RCBA dump. The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI. TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3. Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06intel/fsp_broadwell_de: Rename from xx_DEV_FUNCKyösti Mälkki
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-05soc/intel/common/block/p2sb/p2sb: Add missing PCI IDsPatrick Rudolph
The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing. Add them to make sure that the BAR0 doesn't change when running PCI resource allocation. Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-05kontron/986lcd-m,roda/rk886ex: Drop secondary PCI resetKyösti Mälkki
The extra PCI bus RST# and 200ms delay there was workaround for custom add-on hardware. Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-05intel/i945,i82801gx: Refactor early PCI bridge resetKyösti Mälkki
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-05intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1Kyösti Mälkki
Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-05intel/fsp_baytrail: Rename from xx_DEV_FUNCKyösti Mälkki
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-05sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNCKyösti Mälkki
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-04acpi_table_header: Replace hard-coded revision via macro and functionHimanshu Sahdev
Minimize use of hard-coded value for acpi_table_header->revision to soft code. Replace with macro defined in arch/acpi.h for FADT and with the get_acpi_table_revision function for SSDT. Change-Id: I99e59afc1a87203499d2da6dedaedfa643ca7eac Signed-off-by: Sourabh Kashyap <Sourabhka@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35539 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04devicetree: Fix improper use of chip_operationsKyösti Mälkki
Auto-discoverable PCI devices do not require field .enable_dev of chip_operations to be set. They are matched with PCI drivers by the use of PCI vendor and device ID fields. The name given for the chip_operations struct must match the pathname the way it is present in the devicetree.cb files. If there was no match, util/sconfig would currently choose to use the empty weak declaration it creates in static.c file. Change-Id: I684a087a1f8ee4e1a5fd83450cd371fcfdbb6847 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-04soc/cavium/common/Makefile: Convert STACK_SIZE value to decimalElyes HAOUAS
STACK_SIZE value needs to be changed from hex to decimal, since -Wstack-usage doesn't recognize hexadecimal numbers anymore. Change-Id: I73606d347194af5de5882a3387a4a5db17f9d94b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04mb/intel/{galileo,wtm2}: Use macro instead of magic numberElyes HAOUAS
Change-Id: Ib8a08e9f854b2b0786c69943d6dbb66abe3ad4d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04mb/google/kukui: Extend FMAP to 8MB layoutHung-Te Lin
The SPI flash component requirement for Kukui family is 8M so we should update FMAP for that: - Add more comments for alignment and size recommendation. - Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M. - BOOTBLOCK: 32K->128K, aligned with other ARM boards. - Preserve RW_DDR_TRAINING for new calibration. - Reorder the sections for better alignment. - RW_MISC to contain RW sections that should be merged when creating AU image. BUG=b:134624821 TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin: # name start end size RW_LEGACY 00700000 00800000 00100000 RW_SHARED 006f7000 00700000 00009000 RW_UNUSED 006f8000 00700000 00008000 SHARED_DATA 006f7000 006f8000 00001000 RW_SECTION_B 00580000 006f7000 00177000 RW_FWID_B 006f6f00 006f7000 00000100 FW_MAIN_B 00582000 006f6f00 00174f00 VBLOCK_B 00580000 00582000 00002000 RW_MISC 00577000 00580000 00009000 RW_ELOG 0057f000 00580000 00001000 RW_DDR_TRAINING 0057d000 0057f000 00002000 RW_NVRAM 0057b000 0057d000 00002000 RW_VPD 00577000 0057b000 00004000 RW_SECTION_A 00400000 00577000 00177000 RW_FWID_A 00576f00 00577000 00000100 FW_MAIN_A 00402000 00576f00 00174f00 VBLOCK_A 00400000 00402000 00002000 WP_RO 00000000 00400000 00400000 RO_VPD 003f8000 00400000 00008000 RO_SECTION 00000000 003f8000 003f8000 RO_FRID 003f7f00 003f8000 00000100 GBB 003f5000 003f7f00 00002f00 COREBOOT 00021000 003f5000 003d4000 FMAP 00020000 00021000 00001000 BOOTBLOCK 00000000 00020000 00020000 Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-04mb/facebook/fbg1701: Remove ONBOARD_MICRON_MEMFrans Hendriks
ONBOARD_MICRON_MEM and ONBOARD_SAMSUNG_MEM are available. These are used to determine if Samsung or Micron onboard memory is assembled. This can not detected run-time. Choice is replaced by one config. Only oldest HW revision contains Samsung module, so set CONFIG_ONBOARD_SAMSUNG memory to default No. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 Change-Id: Id65e92bd4b8d4fe3a6b87dec9bf77e3a62e1be96 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04device/pci_device.c: Use verified boot to check opromFrans Hendriks
Before oprom is executed, no check is performed if rom passes verification. Add call to verified_boot_should_run_oprom() to verify the oprom. verified_boot_should_run_oprom() expects and rom address as input pointer. *rom is added as input parameter to should_run_oprom() which must be parsed to verified_boot_should_run_oprom().. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG1701 Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04soc/skl/vr_config: fix KBL-U GT3 detection bugMaxim Polyakov
Some VR parameter values for KBL-U with GT3 graphics are different from values for other CPUs in this series [1]. However, GT3 iGPU will never be detected, since the igd_id variable is compared with the LPC device PCI ID. The patch fixes this bug. [1] page 109, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006 Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04soc/skl/vr_config: fix GT Loadline for KBL-U/GT3Maxim Polyakov
According to the documentation[1], the Loadline in the unslased GT VR domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC). [1] page 109, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006 Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35781 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04src/pci_ids: add missing Intel Kaby Lake iGPU PCIIDsMaxim Polyakov
Adds missing Intel HD/Iris iGPU PCI IDs for Kaby Lake processors and updates the platform report for these devices. These changes are in accordance with the documentation: [*] page 10, Intel(R) Open Source HD Graphics and Intel Iris(TM) Plus Graphics for the 2016 - 2017 Intel Core(TM) Processors, Celeron(TM) Processors, and Pentium(TM) Processors based on the "Kaby Lake" Platform. Programmer's Reference Manual. Volume 4: Configurations. January 2017, Revision 1.0 Doc Ref # IHD-OS-KBL-Vol 4-1.17 [*] Linux kernel sources: include/drm/i915_pciids.h Change-Id: I1cd1e4ab82f756141f8f13edf1c17f726166dffb Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04src/pci_ids: add missing Intel Skylake iGPU PCIIDsMaxim Polyakov
Adds missing Intel HD/Iris iGPU PCI IDs for Skylake processors These changes are in accordance with the documentation: [*] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM) Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference Manual. Volume 4: Configurations. May 2016, Revision 1.0 Doc Ref # IHD-OS-SKL-Vol 4-05.16 Change-Id: I0ba6e58ec3916dceea00519ac5a51503573e8935 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35493 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04soc/skl/vr_config: set Iccmax_gt depends on CPU/GTMaxim Polyakov
According to the DC Current Specifications [1], the current limit for the graphical VR domain (Iccmax_gt) isn't same for different Kaby Lake S CPUs. This value should depend on the iGPU model and processor TDP: +---------------------+-----+------------+ | Segment | TDP | Icc_max GT | +---------------------+-----+------------+ | Dual Core GT2/GT1 | 35W | | | Dual Core GT2 | 51W | 48 A | | Dual Core GT1 | 54W | | +---------------------+-----+------------+ | Quad Core GT2 | 35W | 35 A | +---------------------+-----+------------+ | Quad Core GT2 | 65W | 45 A | | Quad Core GT2 K-SKU | 91W | | +---------------------+-----+------------+ This patch adds the remaining Iccmax_gt current limit values from the documentation [1]. [1] 7th Generation Intel(R) Processor Families for S Platforms and Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1, December 2018, Document Number: 335195-003 Change-Id: I19766e4f8fab6b48565b65ed4cf13efbc213e654 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04mb/facebook/fbg1701: Add measured boot supportFrans Hendriks
No support is available in mainboard. Add support to mainboard: - Add mb_log_list[] - Add routine mb_crtm() BUG=N/A TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701 Change-Id: I5120ffb6af0b41520056e1773f63b7b2f34a2460 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-10-04mb/facebook/fbg1701: Add verified boot tablesFrans Hendriks
The vendorcode for verified boot is uploaded, but not used by a mainboard. Add support to the mainboard for verified boot. The items to be verifed are placed in board_verified_boot.c BUG=N/A TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701 rev 0-2 Change-Id: I3ea0a95287977df0dea13e05acedd5406538a6ee Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33463 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04vendorcode/eltan/security/verified_boot: Add verified boot supportFrans Hendriks
Create verified boot support, which includes verifiication of bootblock. This feature use the vendorcode/eltan/security/lib. cbfs_locator is used to init the verified boot support. vendor_secure_prepare() and vendor_secure_locate() are used to preform the required action in each stage. The next lists will be used for verification: * bootblock_verify_list * postcar_verify_list * romstage_verify_list * ramstage_verify_list BUG=N/A TEST=Created binary and verify logging on Facebook FBG-1701 Change-Id: If6c1423b0b4a309cefb7fe7a29d5100ba289e0b4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04vendorcode/eltan/security/mboot: Add measured boot supportFrans Hendriks
Create measured boot. This feature uses the vendorcode/eltan/security/lib. Measure boot can work with and without Verified boot enabled. The function mb_measure() is starting point for the support. This function will be called by the common Verified boot code. BUG=N/A TEST=Created binary and verify logging on Facebook FBG-1701 Change-Id: I7f880a17e240515dd42d57383b5ddddf576985b0 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-04arch/x86/acpi: Add SSDT for QEMUPatrick Rudolph
Add a SSDT on qemu and place BOOT0000 inside it to allow testing the google firmware kernel module in qemu. Tested on Qemu Q35. Change-Id: Ibd1b2c2f4fc3db9ae8f338b0d53b2d00ea2c4190 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HIMANSHU SAHDEV <sahdev.himan@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-03cpu/intel/: Fix regression with smmrelocateKyösti Mälkki
Fix regression with commit d53fd70 intel/smm/gen1: Use smm_subregion(). The bitmask on SMRR register parameter was inverted for selected models. Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-03ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabledMartin Roth
Don't set a default bus type for the Chrome EC on x86. The platform must select the bus, typically LPC or ESPI. BUG=b:140055300 TEST=Build tested only Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-03mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPIMartin Roth
Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-03southbridge/intel: Add config option to validate firmware descriptorMathew King
Add new config option to validate the Intel firmware descriptor against the fmap layout. This will prevent a firmware descriptor from being used that could corrupt regions of the bootimage in certian circumstances. BUG=chromium:992215 TEST=Build firmware image with mismached decriptor and fmp Without VALIDATE_INTEL_DESCRIPTOR set firmware builds With VALIDATE_INTEL_DESCRIPTOR set error is shown with mismached regions Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03sb/intel/i82801gx: Use symbolic name for register, code reworkPetr Cvek
An original code had a wrong register address 0x27 for AHCI BAR. The value was aligned incidentally by the code specific of the pci_read_config32 function to the correct address 0x24. All 0x24 values in sata.c were changed to the symbolic name PCI_BASE_ADDRESS_5 and the code was optimized. An equivalent code was tested on a real hardware. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03mb/facebook/fbg1701/devicetree.cb: Use 64MB framebuffer sizeFrans Hendriks
Connected 4K monitor is not configured at max resolution. The framebuffer size is too small. Increase the framebuffer size to 64MB. This is sufficient for max configuration of 1 HDMI monitor combined with internal LCD panel. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMBFrans Hendriks
Add defines to have some more readable code for devcietree.cb. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03mb/facebook/fbg1701: Add mainboard_read_pcb_version()Frans Hendriks
PCB version is determined using inb() in actual code. Create function mainboard_read_pcb_version to read pcb version. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 Change-Id: I7c16627f468d84ca4ad2aab8bf9fb555f50dc23c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-03intel/fsp_baytrail: Drop some PCI scratchpad register definitionsKyösti Mälkki
These were unused and somewhat cryptic, assumed purpose was to store pre-CBMEM timestamps in various PCI config space locations. Change-Id: I074294446501d49a9bd3c823a2a794c33f443168 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02intel/quark: Drop xx_DEV_FUNCKyösti Mälkki
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02intel/skylake: Refactor IRQ assignmentsKyösti Mälkki
When creating the IRQ routing, referenced device and function number are always of the same PCI device. Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02intel/pci_devs: Regroup PCI xx_DEVID entriesKyösti Mälkki
Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02mb/google/drallion: Disable GBE in firmware for drallion variantsThejaswani Putta
BUG: None TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02intel/baytrail: Replace config_of(dev) with config_of_soc()Kyösti Mälkki
The function does not otherwise need dev. Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02mb/google/drallion: Dynamicly disable memory channelEric Lai
Disable memory channel by HW strap pin. Using for factory debug. BUG=b:139773082 BRANCH=N/A TEST=Rework HW strap pin and check /proc/mem_info Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02mediatek/mt8183: Rename fields of struct sdram_paramsYu-Ping Wu
Two fields of struct sdram_params are renamed for future CL of DRAM full calibration. Field 'impedance' is also removed. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02sb/intel/common/smihandler: Hook up smmstoreArthur Heymans
TESTED on Asus P5QC. Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameterMichael Niewöhner
Make the the FSP Parameter PchHdaVcType a devicetree setting and make use of it in the devicetrees of all boards that currently set it. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2019-10-01mediatek/mt8183: Allow modifying vcore voltageHsin-Hsiung Wang
Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be calibrated with different vcore voltages to get correct parameters. A new API is added to allow changing vcore voltage. BUG=b:80501386 BRANCH=none TEST=measure vcore voltage with multimeter Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-01mb/kontron/986lcd-m: Add gameport base allocation workaroundPetr Cvek
A missing definition of gameport base (PNP io 0x60) will cause an automatic address assignment during PCI/PNP enumeration, which won't obey limit 0x7ff. This will cause the enumeration to fail as other devices already have the values enabled. The symptoms are: not working USB, PS/2, garbled UART console, not working PCIe GPUs and crashes. Probably because of wrongly assigned IO ports. Example of log (shortened): Done reading resources. Setting resources... !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.0 1c * [0x0 - 0xfff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io !! Resource didn't fit !! aligned base 400 size 10 limit 2e7 40f needs to be <= 2e7 (limit) PCI: 00:1f.2 20 * [0x3080 - 0x308f] io !! Resource didn't fit !! ... ERROR: PCI: 00:02.0 14 io size: 0x0000000008 not assigned ... ERROR: PCI: 00:1f.2 10 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 14 io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 18 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 1c io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 20 io size: 0x0000000010 not assigned ... PCI: 00:1b.0 subsystem <- 8086/27d8 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/27d0 PCI: 00:1c.0 cmd <- 107 PCI: 00:1c.1 brids70c01mcu0PeC: 0 dV0i8s0immicrocode: upd10a00000y0025 x666600CPU physiaB 0 0 e k MTRR cheaeu60zeAttemfWaiting for 1st Sot AP: slot 1 apic_L0ecl0zsax a aInitiNntt kac:oIG0 Ua dUrSGSGL Ct0C07fintel_vga_int15_h VGA Option ROM wa7..Azalia0Azalia: codkAbCiPCI: 00:1c.0 init finished We can see the ports probably started to collide after the activation of 00:1c.0 device. A debug run with compiled SPEW shows the problem with enumeration: PCI: 00:1f.1 18 * [0x50b8 - 0x50bf] io PCI: 00:1f.2 10 * [0x50c0 - 0x50c7] io PCI: 00:1f.2 18 * [0x50c8 - 0x50cf] io PCI: 00:1f.1 14 * [0x50d0 - 0x50d3] io PCI: 00:1f.1 1c * [0x50d4 - 0x50d7] io PCI: 00:1f.2 14 * [0x50d8 - 0x50db] io PCI: 00:1f.2 1c * [0x50dc - 0x50df] io PNP: 002e.7 60 * [0x50e0 - 0x50e0] io <-- gameport base DOMAIN: 0000 io: base: 50e1 size: 40e1 align: 12 gran: 0 limit: 7ff done Notice a weird base for DOMAIN, along with the limit. Adding a definition of gameport (0x220) as a workaround fixes the problems. The gameport should be still disabled thanks to disable bits (W83627THF datasheet is little bit chaotic). I didn't find any info if the gameport is available on some pads of the motherboard. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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