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2020-02-28vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2052Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2052. Change-Id: Icb911418a6f8fe573b8d097b519c433e8ea6bd73 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-28mainboard/google/hatch/puff: Toggle on TetonGlacierModeEdward O'Callaghan
Leverage in Puff to avoid diskswap variants. Later this could become part of the baseboard definition and hatch diskswap variants migrated over to use it as well. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-28soc/intel/cannonlake: Plumb TetonGlacierMode into dtEdward O'Callaghan
The following plumbs through the enabling of Intel's TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives to be accessable via devicetree. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-28mainboard/google/hatch: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-28ec/google/chromeec: Introduce SKU_ID helpersEdward O'Callaghan
The following introduces helpers that, by default, accommodate a larger SKU id space. The following is the rational for that: Allow INT32_MAX SKU id encodings beyond UINT8_MAX. This allows for the SKU id to accommodate up to 4 bytes however we reserve the highest bit for SKU_UNKNOWN to be encoded. However, the legacy UINT8_MAX encoding is supported by leveraging the Kconfig by overriding it with the legacy max of 0xff. Follow ups migrate boards to this common framework. V.2: Fixup array size && drop sku_id SKU_UNKNOWN check and pass whatever is set to userspace as firmware doesn't care about the value. V.3: Use SPDX-License header. BUG=b:149348474 BRANCH=none TEST=tested on hatch. Change-Id: I805b25465a3b4ee3dc0cbda5feb9e9ea2493ff9e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-27mb/google/hatch/var/jinlon: Configure GPP_E0 as outputRajat Jain
Configure GPP_E0 as output for view angle management Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9 Signed-off-by: Rajat Jain <rajatja@google.com>. Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-27mb/google/dedede: configure ESPI IO decode range for chrome ECAamir Bohra
Configure below ESPI IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. Change-Id: I1e450d6e45242180de715746b9852634de2669c6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-27mb/google/dedede: Enable display supportAamir Bohra
1. Enable Internal Gfx device. 2. Configure DDI0 for EDP. 3. Configure HPD and DDC suppport for DDI1/DDI2. 4. Configure HPD GPIOs. TEST=Verify display on EDP panel in OS Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-27soc/intel/tigerlake: Add display related UPD configs for Jasper LakeAamir Bohra
TEST=Build dedede board Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-27soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela
Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-26mb/google/hatch: reflow commentPatrick Georgi
Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-26soc/intel/tigerlake: Integrate Legacy 8254 timer supportSubrata Banik
This patch overrides required FSP-S UPDs to enable 8254 timer support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected. TEST=Required to boot TianoCore payload. Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-26mb/intel/tglrvp: add Tiger Lake memory initialization supportSrinidhi N Kaushik
Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-26ec/purism/librem: fix topstar driver ERAM mappingMatt DeVillier
Correct the offset for the Topstar driver enable/disable bit, which was off by 2 bits compared to a dump of the AMI UEFI ACPI. This prevents the fan mode (FANM) from being inadvertently changed and hopefully fixes some intermittent issues with fan speed on resume from suspend. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Ibc3c39d5b14c753eed6d1ed8cbf161717f8d04e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39105 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26mainboard/hatch: Fix GPE wake commentsEdward O'Callaghan
The indirection of names is exceedingly confusing for ultimately the single interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on the PCH side. This helps folks chase this indirection down through the code. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-26mb/google/dedede: Update GPE configurationKarthikeyan Ramasubramanian
WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is routed to GPP_C12 GPIO. Update the GPE configuration accordingly. BUG=None TEST=Build the mainboard. Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26mb/google/dedede: Enable host bridge deviceAamir Bohra
Change-Id: Ie47265527b2b81748f4f3ad744d35cb81af17b80 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-26mb/google/fizz: allow 8 bit sku idsJeff Chase
Change-Id: I663678a4c572fe80298f7388870d5cd403122b98 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-02-26vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger LakeRonak Kanabar
Update FSP header file for Tiger Lake platform version 2457. Add SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-26soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resumeSubrata Banik
This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to avoid discrepancy between S0 and S3 resume flow. TEST=Able to boot to TianoCore without any hangs and errors, also verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD. Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25mb/hp: Set CBFS_SIZEPatrick Rudolph
Overwrite the default of 1 MiB with the actual bios region size set in the stock IFD. Allows to use payloads like TianoCore without manually touching the CBFS_SIZE. Change-Id: Ic1753a38212cc4961671fea11afe88265e73333b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39073 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/mediatek/mt8183: Fix programming error of DRAMC settingHuayang Duan
1. The ac timing of 2400Mbps should use diff params with 1600Mbps. 2. Fix the typo error of save shuffle function for DVFS. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I5edac32938def50836f386426e7deb652b80d42d Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-25include/stdint.h: Remove old reference to ROMCCElyes HAOUAS
Change-Id: I00fdcee177c5d4b5e95bc3d0330fd8934eee2f0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-02-25mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2Michael Niewöhner
Fix PNP warning about missing devicetree entry for SUART1/2 by setting register 0xF0 to a sane (default) value. Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-25superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHBMichael Niewöhner
The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB bridge's index/value interface. They are no one-time config registers so we can't specify a sane value in the devicetree. Thus, drop them to stop coreboot from complaining about the missing entries. Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-25mb/supermicro/x11-lga1151-series: fix GPIO reset mappingMichael Niewöhner
When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset value of 0x0 is only defined for GPD pads. For any other GPIOs this maps to 0x3. On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical to Chipset mapping not found". Set the right value (0x3<<30) for the affected GPIOs. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-25soc/mediatek: Fix typos in commentsElyes HAOUAS
Also add missing whitespace. Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-02-25lib/lzma: Fix out-of-bounds readAlex Rebert
Fix an out-of-bounds read in the LZMA decoder which happens when the src buffer is too small to contain the 13-byte LZMA header. Change-Id: Id5893e60fc9a48deb83560b7917f5558cd30ef4e Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-25soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath
Update Jasper Lake CPU, SA and PCH IDs. BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-25soc/intel/common/block: Move cse common functions into block/cseSubrata Banik
This patch cleans soc/intel/{cnl, icl, tgl} by moving common soc code into common/block/cse. Supported SoC can select existing HECI_DISABLE_USING_SMM option to select common cse code block to make heci function disable using sideband interface during SMM mode at preboot envionment. BUG=b:78109109 TEST=Able to make HECI disable in SMM mode successfully without any hang or errors in CNL, ICL and TGL platform. Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/intel/common/block: Move smihandler common functions into common codeSubrata Banik
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-25superio/aspeed/ast2400: rename SWAK to SWC to match the datasheetMichael Niewöhner
The datasheet uses "SWC" as shortcut for "System Wake-up Controller", thus rename it in the code. Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-25soc/intel/cannonlake: Add TDC config for CMLMarx Wang
Add Thermal Design Current (TDC) defaults for CML: 1. TdcEnable 2. TdcPowerLimit BUG=b:148912093 BRANCH=None TEST=build coreboot and Intel FSP with fw_debug enabled, flash image to the device, capture the log from the serial port during boot-up and check TdcEnable and TdcPowerLimit for each domain in captured log Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-25mb/amd/samba: Drop board leftoverElyes HAOUAS
lippert/hurricane-lx doesn't exist anymore (see Change-Id: I87e3963). Change-Id: I6d1c3a846c5bbb5fdc74178d0cf8a3cdaae1a010 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39076 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24include/arch/cpu.h: Remove old reference to ROMCCElyes HAOUAS
Change-Id: I17d13c53baf16f58e6e2ba45f439c36f7ba28690 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39071 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24cpu/Kconfig: Remove old reference to ROMCCElyes HAOUAS
Change-Id: I06425d8290a89e72a2420aeb6a9bc4b4acbaf498 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39070 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/inagua: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I55bf3004c728bb42ee51dfa917c58d97c56502cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38876 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Iad86755952204bb1a56ef341e626b0627a958467 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38868 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/elmex/pcm20540*: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I53b80fe97370c99968f073dfad61b5e5709e4ab6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38870 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/union_station: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0edfc7bb6d01eb1a12299fddd3d3ac45b43edfdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38875 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/lippert/frontrunner-af: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I63dd15ade28acb06da8d320edc8ae1fd433aa0e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/38877 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/south_station: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Iba1d020b9e565e3c6c89a97114084d72a00b2a55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38871 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38869 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/lippert/toucan-af: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I22774a6d6a32c2fb8340f5ac678befe0d5f8ad75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/parmer: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic3fda4e598af8df9c9ddc97f7eb7fdcdaff6580b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38879 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/amd/persimmon: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I51d42f137fa539225bca5631bec38144ffd4f1d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38873 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCKMike Banon
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ifb50fd22f5ef4db204a3427e03430177cad211cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38866 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24soc/intel/icelake: Skip FSP-S IGD related UPD overrideSubrata Banik
Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence related FSP-S UPD override can be avoided from coreboot. As per FSP-S UPD Header (FspsUpd.h) /** Offset 0x020E - GT Frequency Limit 0xFF: Auto(Default) **/ UINT8 GtFreqMax; /** Offset 0x0209 - CdClock Frequency selection 0: (Default) Auto **/ UINT8 CdClock; TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform. Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-24mb/intel/jasperlake_rvp: Disable SATA controllerUsha P
This patch disables the SATA config from devicetree for JSL RVP, since we are not planning to use the SATA storage in chrome config. Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-24device/Kconfig: select linear framebuffer for TianocoreMatt DeVillier
Automatically select the linear framebuffer mode option if available when Tianocore selected as payload, since VGA text mode will not work properly with the default Tianocore payload. Change-Id: Ic36fd035526f3efd00ffa12ad613fbac304b18cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-24soc/rockchip: Fix typosElyes HAOUAS
Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24src/commonlib: Fix typosElyes HAOUAS
Change-Id: Ida1770c5e4b18c536e4943eb9cf862d69196c589 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24soc/{samsung,sifive}: Fix typosElyes HAOUAS
Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-02-24soc/amd/common/block/include/amdblocks: Fix typosElyes HAOUAS
Change-Id: I8363816a51c342935668545a8b39acce96ce4b2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38980 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/google: Fix typosElyes HAOUAS
Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24mb/amd: Fix typosElyes HAOUAS
Change-Id: I9abc0837b72b13e7614ecffa5b21c3d4bf41d0f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24mainboard: Add missing include <device/pci_def.h>Mike Banon
Add missing include <device/pci_def.h> for the boards that are being switched away from ROMCC_BOOTBLOCK. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I83ff712f99388c4e6ea00a942eb57bcabb53a3fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38903 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24src: capitalize 'RAM'Elyes HAOUAS
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-24gfx: Move drivers/generic/gfx to drivers/gfx/genericFurquan Shaikh
This change creates gfx directory under drivers/ so that all drivers handling gfx devices can be located in the same place. In follow-up CLs, we will be adding another driver that handles gfx devices. This change also updates the names used within the driver from *generic_gfx* to *gfx_generic*. In addition to that, mainboard drallion using this driver is updated to match the correct path and Kconfig name. TEST=Verified that drallion still builds. Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-24vboot: remove rogue vboot_struct.h includeJoel Kitching
As part of vboot1 deprecation, remove an unused vboot_struct.h include. coreboot is now free of vboot1 data structure use. One vboot_api.h include remains as part of security/vboot/ec_sync.c. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I042d692aa252f8f859d4005455eb6a2eabc24a87 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-24mb/google/sarien: Remove MAC address pass throughDtrain Hsu
Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:149813043 TEST=tested on sarien and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-02-24mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pinEric Lai
Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin. This can save 1mW power comsumption. BUG=b:149289256 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-24mb/google/{auron,slippy}/ec: clear pending events on S3 wakeupMatt DeVillier
Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source] partially broke resume from suspend on Auron and Slippy variants when multiple events exist in the EC event queue. In the case of the device suspending manually and then subsequently having the lid closed, the device will be stuck in a resume/suspend/resume loop until the device is forcibly powered down. Mitigate this by clearing any pending EC events on S3 wakeup. Test: build/boot several Auron/Slippy variants, test suspend/resume functional with both single and multiple events in EC event queue. Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-24mb/google/dedede: Add waddledoo variantKarthikeyan Ramasubramanian
Add initial support for waddledoo board. BUG=None TEST=Build the mainboard and variant board. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-24mb/google/dedede: Add EMMC configurationKarthikeyan Ramasubramanian
Turn on EMMC device and enable the HS400 mode. Configure the GPIOs associated with EMMC. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-24mb/google/dedede: Add USB configurationKarthikeyan Ramasubramanian
Add USB port configuration in devicetree. Configure USB Over-Current (OC) GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-24mb/google/drallion: Remove MAC address pass throughDtrain Hsu
Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:147994020 TEST=tested on drallion and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-24soc/intel/cnl: Rename hfsts into me_hfstsSridhar Siricilla
Remove me_hfs3 union from cnl/me.c since it's already defined in soc/me.h. Rename below union tags for consistency: hfsts2 -> me_hfsts2 hfsts3 -> me_hfsts3 hfsts4 -> me_hfsts4 hfsts5 -> me_hfsts5 hfsts6 -> me_hfsts6 TEST=Verified on hatch Change-Id: If81edbad0322425ee3e96c55a9c84a5087604308 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-23soc/intel/apollolake: Make SMI_STS offset macro definition consistentSubrata Banik
This patch makes all bit field macro definition for SMI_STS register (offset 0x44) be consistent i.e. ending with "_STS_BIT". Also modified relevant files where those macros are getting used. Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-21cpu/x86/smm: Convert C++ style commentEugene Myers
Originally, this patch made 'BIOS' uppercase in the referenced comment and converted the C++ style to be consistent with the remainder of the function. Somewhere, the 'BIOS' became uppercase creating a merge conflict. Now this CL converts the C++ style to be consistent with the remainder of the comments. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I85d78b5e08a7643c3d87e3daf353d6b3ba8d306b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38854 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-21security/intel/stm: Use depends on ENABLE_VMXEugene Myers
The STM is a part of the core VTx and using ENABLE_VMX will make the STM option available for any configuration that has an Intel processor that supports VTx. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I57ff82754e6c692c8722d41f812e35940346888a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38852 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-21security/intel/stm: Check for processor STM supportEugene Myers
Check to ensure that dual monitor mode is supported on the current processor. Dual monitor mode is normally supported on any Intel x86 processor that has VTx support. The STM is a hypervisor that executes in SMM dual monitor mode. This check should fail only in the rare case were dual monitor mode is disabled. If the check fails, then the STM will not be initialized by coreboot. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-21nb/intel/snb: Add PCI routing table for PEG root portsJames Ye
Previously the PRTs were defined in southbridge code (8014714 southbridge/intel/bd82x6x/acpi: Fix IRQ warnings), but this was lost when southbridge PRTs became autogenerated. Add the proper PRTs for the PCI express for graphics root ports. This (again) fixes warnings issued by Linux for interrupts on secondary functions of devices on the PEG ports, such as the HDMI audio controller on graphics cards. pcieport 0000:00:01.0: can't derive routing for PCI INT B snd_hda_intel 0000:01:00.1: PCI INT B: no GSI Tested with GIGABYTE P67A-UD3R (CB:31363) with Radeon HD 5670. Change-Id: Ic429ec2fdeadb9dab1c03916974e173004d6cd16 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-20soc/amd/stoneyridge: Remove TODO for file extensionsMarshall Dawson
The comment is no longer relevant. Perhaps the intention had been to modify the names of the files delivered from AMD in order to simplify Makefile.inc. AMD firmware is distributed via the new amd_blobs repo and the filenames match the blobs as they are released. Multiple Family 15h devices are supported by this directory and their SMU Firmwares do not all follow identical naming convention. Keep the existing functionality and reword the comment. BUG=b:120118850 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ifbf8e2286f34bc37a6178c37f8c412ec51ee02c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-19soc/intel/common/block/lpc: Drop unnecessary helper functionSubrata Banik
This patch removes unnecessary helper function pch_lpc_interrupt_init() and directly uses soc_pch_pirq_init() function to avoid redundant device NULL check. TEST=Able to build and boot CML platform. Change-Id: I3d11afb7e98f9b7f84beb2fdf308bbffeb3bbff7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38952 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-19soc/tigerlake: Add IRQ header and ACPI support for JSPMeera Ravindranath
Tigerlake irq.h and pci_irqs.asl have differences compared to Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as pci_irqs_tgl.asl Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake SoC and allowing irq.h and pci_irqs.asl to choose the correct file based on SoC selected. BUG=None BRANCH=None TEST=Compilation for Jasperlake board is working Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-19soc/intel/p2sb: Drop unnecessary P2SB_GET_DEVNico Huber
PCH_DEV_P2SB already covers both __SIMPLE_DEVICE__ cases. The values are only used for PCI-config access functions, which also check for NULL when necessary. The PCI_DEV_INVALID case can't occur by definition, and if we wanted to check, we could do so at compile time using _Static_assert(). Change-Id: I400fc20133809aaa0fd0519531a62ec9b8812ef1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-19vboot: remove use of NEED_VB20_INTERNALS switchJoel Kitching
The NEED_VB20_INTERNALS switch is being deprecated. Use the header file vb2_internals_please_do_not_use.h instead. BUG=b:124141368, chromium:957880 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie35644876178b806fab4f0ce8089a556227312db Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:2055600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-19vboot: use vb2api_get_recovery_reason functionJoel Kitching
Use vb2api_get_recovery_reason() API function rather than accessing vb2_shared_data internals. Of all the vanilla verified boot code in coreboot, this is the last remaining use of vboot's internal data structures in coreboot. There remains only one sole instance in Eltan's code. BUG=b:124141368, chromium:957880 TEST=make clean && make test-abuild BRANCH=none Change-Id: I845c9b14ffa830bc7de28e9a38188f7066871803 Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:2055662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-18mb/intel/glkrvp/chromeos.fmd: Correct indentationAngel Pons
Tested with BUILD_TIMELESS, no changes. Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-18cpu: Allow to configure microcode at pre-defined addressAndrey Petrov
FSP-T takes microcode pointer and location parameters, and FSP-T is invoked before CAR is set-up and before memory is trained. So it is not possible to modify supplied microcode pointer in runtime. Because of that we have to hardcode the pointer in bootblock. Also, current FSP-T on Xeons require microcode (it is not optional). Reasons for that are currently unclear and are being investigated. However for the present time we need to be able to add microcode at a certain offset so FSP-T can be used. TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-02-18mb/facebook/monolith: Use serial number and UUID from VPDWim Vervoorn
The serial number and UUID returned by DMI are retrieved from VPD. The solution supports a 16 character "serial_number" and a 36 character "UUID" string. BUG=N/A TEST=tested on monolith Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-18mb/facebook/monolith: Enable use of VPDWim Vervoorn
Enable use of VPD for monolith. This will be used to store the UUID and Serial number. BUG=N/A TEST=build Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-18soc/intel/common: Add function to wait for CSE to enter Soft Temp Disable modeSridhar Siricilla
Below helper function is added: cse_wait_com_soft_temp_disable() - It polls for CSE's operation mode 'Soft Temporary Disable'. CSE enters this mode when it boots from RO(BP1) partition. The function must be called after resetting CSE to wait for CSE to enter 'Soft Temporary Disable' Mode. BUG=b:145809764 Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-18soc/intel/common: Check prerequisites for HMRFPO_GET_STATUS commandSridhar Siricilla
Send HMRFPO_GET_STATUS command when CSE's current working state is Normal. TEST=Verified on hatch. Change-Id: I4380e5096c6346d88aae6826d19a2f4ed1e97036 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-18cpu/x86/name: Make name.c file available in romstageUsha P
In this patch, name.c file that includes the function definition for fill_processor_name which is used by the report_cpu_info function is been made available in romstage. This is done to facilitate the report_platform_info to be called from romstage, as the intention is to move the report_platform_info to romstage for all SOC's due to the bootblock size constraint. BUG=None TEST=Build and boot APL, GLK and CNL platforms. Change-Id: Ifd6d4b80c2e07d02adaed676a56efeb6fb704552 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-18ec/google/chromeec: Add SSDT generator for ChromeOS ECTim Wawrzynczak
Upcoming patches for the Linux kernel (5.6 ?) would like to consume information about the USB PD ports that are attached to the device. This information is obtained from the CrOS EC and exposed in the SSDT ACPI table. Also, the device enable for this PCI device is moved from ec_lpc.c to a new file, ec_chip.c, where EC-related ACPI methods can live. It still allows other code to call functions on device enable (so that PnP enable for the LPC device still gets called). BUG=b:146506369 BRANCH=none TEST=Verify the SSDT contains the expected information Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-18security/vboot: Correct help text of VBOOT_STARTS_IN_ROMSTAGEYu-Ping Wu
Since CB:37231 [1], the vboot working data has been replaced with vboot work buffer, so corrrect the help text of option VBOOT_STARTS_IN_ROMSTAGE accordingly. [1] security/vboot: Remove struct vboot_working_data BRANCH=none BUG=chromium:1021452 TEST=none Change-Id: I80783274179ae7582bbb4c8f9d392895623badce Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-02-18nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI IDJonathan A. Kollasch
Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-18nb/intel/sandybridge: use list of northbridge device IDsJonathan A. Kollasch
Change-Id: Ida311a7b0c1f33b1724a07c7cd64ea9834cfc179 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-18volteer: allow empty SPD_SOURCESPaul Fagerburg
Some Volteer variants might not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17ec/lenovo/h8/acpi: Add alternative Fn-F2 and Fn-F3 layoutNicola Corna
thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and the lock hotkey (KEY_COFFEE) on scancode 0x02. On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2 and Fn-F3 are different from the default one so a new layout has to be defined. Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-17mb/google/slippy: Fix IRQ of the ambient light sensorNicolò Veronese
Change based on google/auron that is similar to peppy. This will be helpful for the next follow-up commit that will add ACPI for the ambient light sensor. Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3 Signed-off-by: Nicolò Veronese <nicveronese@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-02-17soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 07:17:53 +0000