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2022-06-15mb/google/nissa: Increase I2C bus frequency to around 390 kHzReka Norman
- Set the speed to I2C_SPEED_FAST in each speed_config so that the speed_config is actually applied. Currently, the speed_config isn't applied, so the hcnt/lcnt calculation falls back to rise_time_ns and fall_time_ns, which are 0 since they're not set. This results in frequencies around 300 kHz. - Move the data hold time to the speed_config, ensuring that the resulting sda_hold value remains the same. - For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to give a frequency around 390 kHz. - In the baseboard, keep default scl_lcnt and scl_hcnt values. These work well for buses with a rise time around 100 ns, and can be used as a starting point before tuning them for a specific variant. BUG=b:229547183 TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks and nereid and check they meet the spec. nereid clock frequencies: I2C0 - 387.9 kHz I2C1 - 392.7 kHz I2C3 - 386.3 kHz I2C5 - 383.6 kHz nivviks clock frequencies: I2C0 - 387.67 kHz I2C1 - 380.47 kHz I2C2 - 388.51 kHz I2C3 - 384.03 kHz I2C5 - 389.09 kHz Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/dedede/var/shotzo: Generate SPD ID for supported partsTony Huang
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: - MT53E512M32D2NP-046 WT:E - H9HCNNNBKMMLXR-NEE - K4U6E3S4AA-MGCR - MT53E512M32D1NP-046 WT:B - H54G46CYRBX267 - K4U6E3S4AB-MGCL - K4U6E3S4AA-MGCL BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: Ie0ffdfed47b1791b990affd9eee262faede4b0c8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65081 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com>
2022-06-15mb/prodrive/hermes: Add BIOS menu control via EEPROMLean Sheng Tan
Introduce a new field in the board settings EEPROM region to control whether BIOS menu is to be enabled. This field will be used in EDK2 payload. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I0af81c9e70a0088caea6bc7e2b81eab9a123c0f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-06-14mb/google/brya/var/agah: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ A2 | | A0 C2 | | C0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I8cc7be20988ff3cc3be1fac3c9b143059ff9190c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65088 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14mb/google/brask/variants/moli: change clk_src and clk_req for LAN_I225VRaihow Shi
change clk_src and clk_req to 4 for LAN_I225V based on ADL_Moli_SC_MB_20220601.pdf. BUG=b:235768639 TEST=emerge-brask coreboot and check LAN_I225V can connect. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/google/brask/variants/moli: Remove the cnvi_bt_audio_offloadRaihow Shi
Remove the cnvi_bt_audio_offload because it is already probed in variant.c for moli. BUG=b:235426221 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I15077ca161b6283e764105d1c2fbc59ead1fd761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/google/brask/variants/moli: enable use_custom_pldRaihow Shi
enable use_custom_pld to match the custom physical location define. BUG=b:235426221 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I62d133eed02faf4e5ad054a0901f73b1196c4c6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/hp/snb_ivb_laptops/Kconfig: move common option to commons sectionPeter Lemenkov
Apparently all nine HP Sandy/Ivy laptop variants select MAINBOARD_USES_IFD_GBE_REGION. So let's move it to the COMMON section. Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I48e0d03c59d3ba013b479b59df8a15a0f8d23c50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-14soc/intel/cmn/cpu: API to initialize core PRMRRSubrata Banik
This patch implements API to sync between core PRMRR(Processor Reserved Memory Range Registers). Read PRMRR base and limit value from BSP and apply it on the rest of the cores. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I720669139429afc3d8c8d15c0ce15f1524f22e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-14mb/intel/adlrvp: Add new upd setting for ADL RVP with Raptor LakeBora Guvendik
Currently, ADL FSP headers and RPL FSP headers differ. Set a RPL only upd for adlrvp with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e69323949233aa8c325a757b28b9d80cbdf4322 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-14mb/amd/chausie/Kconfig: enable PCIe power managementFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia24a502994d24f3341273c5e6f768687ad20baf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65113 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14mb/amd/chausie/devicetree: add PCIe clock output configurationFelix Held
The general purpose PCIe clock outputs 0, 1 and 3 are used with their corresponding clock request pins, so set the gpp_clk_config to GPP_CLK_REQ for those and disable the unused output 2. This matches the DXIO descriptor in port_descriptors.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2Ronak Kanabar
In x86 processor as per Software Developer's manual there are 2 ways to get CPU topology by querying the processor. BIOS can use CPUID instruction using CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) as input or CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) as an input. Both will return valid CPU topology data. While CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) returns data related to number of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) provides more granular information regarding Die, package etc. coreboot uses V2 to in order to query and return CPU topology data as of now since that's the highest instruction of CPUID which is supported, there is a mismatch in the way FSP processes the data. FSP queries coreboot MP services to get CPU topology data which uses structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there is hang observed on ADL_N CPUs. To solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY data to processor_info_buffer->Location structure so remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 Files: MdePkg/Include/Protocol/MpService.h#L182 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 Ref doc: Software Developer’s Manual volume 3 CH 8.9 BUG=b:220652104 TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology value and observe system boots (no hang). Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-13mb/google/volteer: Fix wrong Type-C port for retimerDerek Huang
This change fixes wrong type-C port number for voxel. Voxel uses tcss_usb3_port1 not tcss_usb3_port3. BUG=b:231344977 BRANCH=volteer TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Iba7b3b15296bed99d3626a6d53dfd59e8d20fe5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64022 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-13soc/amd/sabrina: only make the available clock outputs configurableFelix Held
Sabrina only has 4 PCIe clock outputs with corresponding clock request pins available, so only make those 4 configurable in devicetree and disable the rest unconditionally. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-13mb/google/dedede/beadrix: Update SoC gpio pin of I2C cameraTeddy Shih
Update SoC GPIO setting of unused I2C camera pins according to beadrix schematics. GPP_H6 : NF1 -> NC (AP_I2C_CAM_SDA) GPP_H7 : NF1 -> NC (AP_I2C_CAM_SCL) BRANCH=dedede BUG=b:235005592 TEST=on beadrix, validated by beadrix's camera still working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I8be57406a44096c764c1faa8f45267d08c4694fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64971 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12soc/intel/lpc: Set up default LPC decode rangesArthur Heymans
Intel LPC devices have generic and fix IO decode ranges. This CL is smarter about using generic ones, by using the fixed ones first. Change-Id: Ifd98bcc639ee08d068956a33b0e12cc70211ca2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65097 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/google/dedede/beadrix: Update probe daughter LTE mainboard SARTeddy Shih
Update FW_CONFIG probe for daughter board LTE and mainboard SAR according to beadrix schematics. BRANCH=dedede BUG=b:226910787, b:213549229, b:233983127 TEST=on beadrix, validated by beadrix LTE working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I126a1c548b6314acc0749fcfbdffd8f482c4f46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-12mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByteFelix Held
The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so it won't fit in the flash and makes soc_update_apob_cache return early before writing the APOB data from DRAM into the flash with this warning: [WARN ] RAM APOB data is too large 1db18 > 18000 Increasing the RW_MRC_CACHE size to 120 kByte fixes this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/google/corsola: Fix PS8640 power-on T6 sequenceRuihai Zhou
The T6 of PS8640 power on sequence should be larger than 0ms, but it's -0.062ms now. Add 100us delay between VRF12 and VCN33. The PS8640 power-on sequence is described in the "PS8640_DS_V1.4_20200210.docx". BUG=b:235448279 BRANCH=None TEST=The sequence T6 is larger than 0ms when power on. Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I0b8a37d6119dc027a9d1c0a62c087b0a7ef14cac Reviewed-on: https://review.coreboot.org/c/coreboot/+/65084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-12soc/mediatek: pass access mode to the payloadWenbin Mei
Some eMMCs (for example, Kingston-EMMC64G-TX29-HP) may enter the ready state by sending CMD1 twice. If it is in the ready state, then the payload (for example, depthcharge) will not send CMD1, but the access mode is only available from the response of CMD1. Therefore, we need to pass the access mode to the payload by defining the following types: - MMC_STATUS_CMD1_READY: in ready state and access mode is byte mode. - MMC_STATUS_CMD1_READY_HCS: in ready state and access mode is sector mode. BUG=b:234672726 BRANCH=cherry TEST=boot ok Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iad905781d8ba0105911cf87a6b845cd8df57521e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65054 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-10mb/google/brya/variants/felwinter: Enable TBT PCIe Root Port 0John Su
The TBT device can't be recognized after we re-plug it at DB type-c port. Intel found that tbt_pcie_rp0 has mapping error after each re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this problem and take this as short term solution. Intel will implement re-mapping mechanism in ACPI for long term solution. BUG=b:230141802 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I61429033dfe64d67916167bb901bdd8246db953e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10soc/amd/sabrina: Update fw.cfg for new names and blobsMarshall Dawson
Make the config file reflect reality instead of using the old cezanne copy. TEST=Build chausie BUG=b:220848549 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I8362bc19875ae152e0deab7f64d5b1c50929b95b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10soc/amd/sabrina: Adjust whitespace in fw.cfgMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I591c6a69f0971c3f4fdb8bb54a7f54c948caa648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10soc/amd/sabrina: Update firmware config for soc nameMarshall Dawson
Modify the config file, consumed by amdfwtool, to use "sabrina" and "SBR" named files. TEST=build chausie using updated amd_blobs BUG=b:220848549 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ia993644e67d14792d753cc74a957529d15be18f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10mb/intel/adlrvp: Add 5G WWAN ACPI support for adlrvp_rpl_ext_ecCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3 are generated under the root port. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I74434d833086f639927d8369f8a6e3af31dd99e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64648 Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/google/brya: Select SOC_INTEL_RAPTORLAKE for skolas variantsBora Guvendik
BUG=b:229134437 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib0531ff736ed7ac52bff8607b26b3e7f1d3ac3ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/intel/adlrvp: Select SOC_INTEL_RAPTORLAKE adlrvp_rpl_ext_ec variantBora Guvendik
BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I12eab0fe2a3c21011f50c72718514fbc90cbe658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10soc/intel/alderlake: Add Kconfig for Raptor LakeBora Guvendik
Until FSP for RPL and ADL align, mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. Currently, ADL FSP headers and RPL FSP headers differ. Use RPL FSP header with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iaf95352b9cafb81f23522bcf63753d199c0420eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10soc/amd/sabrina: change MAX_CPUS to 8Felix Held
The Sabrina APU has a maximum configuration of 4 physical cores with 2 threads each, so a total of 8 CPU cores. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10soc/amd/sabrina/mca: update MCA bank names to match the hardwareFelix Held
The MCA bank names were checked against PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1b947e686a0306d4468203103f91107c15ececc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-10soc/amd/sabrina/Makefile: Support new Ucode patch namesFred Reitberger
Sabrina slightly changed the names of microcode patches. Adding a wildcard to support the new name without breaking current builds that are using the placeholder CZN binaries. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I86caf0ba5c15f64a9a1f0e76a3186919e5e761a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65069 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/chausie/ec: Set MS bit in SW02Fred Reitberger
Set the MS bit in EC SW02 register to enable s0i3 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10soc/intel/apollolake: Let coreboot set the VendorID and Subsystem IDSean Rhodes
Set all FSP S UPDs that set IDs to 0, which allows them to be set by coreboot. Tested on StarLite Mk IV and LPC now has the correct device ID of 0x31e8, where previously it had 0x7270. The UPDs differ APL and GLK, but the ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I034c9dc9d81c4d775dfff0994c9a6be823689b1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-10mb/google/brask/variants/moli: correct ddi_ports_configRaihow Shi
1. enable DDI_PORT_1, DDI_PORT_3 hot plug detection to let tcp0 and tcp2 can display 2. remove DDI_ENABLE_DDC for Port 2, because tcp-dp dosen't need to enable DDC BUG=b:234521799 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/google/brask/variants/moli: enable USB retimerRaihow Shi
Enable USB retimer in moli overridetree. BUG=b:233869074 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ib7ea0b0d85776857d07e129935059397720fa0e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVPCliff Huang
In Adl-P RVP, those interfaces are used as USB ports. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I322280ab02361e3a2a5925d69f33b23453d36dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63946 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVPCliff Huang
Use clock src and clock req to 7 for x4 slot. Remove free running clock setting for clock 6. Configure gpio for source clock OEB native function going to x4 slot. BUG=b:233252409 BRANCH=firmware-brya-14505.B TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check the device. ex: 58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01) NOTE: The bus number varies. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-10ec/google/chromeec: Add support to report fan speed via ACPISumeet Pawnikar
Add fan speed rpm control for DPTF based Active2 policy as per document #626708, by utilizing existing FAN0 variable from src/ec/google/chromeec/acpi/emem.asl#18. There is no corresponding EC change required for this policy support because EC fan code already exporting this rpm value using EC_MEMMAP_FAN for FAN0. BUG=b:224457192 BRANCH=None TEST=Built and booted on ADL-P based Brya system and verify the fan speed in rpm under sysfs path cat /sys/bus/acpi/devices/INTC1048\:00/fan_speed_rpm. Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-09soc/amd/sabrina/acpi: Correct VID decoding on SabrinaFred Reitberger
Sabrina uses the SVI3 spec for VID tables which is incompatible with the SVI2 spec used on PCO/CZN. Move the defines from common to soc and update the decoding for sabrina. See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables TEST=timeless builds on mandolin/majolica for PCO/CZN build chausie and verify pstate power is correct in ACPI tables Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I915e962f11615246690c6be1bee3533336a808f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-09mb/starlabs/lite: Disable Burst in Power Saver profileSean Rhodes
When the CMOS option `power_profile` is set to Power Saver, disable Burst. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-09mb/google/dedede/var/shotzo: Deselect BASEBOARD_DEDEDE_LAPTOPTony Huang
Shotzo is not a laptop (it is a Chromebase), therefore deselect BASEBOARD_DEDEDE_LAPTOP. BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: I4669ef163e4bd8f2de556a051197802ee2d54927 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65015 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/dedede: Create shotzo variantTony Huang
Create the shotzo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=b:235303242 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SHOTZO Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-06-09mb/google/brask/variants/moli: remove mainboard_vbt_filename in ramstageRaihow Shi
mainboard_vbt_filename() is to decide which VBT to return, but moli only has one VBT, so it doesn't need this function. BUG=b:234521809 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/alderlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init()Subrata Banik
This patch provides an option for CPU programming where coreboot expected to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09vc/intel/fsp/fsp2_0/mtl: Add FSP header files (2173_00) for Meteor LakeSrinidhi N Kaushik
Add header files generated from FSP 2173_00 source build for Meteor Lake platform. BUG=b:234701164 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I8b1caa4bc09f09005859e6c8853d14b8f96a26ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-09soc/intel/alderlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. This patch is the Alder Lake equivalent of CB:59024. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-09soc/intel/apollolake: Correct the maximum number of Heci devicesSean Rhodes
Both APL and GLK have 3 Heci devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7dc7afb4d2906838a478083b466b36aa78ec49a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-09soc/intel/alderlake: add support for external source clockCliff Huang
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9. This allows boards to use source clock 7, 8, 9. BUG=b:233252409 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09soc/intel/alderlake: Add support for PCIe slot & device detect timeoutCliff Huang
1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09mb/google/brya: Create ghost4adl variantJack Rosenthal
Create new variant of Brya "ghost4adl". Memory config and device tree was sourced from the schematics (revision 7670d041f40279b5126990f20ec8f90c0538440c). GPIO overrides have not been added yet. This is to be added in a follow-on CL. BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-06-09mb/google/brya/var/agah: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 portIvy Jian
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`. The change is required to detect USB2 device on type-C port of Agah boards. BUG=b:233554817 TEST=build and test USB2 hub could be detected on both the Type-C ports. ================================================================= usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00 usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0 usb 3-3: Product: USB 2.0 Hub hub 3-3:1.0: USB hub found hub 3-3:1.0: 4 ports detected ================================================================= Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/nissa/var/craask: Generate SPD ID for supported memory partTyler Wang
Add craaskbowl supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3LKBKB0BM-MGCP 2. Hynix H9JCNNNCP3MLYR-N6E BUG=b:235134420 TEST=Use part_id_gen to generate related settings Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64858 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/brya: Add memory parts for CrotaTerry Chen
Add a mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) K3LKLKL0EM-MGCN 3 (0011) H58G56AK6BX069 2 (0010) BUG=b:233830713 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: If9f2b65717a05576fa6b4fb1f53133902ff1a7c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64982 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/qemu-armv7: Initialize cbmemArthur Heymans
Change-Id: I607205a0d44c71eb26031ced7a8af303efacd6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-09mb/aopen/dxplplusu/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Iae3343e66906a8123b3d8de2b67948f286e4ad32 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntaxFelix Singer
Change-Id: I8a0f18d37c065827a0f5b54f24ea1fcde497c504 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace And() with ASL 2.0 syntaxFelix Singer
Change-Id: Id600bcb3fad35455adffe11a8105ad2590e83feb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Idfc08803946cc2d4537db4be8d1bc07e48aa6fed Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I63b8b8a086e2c5ede765855b3c803206edf87690 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/kahlee: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I19835510b89cd243277f0c9701209c81bdf6ea29 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/cyan: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Ib8719143a5a217173b34931e9c0ef02e9895d0a5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual(a, b)` with `a <= b`. Change-Id: Ib4e81ea95c6fda0e8f8640671db5ce56f3a1b474 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I04f3cc2dbba59d732c9c52a4b90a32481f9da337 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Ib34dc8d84815d0885f30b3ea8ceb2fb95a833d50 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Ib96cf05f575a2868b2ad0c00fd5486d6e2c5d90a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I86a11ab5d2667661af3491174001001e644083e3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: If83d7fe29d112ba0ed0f72798f2b5436ecf0a6a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Ief1fe60116645d0cdad9e7ac600bc1062b54b40d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Ic58e22046aa13549747692f4b21184cf573aa4d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I99cc4cf08ad74f2cb84e0ad16e615e03bbf388af Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace Divide(a,b,,c) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b, , c)` with `c = a / b`. Change-Id: I9b8262396755197dfbe044e3dc6a6a75c903f093 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I6732fd876524feab924a58434bec381dcdb87bce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Ied407753ee3bb024c8c0350c45312c337ac799e5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/ene_kb3940q/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Ic04ce82fbfd36bbd2e0cfda1a92ca0a18e1fcd73 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/kontron/it8516e/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I81e976de964f6ae3528884debaf2b24ddf8ed28a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Id61c537cc91edbd407fb6429eb4dd2bc8bc7f123 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Idc24216209bbfe73ef4197d4b8101f0d7e5891f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I5c16893b9c98f36fd2c210ed301c2ebb65f95368 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/kahlee/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: Id7975a8cad4078a523de2466919982ad540f5dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I61ef7b53e851f4c2367cba43ff76b200e9490ad2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/aopen/dxplplusu/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: If482b2ad4ba7d4ed1ca8c0695690ede153ed1e2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I56e8fdb2503a84ded2bcf183402602579c3f2997 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntaxFelix Singer
Change-Id: I493d686fb122fb47f0b4dcf34e3635518770f97f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09arch/x86/acpi: Replace ShiftRight() with ASL 2.0 syntaxFelix Singer
Change-Id: Iaa99d9dc4cf12a7431be1610d339cf78116f8bea Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I033f73e6552746c6899e46ee4d619ab47cb3d55b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09sio/winbond/w83627hf/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I24cf4fd70e887c14006975f494be63c34f8a75e6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09sio/winbond/w83627hf/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I9344e34058a1dd8b951d273e53e3c229a0ec07b4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/winbond/w83627hf/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I3833a3a341bd64191cc0b811ca80e96a359307a1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I407d061ac7664d4910b8759fd1a72eab133b6e22 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Ia09c54465af47f5779917ed71bb3ea148864dfd1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/google/chromeec/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I2e0c5961fcc90c97666f49837a71f6c0bdc429b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual(a, b)` with `a <= b`. Change-Id: I256e56841e1c7037fe8ba5e9a963ad2301092325 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Ic114e097a08488106554ce2dec61fa219d7cf1d0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I1dbe6c325ed33a4dd15e4d6315b2308d8351974e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I49a7ed2d57124746815478f3ead8a8f7c54d048a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual(a, b)` with `a <= b`. Change-Id: Ib00f363b48295ed1c000a839f54d5ea5dc2b88e2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I12c855437a581beade2d218b8f710cf1b32cb841 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: Ic9836acb4d32f2ce30c3c6d488bc22ddc64bf365 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 20:07:38 +0000