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2024-08-06soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platformYuchi Chen
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83314 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-06vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoCChen, Yuchi
Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83192 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-06mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flashKrystian Hebel
Depending on how firmware image was passed to QEMU, it may behave as: - ROM - memory mapped reads, writes are ignored (FW image mounted with '-bios'); - RAM - memory mapped reads and writes (FW image mounted with e.g. '-device loader'); - flash - memory mapped reads, write and erase possible through commands. Contrary to physical flash devices erase is not required before writing, but it also doesn't hurt. Flash may be split into read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd. Combined size of system firmware must not exceed 8 MiB by default (FW image(s) mounted with '-drive if=pflash'). This function detects which of the above applies and fills region_device_ops accordingly. Tested by starting QEMU with firmware passed as '-drive if=pflash', '-drive if=pflash,readonly=on' and '-bios'. When started with firmware passed through '-device loader', coreboot complains about corrupted FMAP, but this is the same behavior as without this change: [ERROR] Invalid FMAP at 0x40000 [EMERG] Cannot locate primary CBFS Writable pflash support was added about 17 years ago, so it should be supported by all QEMU versions currently in use. Since QEMU 5.0.0 it is possible to change the limit of firmware size with `max-fw-size` machine configuration option, up to 16 MiB, as bigger sizes would overlap with default IO APIC memory range. Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82555 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-08-06Kconfig: Reverse ARCH_SUPPORTS_CLANGArthur Heymans
Since most targets support clang it's easier to reverse the semantics of the Kconfig options. Change-Id: Ib28e7a4cb286b9f8b05be94dae3947179f43c746 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-06acpi/acpigen_ps2_keybd: Fix total keymap size calculationTyler Wang
This patch move keymap size calculation inside of has_alpha_num_punct_keys condition. When the condition is not met, it can prevent total keymaps size calculate incorrectly. BUG=none TEST=emerge coreboot pass Change-Id: I3dcf31d89924c1a8f2768e42065761b361e9ca41 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-06mb/google/brox/var/jubilant: Update WWAN and UsbCam SettingsRen Kuo
Update GPIOs for WWAN and USB Camera functions. BUG=b:341188351 TEST=Build and verify on jubilant Change-Id: I145aa994767ddc59be519b96017af71badf82734 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2024-08-06mb/google/trulo: Register Firmware name for ISHVarun Upadhyay
Define ISH main firmware name so ISH shim loader can load firmware from file system. BUG=b:354607924 TEST=Boot trulo board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Device 54fc Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83671 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-05mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices configKeith Hui
Match PCIe root port allocation and associated comments to boardview, as follows: Z77 PCIe ports 1-4: PCIEX16_3 (x4) Z77 PCIe port 5: PCIEX1_1 Z77 PCIe port 6: RTL8111F LAN Z77 PCIe port 7: ASM1042 USB3 Z77 PCIe port 8: ASM1061 eSATA CPU PCIe lanes 1-8: PCIEX16_1 CPU PCIe lanes 9-16: Multiplexed via 4x ASM1480 to PCIEX16_1 lanes 9-16 and PCIEX16_2 lanes 1-8 (CPU PCIe lanes are not covered by overridetree.cb.) These are not hardware tested. Change-Id: I472e28add254ea945b401d1ddfd03f29f46d8fd2 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-05mb/supermicro/x10slm-f: Add board id for flashing via BMCNico Huber
The ID for X10SLM+F is 0811 as reported by Knogle on IRC. Change-Id: Ie58aad50e66efbc3113541884beea9668d886b5d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-05mb/google/dedede/var/awasuki: Disable SD cardWeimin Wu
Because Awasuki doesn't have SD card, disable related configurations. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: I1b0d2a9c2f9cdd4bca7c30cdc454ffa84b293146 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83706 Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-05soc/amd: add PSP SMI handler stubFelix Held
The PSP can send SMIs to the x86 side to have the SMI handler service requests from the PSP. This commit adds an empty PSP SMI handler; the actual implementation is added in later patches to keep the patches relatively small. This patch is a slightly modified version of parts of CB:65523. Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/83739 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-05mb/google/brox: Add model brox-ti-pdcBob Moragues
BRANCH=None BUG=b:348171026 TEST=Test on TI PDC device Cq-Depend: chromium:5691079 Cq-Depend: chromium:5691080 Cq-Depend: chrome-internal:7464767 Original-Change-Id: I6ffb8bdb2245a74b0d5270435d0ffc8a44e7c2a6 Original-Signed-off-by: Bob Moragues <moragues@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5691110 Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Change-Id: Iac5b4cd4dcb1d274553f78e9d4295f8f9ad8a863 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-05nb/intel/*: Match ACPI with resource allocationArthur Heymans
Currently resource allocation starts top down from the default value 0xfe000000. This does not match what ACPI reports, so adapt CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I2ba0e96a7ab18d65b7fbbb38b1a979ea2ec6d1be Reviewed-on: https://review.coreboot.org/c/coreboot/+/80207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-04mb/google/brya/var/nova: Adjust Type-C port to USB 2.0 onlyPranava Y N
This patch introduces the following changes, - Remove TCSS XHCI (USB 3.x) devicetree settings - Update Over Current (OC) & USB 2.0 config - Update TCSS-XHCI capabilities BUG=b:348332200 TEST=Able to build google/nova and ensure lsusb can list genesys hub device. Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83707 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-04mb/google/brya/var/nova: Remove PMC MUX settingPranava Y N
This patch removes the PMC MUX related setting from devicetree as Nova doesn't include a MUX for it's USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-03mb/dell/optiplex_9020: Fix UB in package power calculationMate Kukri
Fix potential undefined behaviour in the `get_pkg_power()` function: - If `rapl_power_unit == 0`, `pkg_power_info / rapl_power_unit` is invalid - If `rapl_power_unit > 7`, the result of the shift doesn't fit into a `uint8_t` Signed-off-by: Mate Kukri <km@mkukri.xyz> Change-Id: I48ef59c4fbeb0a55675ac24da31e6e0b194cb58d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83736 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-03mb/google/rex: Skip UART0 config in FSPSubrata Banik
UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=none TEST=Able to build and boot google/rex0. Able to see all debug prints over CPU uart. Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-03arch/arm64/armv8/mmu: Improve log formatYu-Ping Wu
Currently we use "%p" to print the address, which results in different string lengths, depending on the value of the address. To improve readability of the printed addresses in the log, change the format to "0x%013lx", so that the length of the printed addresses will be consistent. In addition, print the level of the translation table when setting up a new table. Example log: Backing address range [0x0000000000000:0x1000000000000) with new L0 ... Mapping address range [0x0000000000000:0x0000200000000) as ... Backing address range [0x0000000000000:0x0008000000000) with new L1 ... Mapping address range [0x0000000100000:0x0000000130000) as ... Backing address range [0x0000000000000:0x0000040000000) with new L2 Backing address range [0x0000000000000:0x0000000200000) with new L3 Mapping address range [0x0000000107000:0x0000000108000) as ... Mapping address range [0x0000000200000:0x0000000300000) as ... Backing address range [0x0000000000000:0x0000000200000) with new L3 ... BUG=none TEST=emerge-geralt coreboot BRANCH=none Change-Id: Ib29c201e1b096b9c7cd750d2541923616bc858ac Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-02soc/ti/am335x: Remove superfluous formatsArthur Heymans
These formats are already included in memlayout.ld. Change-Id: I89d226440308ce3fbe00382698dcd8c88863e694 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02soc/ti/am335x: Use Linker instead of compiler to linkArthur Heymans
Clang does not work that well as a linker for the header as it will default to other linkers which do not work well here. Instead just use the linker directly. Change-Id: Id6ba42b470349a4b138a65b2a037f16a65982ef7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flagDinesh Gehlot
The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is enabled and the system is currently booting from the RO section. Additionally, it integrates forced CSE sync into eSOL decision-making. BUG=b:353053317 TEST=Verified forced CSE sync on rex0 with GBB 0x200000 Cq-Depend: chromium:5718196 Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-02security/vboot: Include new gbb flag to enforce CSE syncDinesh Gehlot
This patch adds a GBB flag to coreboot, which, when enabled, enforces CSE sync even if the current CSE version matches the version in CBFS. The CSME sync GBB and flag are designed to enhance autotest functionalities and are not intended or recommended for use in developing any other features. BUG=b:353053317 TEST=futility gbb --help Cq-Depend: chromium:5718196 Change-Id: I6352959e1e898a90b4c6e12a22f8d6513f90ded9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83685 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-02i2c/drivers/generic: Return ROTM in a packageSean Rhodes
The ROTM method should return a package: ``` Name (RBUF, Package (0x03) { "0 1 0", "1 0 0", "0 0 1" }) Return (RBUF) ``` Adjust the acpigen to do this. Change-Id: Id493f6955c1d0dc3449402262a8575091a828226 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-02soc/ti/am335x: Change and optimize memlayoutArthur Heymans
Clang builds (bootblock: 20800 bytes) are slightly larger than GCC builds (bootblock: 18688 bytes) so increase the size of both bootblock and romstage. The technical reference manual mentions no upper limit to the size of the bootblock in the TI header so increasing the bootblock size is allowed. To be able to link the clang bootblock increase it from 20K to 22K. Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-02mb/google/brya/var/trulo: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-02mb/google/brox/var/greenbayupoc: update ALC236 verb tableWu Garen
The previous uploaded verb table is not fully applied due to configuration error. Uploaded the verb table provided by Realtek which can be found in b:336967284. BUG=b:326412504, b:336967284 TEST=deploy and check volume Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Terry Cheong <htcheong@chromium.org>
2024-08-02mb/google/brox/var/brox: Enable Class-D calibrationTerry Cheong
DC offset of class-D amplifier is 7mV in Brox which is larger than the expected 3mV. Add a section in the verb table to enable class-D calibration based on the updated verb table provided by Realtek in b:342506575 comment#6. This improves the offset to be less than 1mV. BUG=b:342506575 BRANCH=main TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \ playing -100dB sine waves. Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-01mb/google/brox: Create jubilant variantRen Kuo
Create the jubilant variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:348543712 TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_JUBILANT. Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-08-01soc/amd/common/smi_util: add PSP SMI helper functionsFelix Held
The PSP can send SMIs to the x86 side of the system. Add helper functions to configure and to reset the PSP SMI generation. Since Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific smi.h to bring it in line with the newer SoCs. This patch is split out from CB:65523. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDsSean Rhodes
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-01mb/starlabs/*: Add the subsystem ids for HDASean Rhodes
The Windows drivers require the subsystem ID to match on the PCI device, so set these to allow the driver to install. Change-Id: I01b36554d5322018efc72734a8e749cc06263577 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01mb/emulation/qemu-q35/memmap: Remove redefine macrosElyes Haouas
SMRAMC, C_BASE_SEG, G_SMRAME, D_LCK, D_CLS, D_OPEN, ESMRAMC, T_EN, TSEG_SZ_MASK and H_SMRAME are already defined in included "q35.h" file. Change-Id: Ic3c01cca14749f77adecc327a78ac011ba3f4c0b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83429 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-01soc/intel/xeon_sp: Add acpigen_write_pci_root_portLu, Pen-ChunX
acpigen_write_pci_root_port writes SSDT device objects for PCIe root port, _ADR and _BBN are provided. SSDT objects for direct subordinate devices will also be created (if detected), _ADR and _SUN are provided. TEST=Build and boot on intel/archercity CRB Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0 Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-08-01mb/google/nissa: Create teliks variantzengqinghong
Create the teliks variant of the nissa reference board by copying the anraggar files to a new directory named for the variant. BUG=b:352263941 BRANCH=None TEST=1. util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELIKS 2. Run part_id_gen tool without any errors Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768 Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01acpi/acpigen_ps2_keybd: Move KEY_DELETE to rest_of_keymapsTyler Wang
This patch supports keyboards that have delete key but without numpad. To prevent KEY_DELETE be defined twice, move it from numeric_keypad_keymaps to rest_of_keymaps. BUG=b:345231373 TEST=Build and test on Riven/Craaskino, delete key function works Change-Id: Ib922a2b52fa7152ba3d9deb44e2c8200b2a3802c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83684 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01mb/google/brya/var/orisa: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31soc/amd/common/psp: move buffer sizes to common headerFelix Held
Since the P2C_BUFFER_MAXSIZE value will be needed in another compilation unit, move the define to the common psp_def.h. P2C_BUFFER_MAXSIZE is moved there too for consistency reasons. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d4d93760c90ad6e0ecadf70600b1d697a02fa82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83701 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31soc/amd/common/psp_smm: introduce and use send_psp_command_smmFelix Held
When sending mailbox commands to the PSP from SMM, the SMM flag needs to be set right before sending the mailbox command and cleared right after the command is sent. In order to not have this code duplicated, factor it out into a function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3628463dece9d11703d5a068fe7c604108b69c1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31soc/amd/common/psp_smm: add comments to psp_notify_smmFelix Held
The reasoning behind this and the positive side effects of this aren't too clear from the code, so point those out in a comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4f4121031fc1ef600cdf5551f61f1ef4e03b56a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31soc/amd/common/psp_smm: add/improve comments to buffers and flagsFelix Held
Since it's not exactly obvious what 'c2p_buffer', 'p2c_buffer' and 'smm_flag' are used for, add comments to those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ec092a92fe9f0686ffb7103e441802fc05381f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-07-31device/path: rename domain path struct element to 'domain_id'Felix Held
Rename the 'domain' element of the 'domain_path' struct to 'domain_id' to clarify that this element is the domain ID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Martin Roth <gaumless@gmail.com> Change-Id: I3995deb83a669699434f0073aed0e12b688bf6e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83677 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-07-31device: introduce and use dev_get_domain_idFelix Held
To avoid having constructs like 'dev->path.domain.domain' in the SoC code, create the 'dev_get_domain_id' helper function that returns the domain ID of either that device if it's a domain device or the corresponding domain device's domain ID, and use it in the code. If this function is called with a device other than PCI or domain type, it won't have a domain number. In order to not need to call 'die', 'dev_get_domain_id' will print an error and return 0 which is a valid domain number. In that case, the calling code should be fixed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d79f19846cea49609f848a4c42747ac1052c288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83644 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31soc/intel/adl: Update DCACHE_BSP_STACK_SIZEKarthikeyan Ramasubramanian
During the stages which use Cache-as-RAM (CAR), coreboot needs more than 1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31mb/google/trulo: Keep ISH default enableSubrata Banik
This patch drops fw_config probing for ISH because ISH IP should remains on by default for all Trulo variants. Additionally, removed the redundant ISH entries from variant override devicetree. BUG=b:354607924 TEST=Able to verify ISH PCI Device is available while booting eMMC sku. ``` lspci 00:00.0 Host bridge: Intel Corporation Device 461c ... 00:12.0 Serial controller: Intel Corporation Device 54fc ... 00:1a.0 SD Host controller: Intel Corporation Device 54c4 ``` Also, able to enter S0ix with this patch. ``` > suspend_stress_test -c 1 --ignore_s0ix_substates At AP console: s0ix errors: 0 s0ix substate errors: 0 s0ix pc10 errors: 0 At EC console: power state 5 = S0ix, in 0x38d87 ``` Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31mb/google/brya/var/xol: Using baseboard's PchPmSlpAMinAssert settingsRaymond Chung
Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum time (98ms) from 2sec. BUG=b:349595391 BRANCH=firmware-brya-14505.B Test=Verified on xol Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-30mb/google/brya/var/orisa: Remove redundant defaults from overridetreeRishika Raj
Streamline variant-level overrides by removing redundant entries that already exist in either the SoC-level or the platform-level configurations. BUG=None TEST=emerge-nissa coreboot Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-29i2c/drivers/generic: Add support for including a CDMSean Rhodes
Chip Direct Mapping is exclusive to Windows; it allows specifying the position where a chip is mounted. There are 8 positions and a _CDM method should return 0xabcd0X, where X is the position. Tested by booting Windows 11 on the StarLite Mk V, rotating the device and checking the orientation is correct, where previously, it was inverted. Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81409 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-29soc/mediatek/mt8196/memlayout: Fix the location of BOOTBLOCK commentYu-Ping Wu
The comment for the BOOTBLOCK region should be written right above the BOOTBLOCK declaration. BUG=b:317009620 TEST=none BRANCH=none Change-Id: I7afdf74844a9d97169b4e4a23c3c9c6060e886d9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83649 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27Revert "soc/intel/adl: Guard TWL SoC missing UPDs for build integrity"Subrata Banik
This reverts commit 59ee65d271c7c617bcc240019231da4f0bd04db6. Reason for revert: - Usb4CmMode & CnviWifiCore Upds are available starting with TWL FSP version v5222.01. Therefore, no special handling is required. BUG=b:330654700 TEST=Able to build google/tivviks. Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-07-27mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10Subrata Banik
This change adds a new USB2 Bluetooth device configuration on Port 10 for the Trulo variant. * A new `drivers/usb/acpi` chip is added with: * `desc` set to "USB2 Bluetooth" * `type` set to "UPC_TYPE_INTERNAL" * `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" * `device` referencing `usb2_port10` BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27mb/google/brya/var/trulo: Remove unused Bluetooth deviceSubrata Banik
This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Trulo variant. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83665 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27mb/google/brya/var/orisa: Remove unused Bluetooth deviceSubrata Banik
This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Orisa variant. It also cleans up a redundant newline before the `serial_io_i2c_mode` definition. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83664 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboardSubrata Banik
This patch moves the configuration for integrated Bluetooth functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard. This change is necessary to support the CNVi BT module on Trulo variants. The configuration is skipped for Orisa. Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to support the CNVi BT module. Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for CNVi WLAN has been removed. This change ensures proper Bluetooth connectivity is applicable for all Trulo variants including Orisa and Trulo. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27mb/google/brya/var/orisa: Update fw_config probe for storage devicesRishika Raj
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices. 2. Update fw_config probe to enable/disable devices in devicetree. 3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config is enabled. BUG=None TEST=emerge-nissa coreboot Change-Id: Id3a22aa2206e86fdca6f6fadbc849572890fee58 Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83657 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for OrisaAmanda Huang
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Orisa variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:345112878 TEST=Able to enter S0ix on Orisa eMMC sku after disabling UFS during boot path. Change-Id: I969b0c0c785ed4c408f6fc6de71e7d0c1a1ea27c Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-27arch/arm64/armv8/mmu: Add missing header arch/barrier.hYu-Ping Wu
Also take the chance to sort the headers. BUG=none TEST=none BRANCH=none Change-Id: I9d487a40d0c58c6458b8b7d32b6401093fa417e7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83651 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-27vc/intel/fsp/twinlake: Update FSP headers to v5222.01Varun Upadhyay
- Add Usb4CmMode & CnviWifiCore Upd support in FspsUpd.h - Update UPD Offset in FspsUpd.h BUG=b:354612775 TEST=Able to build and boot google/Tivviks Change-Id: Ia68b6aa90c782a359b594f381e223772a897c6e6 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSSubrata Banik
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Trulo variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. Note: Enabling this config would introduce an additional warm reset during the cold-reset scenarios due to the function disabling of the UFS controller as results we are expecting ~300ms higher boot time (which might not be user visible because `cbmem -t` can't include impacted boot time due to in-between resets). BUG=b:355384185 TEST=Able to enter S0ix on Trulo eMMC sku after disabling UFS during boot path. Able to grep below debug prints while booting the eMMC sku. [INFO ] FW_CONFIG value from CBI is 0x20000000 [INFO ] Disabling UFS controllers ... [INFO ] fw_config match found: STORAGE=STORAGE_EMMC Change-Id: I06a84fa8c3843edae5932e19d394b18b72ace422 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83654 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2024-07-26soc/intel/meteorlake: Remove unnecessary #if ENV_RAMSTAGESubrata Banik
TEST=Able to build google/rex. Change-Id: I0de87a2ff5ecb37f00ec745ad930e83f6356a3fe Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83637 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26ec/system76/ec: Remove RPM calculationTim Crawford
System76 EC since system76/ec@80cfa91b9fd5 ("acpi: Report RPM values instead of raw tachometer values") performs the RPM calculation itself and stores it in EC RAM where previously the raw tachometer values were saved. The SBIOS is no longer required to make the conversion. Change-Id: I82a4e25a8ce0f274b2d98e7ff2b12595acf6c3c5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-07-26mb/starlabs/starbook/rpl: Don't set tcss_aux_oriSean Rhodes
Not setting tcss_aux_ori in devicetree is the same as setting it to zero so remove it. Change-Id: Ia0e90179dd05b23f1f36935be51327250c5a8684 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-07-26arch/riscv: Remove opensbi submodule includesMaximilian Brune
Currently we include a header file from the opensbi submodule. That causes some issues, since we merge outside code with our own. Most recently there have been made attempts to make the coreboot codebase C23 ready. The code that we include from opensbi however causes the build to fail, since it is not C23 ready. This patch effectivily detaches the coreboot codebase from the opensbi codebase and just copies the structure and definitions that we need from opensbi into coreboot. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9d8f85ee805bbbf2627ef419685440b37c15f906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83641 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26commonlib/device_tree.c: Add read reg property helperMaximilian Brune
Add a helper function to read the reg property from an unflattened device tree. It also factors out the common code into a new function called `read_reg_prop`. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7846eb8af390d709b0757262025cb819e9988699 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-26mb/intel/beechnutcity_crb: Update SMBIOS info for type 0,1,2,3Li, Jincheng
Update wake-up type, mainboard feature flags and enclosure type. All other info are used from src/lib/smbios_defaults.c Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-26mb/intel/avenuecity_crb: Update SMBIOS info for type 0,1,2,3Li, Jincheng
Update wake-up type, mainboard feature flags and enclosure type. All other info are used from src/lib/smbios_defaults.c Change-Id: I8e68c057fefa1d408fb8d69fef066cb573c929a4 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83328 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/intel/xeon_sp/gnr: Add dimm_slot configurationJincheng Li
Add sample DIMM slot configuration table for avenuecity CRB and beechnutcity CRB. This table will be used to fill SMBIOS type 17 table. TEST=Boot on intel/avenuecity CRB It will help to update Locator, Bank Locator and Asset Tag with the value described in dimm_slot_config_table Change-Id: I53556c02eb75204994a1bcb42eccb940e83bd532 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibilityRishika Raj
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to 512KB + 32KB, addressing a requirement specified by coreboot where stack usage is higher than 1KB alone. BUG=None TEST=None Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83540 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-26soc/mediatek/mt8188/memlayout: Add a space in SRAM_L2C_START commentYu-Ping Wu
Change-Id: I1888fedcc66ae13c76331d3f2f4465197ae51d35 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-26mb/starlabs/starbook/cml: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: I92765b404508901c7e84fad0bca30489cf69abac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83456 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-26ec/google/chromeec: Drop 'choice' selections for EC and PD firmwareMatt DeVillier
Since the EC and PD firmware sources are now limited to two options - 'none' and 'external' - drop the choice selection and make the EC and PD external options independent. TEST=build google/lulu with external EC binary using existing defconfig Change-Id: Ie37ff3a188b414fd099fbb344858bca4df419086 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83639 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26ec/google/chromeec: Drop ability to build Chrome-EC, PD componentsMatt DeVillier
In preparation for dropping the Chrome-EC submodule, remove the ability for Chrome-EC and PD components to be built as part of coreboot. These components have not been used or buildable for many years. Change-Id: Ibf6bd43e755cf5b4d2aa8a42f38dc52e7023e9b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83638 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-25soc/amd/common/psp_gen2: use MMIO access againFelix Held
Now that we have a get_psp_mmio_base function that will work on all SoCs that use the psp_gen2 code, we can move back to accessing the PSP registers via their MMIO mapping. This sort-of reverts commit 198cc26e4951 ("soc/amd/common/block/psp/psp_gen2: use SMN access to PSP"). When doing SMN accesses from the SMI handler after the OS has taken over ownership of the platform, there's the possibility to cause trouble by clobbering the SMN access index register from SMM. So that should be either avoided completely or the SMI code needs to save and restore the original contents of the SMN index register. The PSP MMIO base will be set up by the FSP before the resource allocation in coreboot and be treated like a fixed resource by the allocator. The first SMI where corresponding handler calls 'get_psp_mmio_base' happens when ramstage triggers the APM_CNT_SMMINFO SMI right after mpinit which happens after the resource allocation. So the PSP MMIO base address is expected to be configured and so the 'get_psp_mmio_base' function will cache the base address and won't need to do any SMN access in subsequent calls that might happen after the OS has take over control. This isn't currently an issue, since the only PSP mailbox command from the SMI handler after coreboot is done and the OS has taken over will be during the S3/S4/S5 entry, and this will be triggered by the OS as the last step after it is done with all its preparations for suspend/ shutdown. There will however be future patches that add SMI-handlers which can send PSP mailbox commands during OS runtime, and so we have to make sure we don't clobber the SMN index register. TEST=PSP mailbox commands are still sent correctly on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I25f16d575991021d65b7b578956d9f90bfd15f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83448 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25soc/amd/common/psp_gen2: return status from soc_read_c2p38Felix Held
This sort-of reverts commit 00ec1b9fc7ba ("soc/amd/common/block/psp/ psp_gen2: simplify soc_read_c2p38") and is done as a preparation to switch back to using the MMIO access to the PSP mailbox registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icca3c7832295ae9932778f6a64c493e474dad507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25soc/amd/common/block/psp_gen2: add get_psp_mmio_baseFelix Held
Add get_psp_mmio_base which reads the PSP MMIO base address from the hardware registers. Since this function will not only be called in ramstage, but also in SMM, we can't just look for the specific domain resource consumer like it is done for the IOAPICs in the northbridge, but have to get this base address from the registers. In order to limit the performance impact of this, the base address gets cached in a static variable if an enabled PSP MMIO base register is found. We expect that this register is locked when it was configured and enabled; if we run into the unexpected case that the PSP MMIO register is enabled, but not locked, set the lock bit of the corresponding base address register to be sure that it won't change until the next reset and that the hardware value can't be different than the cached value. This is a preparation to move back to using MMIO access to the PSP registers and will also enable cases that require the use of the MMIO mapping of the PSP registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/83446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25soc/amd: add SoC-specific root_complex.c to SMMFelix Held
The PSP code introduced in a following patch needs both SoC-specific functions get_iohc_info and get_iohc_non_pci_mmio_regs to also be available in SMM, so add those compilation units to the corresponding target. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e32084b45f07131c80b642bc73d865fc57688a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-07-25soc/amd/*/root_complex: introduce and use domain_iohc_info structFelix Held
Instead of implementing the functions get_iohc_misc_smn_base and get_iohc_fabric_id in the SoC code, move those functions to the common AMD code, and implement get_iohc_info in the SoC code that returns a pointer to and the size of a SoC-specific array of domain_iohc_info structs that contains the info needed by the common code instead. This allows to iterate over the domain_iohc_info structs which will be used in a later patch to find the PSP MMIO base address in both ramstage and smm. TEST=Mandolin still boots and all non-PCI MIO resources are still reported to the resource allocator Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifce3d2b540d14ba3cba36f7cbf248fb7c63483fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/83443 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-25acpi,soc: use is_domain0 functionFelix Held
No need to open-code this when we have a function for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83643 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-25device: move is_domain0 and is_dev_on_domain0 to common codeFelix Held
Move is_domain0 and is_dev_on_domain0 from the Intel Xeon SP code to the common coreboot code so that it can be used elsewhere in coreboot too, and while moving also implement it as functions instead of macros which is more in line with the rest of helper functions in that new file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I954251ebc82802c77bf897dfa2db54aa10bc5ac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83642 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25mb/protectli/vault_[adl_p,bsw]/Kconfig: drop unneeded MAINBOARD_VENDORFelix Held
MAINBOARD_VENDOR is already provided by the Kconfig file on the vendor level, so there's no need to redefine it to the same value at the mainboard level. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icfcbcec005fadb8eaf1b8f90e1d71b3c6ee32088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83640 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-25soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOSYu-Ping Wu
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver accesses VBNV via Bank 0, the bit must be cleared before we can save VBNV to CMOS in verstage. Usually there's no problem with that, because the Register A is configured in cmos_init() in ramstage. However, if CMOS has lost power, then in the first boot after that, the bit may contain arbitrary data in verstage. If that bit happens to be 1, then CMOS writes in verstage will fail. To fix the problem, define vbnv_platform_init_cmos() to call cmos_init(0), which will configure the Register A and therefore allow saving VBNV to CMOS in verstage. [1] 48751_16h_bkdg.pdf BUG=b:346716300 TEST=CMOS writes succeeded in verstage after battery cutoff BRANCH=skyrim Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83495 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25mb/google/nissa/var/riven: Add Fn key scancodeDavid Wu
The Fn key on riven emits a scancode of 94 (0x5e). BUG=b:345231373 TEST=Flash riven, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Iddedd08fc50e8e8e369ce3d73edf0f3077867e87 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83614 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-25ec/starlabs/merlin: Improve accuracy of RSOCSean Rhodes
Multiply before dividing to improve accuracy of the result. Change-Id: I974cad3af4e1f86ae58e90c68db463fc436223af Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83619 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25mb/google/brya/var/trulo: Configure GPIO pins for ramstageSubrata Banik
This patch configures GPIO pins as required for booting the Trulo device from ramstage. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7b540416083a923ba4d2e52aa8edafb4bfb9ac0e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-25soc/amd/psp_verstage: Add -Oz flag for clangYu-Ping Wu
When we tried to add CMOS support to PSP verstage (CB:83495), the clang builds failed on boards with cezanne SoC (such as Guybrush), due to over-sized verstage. On the other hand, there is no such problem for gcc builds on the same boards. Building PSP verstage by clang generates much larger verstage size (81K) compared with using gcc (67K). To unblock adding features to verstage, temporarily enable -Oz for clang builds. Change-Id: I033458556986ade88fb8e68499b632deae4dd419 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-24mb/google/volteer/{delbin,drobit}: Use alias name for DPTF PCI deviceFelix Singer
Change-Id: If514ee7c1174d13b8ca8eb7fd20359e0730a8893 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83525 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24mb/protectli/vault_cml: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: Ie485684747efccb8fb0ab87f10694c52a98f3c88 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83455 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24mb/google/dedede/var/awasuki: Initialise overridetreeWeimin Wu
Initialise overridetree based on the schematics revision 20240715. BUG=b:351968527 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-24soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCsJincheng Li
TEST=Build and boot on archercity CRB No changes in boot log and 'dmidecode' result under centos TEST=Build and boot on avenuecity CRB It will add DMI type 16,17,19,20 Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-24arch/x86/Makefile.mk: Remove obsolete romcc referenceArthur Heymans
No assembly.inc file is being generated by romcc anymore. The -I. was only used in a single place that can use the common -Isrc instead. Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83563 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-24arch/x86: Build all stages using the same functionArthur Heymans
There is no difference in how early and later stages are linked so rename the same function. Change-Id: I458c7c6822b310847e7ab32519fd8d66a90f88f7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-07-24arch/x86: Link ramstage in one stepArthur Heymans
We only use the bfd linker currently but partial linking is not supported by other linkers and is also a problem for LTO. Change-Id: I3b23d86e604229262d7c762e23bb963a0e944b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71910 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23mb/google/dedede/var/galtic: Group fw_config fields togetherMatt DeVillier
No need to have separate sections, and will be cleaner when adding another section in a subsequent patch. Change-Id: I4ad6be9dd67b5adbc9c5b0fcab51ce0c54351173 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-07-23mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670Michał Żygowski
It is a new incoming Protectli product based on Alder Lake-P SoC. More details and documentation will be added later. TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670. Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80501 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23mb/google/rauru: Add MediaTek MT8196 reference boardJarried Lin
Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83573 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoCJarried Lin
Add new folder and basic drivers for Mediatek SoC 'MT8196'. Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for MT8196 SPEC detail. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-07-23mb/google/brya/var/xol: Limit power limits for low/no battery caseSeunghwan Kim
Xol has a shutdown issue on our reliability test environment: - High temperature - No battery condition It needs to have margin for the PL2 and PL4 values from the adapter power, this will limit the PL2/PL4 values up to 30W/40W for xol's 45W power adapter. The new values are confirmed by our power team. BUG=b:353395811 BRANCH=brya TEST=built and verified MSR PL2/PL4 values. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:18000000 <= MSR PL1 (18W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) [When connected 60W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:60000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 [When connected 45W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:45000000 constraint_2_power_limit_uw:45000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-23drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMDYu-Ping Wu
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A is bank selection. Since the MC146818 driver accesses VBNV via Bank 0, the value set in cmos_init() must not contain that bit. To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add an static assertion about the bank selection for AMD. Note that the kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157 BUG=b:346716300 TEST=none BRANCH=skyrim Change-Id: I6122201914c40604f86dcca6025b55c595ef609e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-22lib/smbios: Create SMBIOS type 4 entryJincheng Li
One smbios type 4 should be provided for each CPU instance. Create SMBIOS type 4 entry according to socket number, with a default value of 1. TEST=Boot on intel/archercity CRB No changes in boot log and 'dmidecode' result under centos Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83331 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INTSeunghwan Kim
If user continues to use the touchpad for over 3 minutes on Xol, the pointer movement is stuttering. Touchpad I2C transaction should appear during the interrupt signal level is low, but we could see some more I2C transaction after the interrupt signal(GPP_F14) went to high. We found experimentally that changing the interrupt type to GPIO_INT from APIC_IRQ improved this issue. We are still investigating, would like to apply this change first for Xol's dogfooding. BUG=b:350609957 BRANCH=brya TEST=built and verified there's no stuttering issue on touchpad movement Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-22mb/google/brya/var/trulo: Configure early and romstage GPIOsSubrata Banik
This change adds early and romstage GPIO configurations for the trulo variant, including: Early GPIOs: - GSC (Google Security Controller) - WP (Write Protect) - UART0 (for serial debug) Romstage GPIOs: - Touch Screen early power sequencing CrOS GPIOs: - CROS_GPIO_VIRTUAL - GPIO_PCH_WP BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic1b84f61ef62ddbadc2a45758fb3fce90fce0e88 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83568 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 23:19:36 +0000