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List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update dptf settings for EVT.
BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge
Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update touchpad settings.
BUG=b:342867386
TEST=ensure touchpad is working.
Change-Id: Ibf62470b7fd921065201894a63d7e2a83dad53ce
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Add TPM TIS ACPI interrupt configuration, set teliks's
`TPM_TIS_ACPI_INTERRUPT` to 13.
BUG=b:352263941
TEST=emerge-nissa coreboot
Change-Id: Iaed51e0bb8abac0ed0b35bfcf12e95fd34f92242
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83832
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.
BUG=b:352263941
TEST=DP function of MB and DB workable
Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include
soc/gpmr.h if necessary.
Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83317
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For easier debugging it is useful to have a function that prints the PMP
regions.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6ab1531c65b14690e37aecf57ff441bf22db1ce5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Use 'enum cb_err' instead of {-1,0}.
Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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We introduce two new functions to create region objects. They allow us
to check for integer overflows (region_create_untrusted()) or assert
their absence (region_create()).
This fixes potential overflows in region_overlap() checks in SMI
handlers, where we would wrongfully report MMIO as *not* overlapping
SMRAM.
Also, two cases of strtol() in parse_region() (cbfstool), where the
results were implicitly converted to `size_t`, are replaced with the
unsigned strtoul().
FIT payload support is left out, as it doesn't use the region API
(only the struct).
Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b
Ticket: https://ticket.coreboot.org/issues/522
Found-by: Vadim Zaliva <lord@digamma.ai>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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LAPIC has been available since P54C released 1993.
Change-Id: Id564a3007ea7a3d9fb81005a05399a18c4cf7289
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61794
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables pch_hda_sdi_enable for the trulo baseboard and
removes SDI lanes update from its variants.
BUG=b:350931954
TEST=Boot verified on google/craask and google/tivviks
Change-Id: I2e0f43b8fffb5e583089769d2c7446b476ce5d5d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345373187
TEST=Build and test on google/rex0, check BRDS is shown in SSDT.
Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72
Change-Id: I82f6290cb1934e2c0597286702f93e3789e8f345
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345373187
TEST=Build and test on karis, check BRDS is shown in SSDT.
Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83791
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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This reverts commit 1f1d8d2bcae64baea19d0e947ba5572a45f46eec.
Reason for revert: Intel® Wi-Fi 6E AX211 (CNVi) does not need Bluetooth
Regulator Domain Settings and therefore, the bluetooth companion
device declaration for CNVi is unnecessary.
BUG=b:345373187
TEST=Able to build and boot google/karis.
Change-Id: I296ddb93659af144e1a82a6b8219c9811c5fe545
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83843
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<device/mmio.h> is supposed to chain-include <arch/mmio.h>. See
`Documentation/contributing/coding_style.md` section `Headers and includes`
Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: Iab7e9f3d17c87576761333c4b62c40eea5e424a5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Use of smbios_memory_type needs <smbios.h>.
Change-Id: Iacab6171c61abd047c09ff7e20313a455bd8414f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Refactor EINT driver by
- Move `pos_bit_calc_for_eint` to `common/gpio_eint_v1.c` and rename to
`gpio_calc_eint_pos_bit`.
- Implement `gpio_get_eint_reg` to obtain EINT base address.
This change is prepared for the driver change in MT8196.
BUG=b:334723688
TEST=EINT works on Geralt
Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83703
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. print host software ownership, SMI enable and NMI enable registers
after configuring
2. read and print GPIO configuration dword registers after writing
3. use %zu to print size_t values according to CI reporting.
Change-Id: I8820956f6db91c7bcc26b46a4361da3dfa8f77b5
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
and Stoneyridge which don't use/support this.
If a mainboard has an section named 'PSP_RPMC_NVRAM' in its FMAP file,
the start and length of it in the flash will be passed to amdfwtool
which then adds the base and length to the corresponding type 0x54 PSP
directory table entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9f8a7eec68a5222be63e46173132f1c4a461b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83815
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Devicetree for lenovo/520 is missing USB ports config, hence they
don't work. This change introduces USB port config.
Tests performed:
- Can select a boot media using a USB keyboard from any port.
- Can boot from each port except usb@1:1.1.
- Measured read speed from a thumb drive on each port 24.5-28.9 MiB/s.
Change-Id: I96dba153a563e0e290b96b837fdca39d7598ef17
Signed-off-by: PuFF1k <exopuf@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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As `qemu-q35/memmap.c` includes `qemu-q35/q35.h`, move macros into q35.h
file.
Change-Id: I0bf13def8bc4510053f6bb44e043bbcb0b958b01
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Details:
- Skeleton files to compile google/fatcat mainboard.
BUG=b:348678529
TEST=Build verified on with using PTL SOC and google/fatcat mainboard.
Change-Id: I4c069ba64f487259ce746dc52296618d91209602
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83732
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the tracehub driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is
reserved.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Fn key on jubilant emits a scancode of 94 (0x5e).
BUG=b:324079605
TEST=Flash jubilant, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I963b0aa85598097fea69ec34d1e79ec0bbec3db3
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83821
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since a generic ITE GPIO driver is available and in use, the existence
of chips-specific drivers no longer make sense. Remove the dead code
in favor of generic GPIO driver.
Change-Id: I7e031d12192af4bd47923d87c1d02c64f9c851a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83497
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refactor mainboards' code to use the new GPIO driver.
TEST=Put Google Jecht to S3 sleep and check if the LED blinks.
Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add SAR Sensor SX9324 for WWAN:
- Apply DRIVERS_I2C_SX9324
- Config GPP_H19 for IRQ
- Add SX9324 registers settings based on tuning value from SEMTECH.
Refer to datasheet:
https://chromeos.google.com/partner/dlm/avl/component/3624/
BUG=b:345327104
TEST=Build and verify on jubilant
Change-Id: I629117f20ca513dc0c8eaa91744ad33e162ba4bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83779
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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wifi.SetTXPower test fail, so enable wifi sar.
BUG=b:351698478
TEST=emerge-brox coreboot
Change-Id: Ibf5425e72eddc45e376ef4e2d077180dab502200
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update header files for FSP for Raptor Lake refresh platform to
version 5045_00, previous version being 4435_00.
FSPM:
1. Add IgdGsm2Size UPD
2. Comment added for Offset 0x0AB6
FSPS:
1. Add CepEnable UPD
2. Offset size updated for UPD ReservedCpuPostMemProduction
2. Comment added for Offset 0x104C
MemInfoHob:
1. Structure updated
BUG=b:355384183
Kit:https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=815173
Cq-Depend: chrome-internal:7554984
Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:350844195
TEST=emerge-nissa coreboot
boot with G2 TS, make sure G2 TS is functional.
Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83823
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MKBP device is required for passing events from input sources to AP.
Input sources include buttons (power, volume); switches (lid, tablet
mode) and sysrq.
BUG=b:357521411
TEST=Build coreboot and switch tablet mode on orisa.
Change-Id: Ic712f53fb4063347c38df05167f0100afc06f979
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83819
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change adds support for specifying the CSE_RW_VERSION directly in
Kconfig.
* If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be
used directly as the CSE_RW version.
* Otherwise, the version will be extracted from the CSE_RW binary file
as before.
Platform prior to Intel Meteor Lake still requires to override the CSE
RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading
the CSE RW version from CSE RW partition.
BUG=b:327842062
TEST=CSE RW update successful on Karis with this patch using below
recipe:
1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269"
2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION=""
Platform prior to Intel Meteor Lake would be using #1 and platform
starting with Meteor Lake expected to use #2 recipe.
Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.
* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
* `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
* `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.
BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.
Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Add the support LP5 RAM parts for fatcat:
DRAM Part Name ID to assign
H58G56BK7BX068 0 (0000)
BUG=b:347669091
TEST=emerge-fatcat coreboot
Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
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This change enables storing the ISH firmware version on the Trulo
baseboard by selecting the `SOC_INTEL_STORE_ISH_FW_VERSION` config
option.
BUG=b:354607924
TEST=Able to dump ISH version on trulo.
> cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.7780
Change-Id: I69a7fa19c53f435ef1f6306b259f703c7b196137
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83820
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This adds pmc_dump_soc_qdf_info function and PMC_IPC_CMD_SOC_REG_ACC
PMC IPC Command to read and print Intel SoC QDF information using PMC
interface if SOC_QDF_DYNAMIC_READ_PMC is enabled. QDF read command is
supported from Panther Lake SoC.
QDF is a four digit code that can be used to identify enabled features
and capabilities. This information will be useful to debug issues
found during the development phase and in the field as well.
Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83784
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pass the PSP NVRAM base and size to amdfwtool for all SoCs except Genoa
which doesn't use/support this. This was previously only implemented for
Picasso, but not for the SoCs that support this, so add the support to
those other SoCs as well.
If a mainboard has an section named 'PSP_NVRAM' in its FMAP file, the
start and length of it in the flash will be passed to amdfwtool which
then adds the base and length to the corresponding type 0x04 PSP
directory table entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785ede8eb0df2473a4390b2c305add20f38d7ede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83814
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Move PSP_NVRAM_BASE and PSP_NVRAM_SIZE from the BIOS directory table
items to the PSP Directory Table items, since the corresponding region
will be referenced by the PSP directory table and not the BIOS directory
table.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iff7568ea05c701ecd346cc7590cf93b091ff31a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83813
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Currently a warning is printed even if the maximum amount of nodes is
not exceeded.
Remove the warning, since in most cases the maximum amount of nodes
for a given prefix is usually well known. For example the /cpu nodes
always have a maximum of CONFIG_MAX_CPUS.
One may also just want to read the first X amount of nodes matching a
given prefix.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic1111e8acb72ea1e9159da0d8386f40cbbdbc63f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The Fn key on awasuki emits a scancode of 94 (0x5e).
BUG=b:355538142
TEST=Flash awasuki, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Ic7aa183bf314fed4901133dc70d848d84fab0784
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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1. Change driver form i2c/hid to i2c/generic.
2. Add fw_config for touchscreen.
BUG=b:351968527
TEST=ectool cbi set 6 0x0x10200a0;
touchscreen functions normally;
Change-Id: Ifd6330be8924d4873f0efab3ce404168a62099eb
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83704
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures the GPIO pins to enable ISH on the Trulo device,
in accordance with schematic_20240607.
BUG=b:354607924
TEST=Builds successfully for google/trulo.
Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83781
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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This patch configures the GPIO pins to enable ISH on the Orisa device,
in accordance with schematic_20240607.
BUG=b:354607924
TEST=Builds successfully for google/orisa.
Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83656
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Before 'handle_psp_command' calls any of the functions in this file, it
make sure that the 'size' field in the command buffer's header doesn't
indicate that the command buffer is larger than the SMM memory region
reserved for it.
The read/write command buffer has a 'num_bytes' field to indicate how
many bytes should be read from the SPI flash and put into the data
buffer within the command buffer or how many bytes from this buffer
should be written to the flash. While we should be able to assume that
the PSP won't send us malformed command buffer, we should still better
check this just to be sure.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e8514eedc3ad154a705c8a1e85d367e452dbed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83778
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use coreboot's SPI flash access infrastructure to do the flash read,
write, or erase operations as requested from the PSP.
This patch is a modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I4957a6d316015cc7037acf52facb6cc69188d446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
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Detect the block size of the SPI flash and number of flash blocks
reserved for the flash region corresponding to the 'target_nv_id' field
in the command buffer. This information is then written to the
corresponding fields in the command buffer. Since detecting the flash
chip still might result in accesses to it, make sure that it's available
for use and not currently used by an OS driver. Since this code is
inside the SMI handler, we don't have to worry about this code to be
interrupted, so we don't need to set some bit to tell other code that
we're currently using the SPI controller in the SMI handler.
This patch is a modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83776
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The SPI_SEMAPHORE_DRIVER_LOCKED bit in the SPI_MISC_CNTRL register
doesn't affect the hardware, but it re-used by AMD as a semaphore to
synchronize the access to the SPI controller between SMM and non-SMM
software like an OS-level driver. Since it doesn't affect the hardware,
it's marked as reserved in the PPRs. Add the 'spi_controller_available'
helper function to check this bit to see if some software or driver
outside of SMM is currently using the SPI flash controller to avoid
interfering with that operation.
This patch is a slightly reworked version of parts of CB:65523.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I49218e03a5dd555b2b2d34eaad86673e9fc908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83775
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add 'find_psp_spi_flash_device_region' to get a pointer to the spi_flash
struct of the SPI flash used in the system and the region_device struct
for the target FMAP region specified by the target NV ID from the PSP
to x86 mailbox command. In order to have small patches, the newly added
static 'find_psp_spi_flash_device_region' function is marked as inline;
that inline will be removed in a following patch that calls this new
function.
This patch is a slightly reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I64b8fba2392de46ecd4c786cef0d5b6acdbd865a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83774
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add and use functions to validate the target non-volatile storage ID in
the different command buffer structs.
This patch is a slightly reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: Idda0166c862d41d380b2ed21345eead5e0a1c135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83758
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch is a slightly modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I41efeecf9243ddbbd8dc3f842c5ce11058bb7999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83757
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add stub functions for the SPI flash access from the PSP SMI handler
and call them for the corresponding P2C mailbox commands.
Parts of this patch are taken from CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: Iedbc9d41eb0d4e8d81eeba9c01281161eb839991
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83756
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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When the PSP wants to access the SPI flash during runtime, but isn't the
owner of the SPI flash controller, it sends an SMI to the x86 side. The
corresponding SMI handler then checks the P2C (PSP to core) mailbox for
the command and data, processes the command, and if needed puts the
requested data into the P2C buffer.
The P2C mailbox is a memory region in TSEG aka SMM memory. Both location
and size are communicated to the PSP via the PSP SMM info mailbox
command which is sent right after mpinit is done.
This commit adds the code to access the P2C mailbox to the PSP SMI
handler code, but the handling of the actual mailbox commands the PSP
sends to the SMI handler is added in later patches to keep the patch
size manageable.
This patch is a heavily reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I50479bed2332addae652026c6818460eeb6403af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83740
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
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This register is currently used by the SPI DMA code that sets an
undocumented bit. A later patch will add and use some other bit in this
register.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I48447dcfb3cee07619a9b42434731f0b21458021
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83773
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust Touchpad I2C fall time configuration such that it meets the
I2C fast mode specification(<= 400KHz).
BUG=b:328670295
TEST=Build Brox firmware and boot to OS. Confirm the I2C bus
frequency(375 KHz), rise(650 ns) and fall(330 ns) times meet the
specification.
Change-Id: I0006bfb9bb5839ffa1248d9f2ea055160ed0936e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83755
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
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The property `has_cdm` only existed in an early patchset, the version
that was merged only requires `cdm_index` so remove the former that
was added in c6c75dfbaeff208c17bb47fdede855286e12d857.
Change-Id: I62a9456e9a4f1571328ba6fd09ae383a8fd11767
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83796
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Change-Id: I3161c7d99a2d94d6c85a6c9652b8e78d3f447252
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Clean up the devicetree by removing settings set to 0, which are
initialized with 0 anyway, remove superfluous disabled devices and also
remove comments duplicating the device alias names.
Change-Id: I07005ae1db7d92fd50e72351031a5eb491768d3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83782
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove some unused GPIOs and configurations for GPIO's that
aren't even connected.
Change-Id: I5b4691a0b5e8b1348304d11c1d59aa60517041ec
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83626
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The GPIOs for WiFi and Bluetooth are also connected to the EC.
They are controlled from there so remove the configuration here.
Change-Id: I7aef1b821420daf5ea9f6ae107021e5d406a5ec3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
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The platform uses eSPI so these are not needed.
Change-Id: I81470658263f4b601c9964ff5bed86b22d24df3b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83624
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Use the USB ACPI to add entries for the USB and TCSS ports.
Change-Id: Iab8b6e03c8c05e459fb354bc008109c873a4846f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83623
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that multiple TPM drivers may be compiled in, it is possible to
support switching between fTPM and dTPM.
The patch adds:
- Device tree entry for PC80 discrete TPM
- TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt
- MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver
When the ME is disabled, e.g. via HECI command, chipset will route the
TPM traffic to SPI automatically. When a SPI TPM is connected to the
JTPM1 on the board, it will be probed successfully and initialized
in place of inactive PTT/fTPM.
Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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When both CRB and pc80 TPM drivers are compiled in, building fails
because the tpm_config_t typedef has two incompatible definitions.
Given that typedefs are discouraged by the project's coding style,
simply get rid of the tpm_config_t typedef.
TEST=Compile MSI PRO Z690-A target with CRB and PC80 TPM chips enabled
in devicetree.
Change-Id: Id41717e265362303a17745303a907c9c8f4f4e12
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82057
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Clock Power Management, ASPM and L1 Substates have been
configured the same way since Skylake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since Skylake, this is not the
case for Alder Lake, Raptor Lake and Meteor Lake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On Comet Lake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On Raptor Lake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81638
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/starlite-specification
Change-Id: I8724e578c21353032b844b20b868348580ff561b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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|
Add pad_own_reg_0 to `struct pad_community`. Pad ownership indicates
whether the GPIO is owned by host or Intel Management Engine. If owned
by host, then host ownership indicates whether the GPIO is owned by ACPI
or driver.
Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83315
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300,
P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0.
Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83314
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83192
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Depending on how firmware image was passed to QEMU, it may behave as:
- ROM - memory mapped reads, writes are ignored (FW image mounted with
'-bios');
- RAM - memory mapped reads and writes (FW image mounted with e.g.
'-device loader');
- flash - memory mapped reads, write and erase possible through
commands. Contrary to physical flash devices erase is not required
before writing, but it also doesn't hurt. Flash may be split into
read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd.
Combined size of system firmware must not exceed 8 MiB by default
(FW image(s) mounted with '-drive if=pflash').
This function detects which of the above applies and fills
region_device_ops accordingly.
Tested by starting QEMU with firmware passed as '-drive if=pflash',
'-drive if=pflash,readonly=on' and '-bios'. When started with firmware
passed through '-device loader', coreboot complains about corrupted
FMAP, but this is the same behavior as without this change:
[ERROR] Invalid FMAP at 0x40000
[EMERG] Cannot locate primary CBFS
Writable pflash support was added about 17 years ago, so it should be
supported by all QEMU versions currently in use. Since QEMU 5.0.0 it is
possible to change the limit of firmware size with `max-fw-size` machine
configuration option, up to 16 MiB, as bigger sizes would overlap with
default IO APIC memory range.
Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82555
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
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Since most targets support clang it's easier to reverse the semantics of
the Kconfig options.
Change-Id: Ib28e7a4cb286b9f8b05be94dae3947179f43c746
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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This patch move keymap size calculation inside of
has_alpha_num_punct_keys condition. When the condition is not met,
it can prevent total keymaps size calculate incorrectly.
BUG=none
TEST=emerge coreboot pass
Change-Id: I3dcf31d89924c1a8f2768e42065761b361e9ca41
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Update GPIOs for WWAN and USB Camera functions.
BUG=b:341188351
TEST=Build and verify on jubilant
Change-Id: I145aa994767ddc59be519b96017af71badf82734
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
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Define ISH main firmware name so ISH shim loader can load firmware
from file system.
BUG=b:354607924
TEST=Boot trulo board, check that ISH is enabled and loaded
lspci shows: 00:12.0 Serial controller: Intel Corporation Device 54fc
Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83671
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Match PCIe root port allocation and associated comments to
boardview, as follows:
Z77 PCIe ports 1-4: PCIEX16_3 (x4)
Z77 PCIe port 5: PCIEX1_1
Z77 PCIe port 6: RTL8111F LAN
Z77 PCIe port 7: ASM1042 USB3
Z77 PCIe port 8: ASM1061 eSATA
CPU PCIe lanes 1-8: PCIEX16_1
CPU PCIe lanes 9-16: Multiplexed via 4x ASM1480 to PCIEX16_1 lanes 9-16
and PCIEX16_2 lanes 1-8
(CPU PCIe lanes are not covered by overridetree.cb.)
These are not hardware tested.
Change-Id: I472e28add254ea945b401d1ddfd03f29f46d8fd2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The ID for X10SLM+F is 0811 as reported by Knogle on IRC.
Change-Id: Ie58aad50e66efbc3113541884beea9668d886b5d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Because Awasuki doesn't have SD card, disable related configurations.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: I1b0d2a9c2f9cdd4bca7c30cdc454ffa84b293146
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83706
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The PSP can send SMIs to the x86 side to have the SMI handler service
requests from the PSP. This commit adds an empty PSP SMI handler; the
actual implementation is added in later patches to keep the patches
relatively small.
This patch is a slightly modified version of parts of CB:65523.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83739
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BRANCH=None
BUG=b:348171026
TEST=Test on TI PDC device
Cq-Depend: chromium:5691079
Cq-Depend: chromium:5691080
Cq-Depend: chrome-internal:7464767
Original-Change-Id: I6ffb8bdb2245a74b0d5270435d0ffc8a44e7c2a6
Original-Signed-off-by: Bob Moragues <moragues@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5691110
Original-Reviewed-by: YH Lin <yueherngl@chromium.org>
Change-Id: Iac5b4cd4dcb1d274553f78e9d4295f8f9ad8a863
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Currently resource allocation starts top down from the default value
0xfe000000. This does not match what ACPI reports, so adapt
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I2ba0e96a7ab18d65b7fbbb38b1a979ea2ec6d1be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch introduces the following changes,
- Remove TCSS XHCI (USB 3.x) devicetree settings
- Update Over Current (OC) & USB 2.0 config
- Update TCSS-XHCI capabilities
BUG=b:348332200
TEST=Able to build google/nova and ensure lsusb can list genesys
hub device.
Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83707
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes the PMC MUX related setting from devicetree as Nova
doesn't include a MUX for it's USB-C port.
BUG=b:348332200
TEST=Able to build google/nova
Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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Fix potential undefined behaviour in the `get_pkg_power()` function:
- If `rapl_power_unit == 0`, `pkg_power_info / rapl_power_unit` is
invalid
- If `rapl_power_unit > 7`, the result of the shift doesn't fit into a
`uint8_t`
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I48ef59c4fbeb0a55675ac24da31e6e0b194cb58d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83736
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.
BUG=none
TEST=Able to build and boot google/rex0. Able to see all debug prints
over CPU uart.
Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently we use "%p" to print the address, which results in different
string lengths, depending on the value of the address. To improve
readability of the printed addresses in the log, change the format to
"0x%013lx", so that the length of the printed addresses will be
consistent.
In addition, print the level of the translation table when setting up a
new table.
Example log:
Backing address range [0x0000000000000:0x1000000000000) with new L0 ...
Mapping address range [0x0000000000000:0x0000200000000) as ...
Backing address range [0x0000000000000:0x0008000000000) with new L1 ...
Mapping address range [0x0000000100000:0x0000000130000) as ...
Backing address range [0x0000000000000:0x0000040000000) with new L2
Backing address range [0x0000000000000:0x0000000200000) with new L3
Mapping address range [0x0000000107000:0x0000000108000) as ...
Mapping address range [0x0000000200000:0x0000000300000) as ...
Backing address range [0x0000000000000:0x0000000200000) with new L3 ...
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: Ib29c201e1b096b9c7cd750d2541923616bc858ac
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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These formats are already included in memlayout.ld.
Change-Id: I89d226440308ce3fbe00382698dcd8c88863e694
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Clang does not work that well as a linker for the header as it will
default to other linkers which do not work well here. Instead just use
the linker directly.
Change-Id: Id6ba42b470349a4b138a65b2a037f16a65982ef7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is
enabled and the system is currently booting from the RO section.
Additionally, it integrates forced CSE sync into eSOL decision-making.
BUG=b:353053317
TEST=Verified forced CSE sync on rex0 with GBB 0x200000
Cq-Depend: chromium:5718196
Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds a GBB flag to coreboot, which, when enabled, enforces
CSE sync even if the current CSE version matches the version in CBFS.
The CSME sync GBB and flag are designed to enhance autotest
functionalities and are not intended or recommended for use in
developing any other features.
BUG=b:353053317
TEST=futility gbb --help
Cq-Depend: chromium:5718196
Change-Id: I6352959e1e898a90b4c6e12a22f8d6513f90ded9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83685
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ROTM method should return a package:
```
Name (RBUF, Package (0x03)
{
"0 1 0",
"1 0 0",
"0 0 1"
})
Return (RBUF)
```
Adjust the acpigen to do this.
Change-Id: Id493f6955c1d0dc3449402262a8575091a828226
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Clang builds (bootblock: 20800 bytes) are slightly larger than GCC
builds (bootblock: 18688 bytes) so increase the size of both bootblock
and romstage.
The technical reference manual mentions no upper limit to the size of
the bootblock in the TI header so increasing the bootblock size is
allowed.
To be able to link the clang bootblock increase it from 20K to 22K.
Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The Type-C kernel driver no longer programs the AP mux. So remove device
references to the TCSS Mux control device from the Type-C port driver.
BUG=b:351117685
TEST=USB-C drive can be detected after system warm or cold reboot.
Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The previous uploaded verb table is not fully applied due to
configuration error. Uploaded the verb table provided by Realtek which
can be found in b:336967284.
BUG=b:326412504, b:336967284
TEST=deploy and check volume
Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Terry Cheong <htcheong@chromium.org>
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DC offset of class-D amplifier is 7mV in Brox which is larger than the expected 3mV.
Add a section in the verb table to enable class-D calibration based
on the updated verb table provided by Realtek in b:342506575 comment#6.
This improves the offset to be less than 1mV.
BUG=b:342506575
BRANCH=main
TEST=Verify DC offset of speaker amplier output is less than 1mV with a multimeter when \
playing -100dB sine waves.
Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the jubilant variant of the brox reference board by copying
the template files to a new directory named for the variant.
BUG=b:348543712
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUBILANT.
Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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The PSP can send SMIs to the x86 side of the system. Add helper
functions to configure and to reset the PSP SMI generation. Since
Stoneyridge also selects SOC_AMD_COMMON_BLOCK_SMI, add the SMITRIG0_PSP
define and rename SMITYPE_FCH_FAKE0 to SMITYPE_PSP in its SoC-specific
smi.h to bring it in line with the newer SoCs.
This patch is split out from CB:65523.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I525a447c9a75fdb95b9750e85a02896056315edf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83702
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The Windows drivers require the subsystem ID to match on the PCI
device, so set these to allow the driver to install.
Change-Id: I01b36554d5322018efc72734a8e749cc06263577
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SMRAMC, C_BASE_SEG, G_SMRAME, D_LCK, D_CLS, D_OPEN, ESMRAMC, T_EN,
TSEG_SZ_MASK and H_SMRAME are already defined in included "q35.h" file.
Change-Id: Ic3c01cca14749f77adecc327a78ac011ba3f4c0b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83429
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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acpigen_write_pci_root_port writes SSDT device objects for PCIe
root port, _ADR and _BBN are provided. SSDT objects for direct
subordinate devices will also be created (if detected), _ADR and
_SUN are provided.
TEST=Build and boot on intel/archercity CRB
Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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