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2021-05-21mb/google/mancomb: Enable some PCIe power saving featuresMatt Papageorge
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: I9d6e606763798afc6b797d7d24ee7cae09f9e33f Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21mb/google/guybrush: Enable some PCIe power saving featuresMatt Papageorge
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/puff/var/dooly: Add gpio_keys for mic mute switchBen Zhang
UI monitors this input event and sends global mic mute command to CRAS when the physical switch is toggled. BUG=b:184593945 BRANCH=puff TEST=build image and verify with evtest on DUT. Apply crrev.com/c/2870806 with chrome cmdline flag and verify global mute is triggered. Verify sequences of switch toggle and suspend/resume. Change-Id: Id89947885fdd96c5b5d598bda6db127daf298dc3 Signed-off-by: Ben Zhang <benzh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20drivers/gpio_keys: Add SW_MUTE_DEVICEBen Zhang
Added SW_MUTE_DEVICE event type for mic mute switch. BUG=b:184593945 BRANCH=puff TEST=build image and verify with evtest on puff: /dev/input/event3: mic_mute_switch UI event_device_info receives the proper name. Change-Id: I09c52dc3df63e266c73741b102a22f8a2b896791 Signed-off-by: Ben Zhang <benzh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20drivers/gpio_keys: Add label to set input device nameBen Zhang
Added the label field to the gpio_keys _DSD so that the kernel driver can use a meaningful name instead of the generic _HID PRP0001. BUG=b:184593945 BRANCH=puff TEST=build image and verify with evtest on puff: /dev/input/event3: mic_mute_switch UI event_device_info receives the proper name. Change-Id: I0377851b9cf23bab31930aed6e7de91b4ac3505b Signed-off-by: Ben Zhang <benzh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/asus/p8z77-series: unselect MAINBOARD_HAS_TPM1 from p8z77-m_proBill XIE
MAINBOARD_HAS_TPM1 should not be selected, since the module is replaceable. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ia3790154476b0db54f37e1f3abb91ba5ee891c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-m_pro: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-M PRO remains identical when not adding the .config file in it. Change-Id: I7f1d93e500153a9821e7ddb693d77c864c879f0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-v_lx2: Extract overridetreeAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2 remains identical when not adding the .config file in it. Change-Id: Ia84b07f5fec3c2969134b0d0bc39248d50ac04ff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-series: Always select `INTEL_INT15`Angel Pons
The mainboard.c guard was only added to preserve reproducibility when unifying the boards. The `install_intel_vga_int15_handler` function does nothing when `VGA_ROM_RUN` is not selected. Remove the guard and always select `INTEL_INT15` for simplicity. Change-Id: If38ca49dba81921a3e7abe22542ae74d8914a38d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-m_pro: Transform into variantAngel Pons
To preserve reproducibility, temporarily guard mainboard.c contents. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-M PRO remains identical when not adding the .config file in it. Change-Id: I05e272690ca78f6b9e22b1db1c36cb9e5a7afe3c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-m_pro: Reorder `_PTS` and `_WAK`Angel Pons
Done to preserve reproducibility when switching to a variant setup. Change-Id: I4f3663d3b58c6245c9b73d370a48b8745ea5b95b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8z77-v_lx2: Transform into variant setupAngel Pons
Get ready to squash all Asus Z77 boards together, so as to factor out some redundant code. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2 remains identical when not adding the .config file in it. Change-Id: I701ec4adbc65732ffc0a60d311bf07bf7f414ebf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8h61-m_lx: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX remains identical when not adding the .config file in it. Change-Id: I3142773e8c8f11f27f7926933097ffde8ba241e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54390 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/h61m-cs: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it. Change-Id: I34eb5387fddcb3505c9218b20b706b773e979b0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54389 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/p8h61-m_pro: Switch to overridetree setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: I443d3823e32a246a89ff12e52a0301b2c252e23b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54388 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/p8h61-m_lx3_r2_0: Extract overridetreeAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I989f69d000a38a7b1f4e0832341aa347cc0bfe98 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54387 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/p8h61-m_lx3_r2_0: List all PCH PCIe RPs in devicetreeAngel Pons
Done to preserve reproducibility when switching to overridetrees. The H61 PCH only supports 6 PCIe root ports anyway. Change-Id: I926d62dda512e435d44c0646083c7722427dc80b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54386 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/asus/h61-series: Always select `INTEL_INT15`Angel Pons
The mainboard.c guard was only added to preserve reproducibility when unifying the boards. The `install_intel_vga_int15_handler` function does nothing when `VGA_ROM_RUN` is not selected. Remove the guard and always select `INTEL_INT15` for simplicity. Change-Id: If51a0ab1c57b0856018a62cf669e5d1b53e5333c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/h61-series: Consolidate devicetree SATA optionsAngel Pons
The H61 PCH only supports 4 SATA ports, and does not support Gen3. Change-Id: I3e060ca6904fd6c773c322988a17bbca28333a3d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/h61-series: Relicense devicetrees as GPL-2.0-or-laterAngel Pons
I added these devicetrees in commit 65ddbb720b1 (mb/asus/p8h61-m_pro: Add new mainboard) and commit fe7c2b996bbb (mb/asus/p8h61-m_lx3_r2_0: Add new mainboard). To ease licensing matters when transforming these boards to use overridetrees, relicense the devicetrees so that all of them use the GPL-2.0-or-later license. Change-Id: Id26d0d9dd6cbb81d6a6a263feab7f36ddb4ff6e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-20mb/asus/p8h61-m_lx/devicetree.cb: Rewrite number in hexAngel Pons
Done for consistency with the other variants. Tested with BUILD_TIMELESS=1, Asus P8H61-M LX remains identical. Change-Id: I440706f6fa11d3c2410c445cb7e946c063578c4e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-20mb/asus/p8h61-m_lx: Transform into variant setupAngel Pons
Handle some differences in the DSDT code using preprocessor. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX remains identical when not adding the .config file in it. Change-Id: I2a02f32dfd9fa9c1adce3baf0d279ea19db5883f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-20soc/intel/xeon_sp: Skip locking down TXT related registersArthur Heymans
When locking down TXT is skipped, e.g. to do error injection, locking down DMI3 and IIO DFX related TXT registers should also be skipped. Change-Id: Ieef25c02ec103eaef65d8b44467ccb9e6917bb6c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50238 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Rocky Phagura Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/ocp/deltalake: Implement skipping TXT lockdown via VPDArthur Heymans
This allows to skip TXT Lockdown via "skip_intel_txt_lockdown" VPD parameter. Change-Id: Ic5daf96bdda9c36054c410b07b08bcd3482d777c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rocky Phagura Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-20security/intel/txt: Add weak function to skip TXT lockdownArthur Heymans
RAS error injection requires TXT and other related lockdown steps to be skipped. Change-Id: If9193a03be7e1345740ddc705f20dd4d05f3af26 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-20soc/intel/broadwell: Use Lynx Point IOBP codeAngel Pons
Change-Id: I89832dd6089e1961b4ffdb5661dc98b26a5cb0a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52515 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20sb/intel/lynxpoint: Add pch_iobp_exec() functionAngel Pons
Taken from Broadwell. A follow-up will make Broadwell use the IOBP code from Lynx Point. Change-Id: Iacc90930ad4c34777c8f1af8b69c060c51a123b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52514 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20sb/intel/lynxpoint: Relocate SATA clock gating writeAngel Pons
Do it in the same place as Broadwell. Tested on out-of-tree Compal LA-A992P, SATA still works. Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47034 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/mancomb: Enable GFX HDA deviceIvy Jian
Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in mancomb. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I47cf9a9dc73fd47e390b079bb9eaa14dc364404a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20mb/google/guybrush: Add SoC thermal zoneRaul E Rangel
The time constant values were taken from the zork thermal.asl. BUG=b:186166365 TEST=Boot guybrush to OS and verify logs look correct thermal-0294 thermal_trips_update : Found critical threshold [3641] thermal-0321 thermal_trips_update : No hot threshold thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal LNXTHERM:00: registered as thermal_zone0 ACPI: Thermal Zone [TM00] (33 C) thermal-0200 thermal_get_temperatur: Temperature is 3070 dK Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONERaul E Rangel
This adds the required method to access temperature data from the ChromeEC. BUG=b:186166365 TEST=Boot guybrush to the OS and verify temperatures $ tail /sys/devices/virtual/thermal/thermal_zone*/temp ==> /sys/devices/virtual/thermal/thermal_zone0/temp <== 31900 ==> /sys/devices/virtual/thermal/thermal_zone1/temp <== 34900 ==> /sys/devices/virtual/thermal/thermal_zone2/temp <== 31900 ==> /sys/devices/virtual/thermal/thermal_zone3/temp <== 33900 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54133 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20drivers/acpi: Add a chip driver to generate thermal zoneRaul E Rangel
Given the following device tree entry: chip drivers/acpi/thermal_zone register "description" = ""CPU"" use chrome_ec as temperature_controller register "sensor_id" = "0" register "polling_period" = "10" register "critical_temperature" = "91" register "passive_config" = "{ .temperature = 85, }" register "use_acpi1_thermal_zone_scope" = "true" device generic 0 on end end It will generate the following: Scope (\_TZ) { ThermalZone (TM00) { Name (_STR, "CPU") // _STR: Description String Name (_RTV, Zero) // _RTV: Relative Temperature Values Name (_TZP, 0x64) // _TZP: Thermal Zone Polling Name (_CRT, 0x0E39) // _CRT: Critical Temperature Name (_PSV, 0x0DFD) // _PSV: Passive Temperature Name (_PSL, Package (0x10) // _PSL: Passive List { \_SB.CP00, \_SB.CP01, \_SB.CP02, \_SB.CP03, \_SB.CP04, \_SB.CP05, \_SB.CP06, \_SB.CP07, \_SB.CP08, \_SB.CP09, }) Name (_TC1, 0x02) // _TC1: Thermal Constant 1 Name (_TC2, 0x05) // _TC2: Thermal Constant 2 Name (_TSP, 0x14) // _TSP: Thermal Sampling Period Method (_TMP, 0, Serialized) // _TMP: Temperature { Return (\_SB.PCI0.LPCB.EC0.CREC.TMP (Zero)) } } } BUG=b:186166365 TEST=Boot guybrush to OS and verify thermal zone works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20mb/asus/f2a85-m_pro: Set resources for 2e.bPaul Menzel
The v4 resource allocator logs the error below: […] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed) update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed) update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed) update_constraints: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: f000, Tag: 100 PCI: 00:01.0 14 * [0x1000 - 0x10ff] limit: 10ff io PCI: 00:11.0 20 * [0x1100 - 0x110f] limit: 110f io PCI: 00:11.0 10 * [0x1110 - 0x1117] limit: 1117 io PCI: 00:11.0 18 * [0x1118 - 0x111f] limit: 111f io PCI: 00:11.0 14 * [0x1120 - 0x1123] limit: 1123 io PCI: 00:11.0 1c * [0x1124 - 0x1127] limit: 1127 io ERROR: Resource didn't fit!!! PNP: 002e.b 62 * size: 0x2 limit: fff io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done […] === Resource allocator: DOMAIN: 0000 - resource allocation complete === […] PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io PNP: 002e.b e2 <- [0x000000007f - 0x000000007e] size 0x00000000 gran 0x00 irq PNP: 002e.b e4 <- [0x00000000f1 - 0x00000000f0] size 0x00000000 gran 0x00 irq ERROR: PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree […] So configure it, to use the resources from port 0. TEST=With CB:54669 boot Asus F2A85-M PRO to SeaBIOS/GRUB and Debian’s Linux 5.10.28 Solution-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: Ibfedca96e4b5ad17f99bc84e2fbf7d0a6aad4484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54670 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/kukui: Add rt1015 support for katsuSunway
Modify the value of "SPEAKER_GPIO_NAME" in katsu as rt1015p sdb BUG=None BRANCH=kukui TEST=Speaker can work normally in katsu during firmware stage Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ib3672383ab34bb07b4e5eb7f7e8b4549e13c67b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54642 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20soc/amd/common: Show espi init in logMartin Roth
BUG=None TEST=See espi init messages in the log. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I9f856402ed9a026427d3529e6d61450b0623fe48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54637 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/sarien/var/sarien/hda_verb: Indent unindented commentsPaul Menzel
Change-Id: I2d08fa7506c6230491273f57ee0116927b29abe3 Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/drallion/var/drallion/hda_verb: Correct codec name in commentPaul Menzel
Correct the Realtek ALC3254 codec name in the comment. The name is used in the original commit message, and is also present in the Linux kernel (`sound/pci/hda/patch_realtek.c`). The file was an exact copy of `src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h` added in commit 95370e1f (mb/google/sarien: Add HD Audio verb table). Change-Id: I43cd73a14e07eb4518e3d44b6f81dff5016da721 Fixes: e3443d87 ("mb/google/drallion: Add new mainboard") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20mb/google/sarien/var/arcada/hda_verb: Correct codec name in commentPaul Menzel
Correct the Realtek ALC3254 codec name in the comment. The name is used in the original commit message, and is also present in the Linux kernel (`sound/pci/hda/patch_realtek.c`). Change-Id: Id8a099297bd8bcebf9734e1beee2449fdcca75c5 Fixes: 95370e1f ("mb/google/sarien: Add HD Audio verb table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20soc/intel/xeon_sp: Remove superfluous printkArthur Heymans
This debug output is not very useful. If CONFIG_BOOTBLOCK_CONSOLE is enabled there will already be something else printed on the console before this. Change-Id: I7c6013805497604bb6a42ed4f9fdc594a73c28f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Rocky Phagura
2021-05-20mb/google/mancomb: Enable AMD I2S Machine DriverIvy Jian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. Also configure Audio Co-processor(ACP) to operate in I2S TDM mode. BUG=b:187860242 TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is enabled in the appropriate scope in SSDT. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I528f90d81a418236e512a1e0840ff44c3a3a983e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-20baytrail: Factor out INT15 handlerAngel Pons
The handler is the same on all Bay Trail mainboards. Factor it out. Change-Id: Ia1b6faaca4792cda5f14948d23498182bf4bb2c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54415 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/dedede: move discrete TPM in overridetree for lalalaAaron Durbin
Move discrete TPM in the devicetree to avoid emitting the following message: "Using default TPM ACPI path: '\_SB_.PCI0.LPCB'" There is no corresonding ACPI device for 1f.5 PCI device. Therefore, move the discrete TPM to a device that has the corresponding ACPI device node. Functionality should remain the same. BUG=b:187518267 Change-Id: Ie9ec70336d5651c87f06f8b357abd1bfdb1cc06b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2021-05-19herobrine: Enable macronix SPI configShaik Sajida Bhanu
Enable macronix SPI config on herobrine board. BUG=b:182963902 Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19sc7280: Reserve wlan & wpss dram memory regionsRavi Kumar Bokka
Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19sc7280: memlayout changes for QCSDI & WMM featuresamrab
Change-Id: If5ebcc9a35e0b86321045ef44bb4874144c6402f Signed-off-by: Sudheer Kumar Amrabadi <samrab@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19sc7280: add qclib supportRavi Kumar Bokka
* Qclib_Ver: BOOT.MXF.1.0-00745-KODIAKLC-2 * Chipcode_Release_Tag: r00003.1 Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19soc/amd/common/block/espi_util: Work around in-band reset race conditionRaul E Rangel
When performing an in-band reset the host controller and the peripheral can have mismatched IO configs. i.e., The eSPI peripheral can be in IO-4 mode while, the eSPI host will be in IO-1. This results in the peripheral getting invalid packets and thus not responding. This causes the NO_RESPONSE status bit to be set and cause eSPI init to fail. If the peripheral is alerting when we perform an in-band reset, there is a race condition in espi_send_command. 1) espi_send_command clears the interrupt status. 2) eSPI host controller hardware notices the alert and sends a GET_STATUS. 3) espi_send_command writes the in-band reset command. 4) eSPI hardware enqueues the in-band reset until GET_STATUS is complete. 5) GET_STATUS fails with NO_RESPONSE and sets the interrupt status. 6) eSPI hardware performs in-band reset. 7) espi_send_command checks the status and sees a NO_RESPONSE bit. As a workaround we allow the NO_RESPONSE status code when we perform an in-band reset. BUG=b:186135022 TEST=suspend_stress_test and S5->S0 tests on guybrush and zork. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-19soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settingsFelix Held
I'm not 100% sure if this should rather be duplicated from Picasso or commonized. Checked with the docs and this won't be compatible with Stoneyridge and one future product's PPR lacked the corresponding register. Some other chip has a compatible register layout, but a different number of PCIe GPP clock outputs, so the common code would need to use some SoC-dependent defines and possibly a SoC-specific lookup table for the mapping which is also not that great. TEST=Checked Cezanne PPR Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b6d0cb8d7eb0288d8a18fcb975dc377b2c6846a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54685 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-19soc/amd/picasso: move gpp_clk_req_setting definition to chip.hFelix Held
Since this enum is only used for the devicetree settings and not for the hardware itself, move it from the southbridge header to the chip one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0907fc5cba9315fec5fabff67d279c6d95d1c9f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54684 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-19mb/google/brya/brya0: Manually probe fw_config for DB_LTETim Wawrzynczak
In order to use the USB WWAN module in USB mode (as opposed to PCIe), the PCIe RP must be turned off at the FSP level. The `probe` statement in the devicetree unfortunately takes effect too late, because the UPDs for disabling/enabling PCIE RP belong to FSP-M (romstage), whereas fw_config probing for devicetree is done in ramstage. Add a new variant-specific file which will handle manually setting the UPD based on FW_CONFIG instead. BUG=b:180166408 TEST=set CBI FW_CONFIG field to LTE_USB, see message in console, set field to LTE_PCIE, do not see message in console. Change-Id: Ica2f64ec99fa547e233012dc201577a14f6aa7d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54633 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18ec/google/chromeec: Provide EC access for Retimer firmware upgradeJohn Zhao
coreboot needs to access EC RFWU entry in order to suspend and resume PD and modes setting. This change adds ec_retimer_fw_update implementation for retimer firmware upgrade. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ib937d8bd72fc39487854773573b435bf2add672a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52713 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/intel/shadowmountain: Update mainboard propertiesJohn Zhao
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. BUG=b:186521258 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/volteer: Update mainboard propertiesJohn Zhao
This changes updates mainboard properties by adding DFP number, PLD and power_gpio for each DFP. BUG=b:186521258 TEST=Validated Retimer firmware upgrade along with upstream kernel under no device attached scenario. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I18f29ce5f8450a8b0f8208a60b8b607f9f0d8817 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52714 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18drivers/intel/usb4: Update driver to support Retimer firmware upgradeJohn Zhao
Along with upstream kernel for Retimer firmware upgrade, coreboot provides DFPx under host router where each DFP has its PLD and DSM. The DFPx's functions encapsulates power control through GPIO, PD suspend/resume and modes setting for Retimer firmware update under NDA scenario. BUG=b:186521258 TEST=Booted to kernel and validated host router's DFPx properties after decomposing SSDT table. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I81bef80729f6df57119f5523358620cb015e5406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52712 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/intel/shadowmountain: Remove power_gpio from baseboardJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/volteer: Remove power_gpio from baseboardJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iec2437ab20d283d080752a80aa4514aa9af6897e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52711 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18ec/google/chromeec: Remove ec_retimer_fw_updateJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot changes the ec_retimer_fw_update format. This change removes this API and will add implementation later once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I2d074b84fb3cb87b443871104b72b6c316af5279 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.aslMaulik V Vaghela
We were not adding power management handling of GPIO_COM3 in gpio.asl This can affect s0ix flow where platform won't go into s0ix since GPIO_COM3 is not power gated. BUG=b:188392183 BRANCH=None TEST=Platform should enter to s0ix and GPIO COMM3 should not block an entry to s0ix. Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/brya: Disable dynamic GPIO PM for community 3Maulik V Vaghela
We recently added GPIO definition for PCIE vGPIO for Alder Lake. We also need to disable GPIO dynamic PM for this community which is already done for other communities as well. BUG=b:188392183 BRANCH=None TEST=Code compiles and Check if dynamic PM for GPIO COMM3 is also disabled Change-Id: I2f8645b8f4a9995e727a7623af97531c5de52892 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54383 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-18vboot/secdata_mock: Make v0 kernel secdata contextAseda Aboagye
The new kernel secdata v1 stores the last read EC hash, and reboots the device during EC software sync when that hash didn't match the currently active hash on the EC (this is used with TPM_CR50 to support EC-EFS2 and pretty much a no-op for other devices). Generally, of course the whole point of secdata is always that it persists across reboots, but with MOCK_SECDATA we can't do that. Previously we always happened to somewhat get away with presenting freshly-reinitialized data for MOCK_SECDATA on every boot, but with the EC hash feature in secdata v1, that would cause a reboot loop. The simplest solution is to just pretend we're a secdata v0 device when using MOCK_SECDATA. This was encountered on using a firmware built with MOCK_SECDATA but had EC software sync enabled. BUG=b:187843114 BRANCH=None TEST=`USE=mocktpm cros build-ap -b keeby`; Flash keeby device, verify that DUT does not continuously reboot with EC software sync enabled. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Id8e81afcddadf27d9eec274f7f85ff1520315aaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/54304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-18mb/asus/h61m-cs: Transform into variant setupAngel Pons
To preserve reproducibility, temporarily guard mainboard.c contents. This will be removed once all boards have become variants. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it. Change-Id: I1ffb41470d24713a4a7f0689958b733d4b1bdf52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/p8h61-m_pro: Transform into variant setupAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: Iaa53a8a1b75f4c7359e32c6cd8c8a488c5763bbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/p8h61-m_lx3_r2_0: Transform into variant setupAngel Pons
Get ready to squash all Asus H61 boards together, so as to factor out lots of redundant code. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I738197bf4d5ea8b879ae26ecbcb0cf3714316662 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18mb/asus/{h61m-cs,p8h61-m_lx}: Reorder `_PTS` and `_WAK`Angel Pons
Done to preserve reproducibility when switching to a variant setup. Change-Id: I78241c807f767846774b8e1a2e0d25f3452ed544 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-18Asus H61 boards: Align dsdt.asl with other boardsAngel Pons
Prepare to transform Asus H61 boards into a variant setup. Change-Id: Ifd5808edac22ebdba9b29a711ad129b91d9975d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-05-18mb/asus/h61m-cs/Kconfig: Sort selectsAngel Pons
In preparation to switch the Asus H61 boards to a variant setup, sort the `select` lines in Kconfig alphabetically. Change-Id: I91ee7dc601f1fc52a7d68f66555143156b91ebf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54365 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/p8h61-m_lx/Kconfig: Sort selectsAngel Pons
In preparation to switch the Asus H61 boards to a variant setup, sort the `select` lines in Kconfig alphabetically. Change-Id: Ia5a8d36f78db2262b4c8d48cbb4dd16718d01475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54364 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/p8h61-m_pro/Kconfig: Sort selectsAngel Pons
In preparation to switch the Asus H61 boards to a variant setup, sort the `select` lines in Kconfig alphabetically. Change-Id: I96486d57250e901d872e4ef12967c2aadd9791ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54363 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/asus/p8h61-m_pro: Relicense gma-mainboard.adsAngel Pons
Commit 65ddbb720b1 (mb/asus/p8h61-m_pro: Add new mainboard) added this file, and I authored this commit. Since most gma-mainboard.ads files are licensed as GPL-2.0-or-later, relicense this one for consistency. Change-Id: I2d28150f4c97ba600cb46fead7bb29cdc65c5baf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54362 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18LGA1155 boards: Drop `VGA_BIOS_{FILE,ID}` for iGPUAngel Pons
These boards have a socketed CPU, and the PCI device ID for the iGPU depends on the installed CPU. Specifying a default doesn't make sense. Change-Id: Iee6749e4fb691f09664cc6ffb3cbf66e4230fa9c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54361 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbolAngel Pons
Mainboards with variants may not always use the same cmos.layout file. Turn the hardcoded path into a Kconfig symbol to allow changing it. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom and with `USE_OPTION_TABLE` selected, building for the Asus P8H61-M PRO produces an identical coreboot image. Change-Id: I4cc622dcb70855c06cb8a816c34406f8421180df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54366 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mainboard: Use decimal for `device lapic 0x0 on`Angel Pons
Most boards use `device lapic 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18mainboard: Use decimal for `device domain 0x0 on`Angel Pons
Most boards use `device domain 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18mainboard: Use decimal for `device cpu_cluster 0x0 on`Angel Pons
Most boards use `device cpu_cluster 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I083c8f8e9b38ddcc217dc8bf17ae3c9473ba77e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask definitionMaulik V Vaghela
Definition for NAV_FWE BIT was added in commit e6e8b3d Even if try to set this BIT it was not getting set since PAD_CFG_DW0 mask will make it 0 since this bit was not part of mask. Adding NAV_FWE to mask will resolve this issue and BIT will be set/unset as per programming in mainboard. TEST=Check GPIO register dump and see if BIT is getting set properly. Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54350 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/dedede: To support ELAN Touchpad device on I2C0Alex1 Kao
Add ELAN Touchpad device under I2C0 BUG=b:188373661 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: I15b9cb0d0276b5e2dd06694530cc35e5643efb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52936 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/brya: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIGDtrain Hsu
Enable/disable LTE function based on LTE bit of FW_CONFIG. The LTE function settings are included GPIO settings, USB port settings and power off sequence. BUG=b:187797408 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-18mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ecMaulik V Vaghela
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps rebooting with hash error. Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-18mainboard: Drop useless `acpi_tables.c` filesAngel Pons
The `tcrt` and `tpsv` values in GNVS can be used to implement thermal management in ACPI. However, not all mainboards use these values. On mainboards where `tcrt` and `tpsv` are not used in ACPI tables and are the only values set in the `mainboard_fill_gnvs` function, remove them as well as the entire `acpi_tables.c` file. Most files come from autoport, which unconditionally generates this file. Change-Id: If2315ddd9700e2da0a24ffecc20acb5c1a1d688e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-18mb/ocp/deltalake: Rearrange slot table for remapping type 9 Slot IDJohnny Lin
Change-Id: I07bdf7f85f8411e04da8a94da7de1e7b93c9e921 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-05-18mb/google/cherry: Pass reset gpio parameter to BL31Yidi Lin
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=execute `echo b > /proc/sysrq-trigger` to reboot system Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-18soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWAREYidi Lin
Enable ATF configuration to support multi-core. TEST=boot to kernel with multi-core support. BUG=b:177593590 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/53898 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16soc/amd/*/Makefile.inc: Strip the quotesZheng Bao
PSP_SOFTFUSE_BITS used to be like this: 15 0 29 "28 6" It causes internal shell report error: /bin/sh: -c: line 0: unexpected EOF while looking for matching `"' /bin/sh: -c: line 1: syntax error: unexpected end of file /bin/sh: -c: line 0: unexpected EOF while looking for matching `"' /bin/sh: -c: line 1: syntax error: unexpected end of file Change-Id: I716f19d37fb57b9ef3fc7259c6dcca7d21022d32 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-16soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik
DisableDimmMc0Ch0 upds changed to DisableMc0Ch0 in new FSP releases. The definition of the upd also changed. Changed FSP meminit code to work based on new definition of the UPDs. Before: 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs After: 0:Enable, 1:Disable TEST=Boot to OS Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec Reviewed-on: https://review.coreboot.org/c/coreboot/+/54036 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar
The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16sb/intel: Drop outdated SMBus I/O BAR commentAngel Pons
The SMBus I/O bar is not relocated because it's reported to the allocator as a fixed resource. Drop these out-of-date comments. Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-16vboot/secdata_tpm: Create FWMP space in corebootAseda Aboagye
This commit has coreboot create the Chrome OS Firmware Management Parameters (FWMP) space in the TPM. The space will be defined and the contents initialized to the defaults. BUG=b:184677625 BRANCH=None TEST=emerge-keeby coreboot Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
2021-05-16vboot/secdata_tpm: Rename set_space()Aseda Aboagye
The name `set_space()` seems to imply that it's writing to a TPM space when actually, the function can create a space and write to it. This commit attempts to make that a bit more clear. Additionally, in order to use the correct sizes when creating the space, this commit also refactors the functions slightly to incorporate the vboot context object such that the correct sizes are used. The various vboot APIs will return the size of the created object that we can then create the space with. BUG=b:184677625 BRANCH=None TEST=`emerge-keeby coreboot` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I80a8342c51d7bfaa0cb2eb3fd37240425d5901be Reviewed-on: https://review.coreboot.org/c/coreboot/+/54308 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16nb/intel/gm45: Guard even more macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-16mb/google/mancomb: enable DDI0-DP portIvy Jian
Configure DDI-0 connector type to DP. BUG=b:187856682 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-14mb/google/volteer: Configure TCSS OC pinsNick Vaccaro
TCSS OC pins have not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design. BUG=b:184660529 TEST="emerge-volteer coreboot" compiles without error. Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-14mb/google/cherry: Add DRAM calibration supportRex-BC Chen
Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-05-14mb/google/dedede/var/boten: Modify DPTF parametersStanley Wu
DPTF parameters from thermal team. 1. Modify TSR1 sensor as charge sensor. 2. Modify P-state parameter BUG=b:180641150 BRANCH=dedede TEST=build and verified by thermal team. Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52755 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/zork: update DRAM table for berknip/dirinboz/gumbozKevin Chiu
Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb index was generated by gen_part_id BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-05-14mb/amd/majolica: Disable IO ports 0x60/0x64Raul E Rangel
I suspect there is additional initialization required to enable the 8042 keyboard controller on the EC. By removing the range we no longer encounter long 20 second delays when reading the IO ports. Since depthcharge polls the IO ports it makes it seem like depthcharge locked up. BUG=b:182100027 TEST=Boot majolica with depthcharge to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 07:17:47 +0000