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2018-08-30soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()Richard Spiegel
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefore code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-30mb/google/octopus: Add missing IOstandy settings.Shamile Khan
Also removed internal pull ups for CX_PREQ_L and CX_PREQ_L signals as they have external pull ups. BUG=b:110654510 TEST=On Yorp Proto 2, flashed image and verified that it boots to OS. Checked Wake-on-Wifi works with both cnvi and pcie modules. Also executed a few suspend resume cycles. Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/28328 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela
PMC base address is different for CNP LP pch and CNP H pch. Added logic to determine PMC base addrress dynamically based on PCH ID. BUG=none BRANCH=none TEST=Boot Coffeelake U RVP board and check if PMC base address is determined correctly. Change-Id: I833395260e8fb631823bd03192a092df323250fa Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27523 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30drivers/intel/gma: Fix OpRegion Mailbox3 backlight changeNico Huber
We should always update BCLP, no matter if the driver is ready yet to process the request. This way it will hold the current value when the driver initializes. Change-Id: I4b091d744f95da39abe542966f0a8589a187573b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-30drivers/intel/gma: store uint8_t brightness values in mailbox3Alexander Couzens
The _BCM function requires a percentage value. While the brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%. Previous implementation stored the percentage brightness value resulting in limiting the brightness to ~40% of it's maximum power. Only affects brightness control using mailbox3. Fixes: 6838aaebf9ec ("drvs/intel/gma/acpi: Add methods to use MBOX3") Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-29mainboard/google/kahlee: Enable EC firmware update screenMartin Roth
Grunt takes a few seconds to update the EC, so display a notification screen while that's happening. BUG=b:113286040 TEST=Boot Grunt with old EC firmware, see update screen Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28lib/gpio.c: Validate num_gpioRichard Spiegel
In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return of an undefined value, as no for loop will be executed. Assert that it's not 0. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28mb/google/octopus/variants/meep: Add weida touchscreen supportTony Huang
Add weida touchscreen support BUG=none BRANCH=master TEST=emerge-octopus coreboot, and verified that touchscreen works on meep. Change-Id: I4352322820237e4c2289410af6643e15109060a1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28acpi: Hide Chrome and coreboot specific devicesDavid Wu
Some ACPI interfaces introduced by Chrome or coreboot do not need drivers outside ChromeOS, for example Chrome EC or coreboot table; or will be probed by direct ACPI calls (instead of trying to find drivers by device IDs). These interfaces should be set to hidden so non-ChromeOS systems, for example Windows, won't have problem finding driver. Interfaces changed: - coreboot (BOOT0000), only used by Chrome OS / Linux kernel. - Chrome OS EC - Chrome OS EC PD - Chrome OS TBMC - Chrome OS RAMoops BUG=b:72200466 BRANCH=eve TEST=Boot into non-ChromeOS systems (for example Windows) and checked ACPI devices on UI. Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1078211 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28eve: Specify a unique ID for PS2 devicesLucas Chen
Windows certification tests will fail if the PS2 devices are using Plug and Play ID (PNP0303). For all Chromebooks we should use GOOG000A. BRANCH=eve BUG=b:110066056 TEST=AltOS certification test verify. Change-Id: I479471fdb3102e3b492612a4e6ad07612273083a Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1098874 Reviewed-by: Matt Delco <delco@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28334 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28fsp/fsp2_0/coffeelake: Update CFL FSP headersLijian Zhao
Coffeelake FSP headers had been updated to version 7.0.3D.60. Original file location from https://github.com/IntelFsp/FSP/tree/master/ CoffeeLakeFspBinPkg/Include . BUG=N/A TEST=Build and flash, able to boot up into OS on whiskeylake rvp platform. Change-Id: I656da83e9042642576b785643e423ba47da8dd73 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28286 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Init SPI bus for ECTristan Shieh
Set EC SPI bus config and init SPI bus according to the config. BUG=b:80501386 BRANCH=none TEST=EC is not working yet. This makes depthcharge go forward a little. Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28251 Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Set up GPIOs for ChromeOSTristan Shieh
Set up EC interrupt GPIO to boot depthcharge. Without this patch, depthcharge will fail to detect EC interrupt GPIO. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC interrupt GPIO. Change-Id: I0ec2c70c189a059219954e0384aaf98995285728 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-28vendorcode/amd/pi/00670F00: Remove IDS headersRichard Spiegel
Only Ids.h had definitions still in use, and they were removed or moved to AGESA.h. Now Ids.h, IdsPerf.h and IdsLib.h can be safely removed. BUG=b:112885948 TEST=Build grunt Change-Id: I031ae8eb5f34fee801365fc89ea11a881211e726 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28299 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.hRichard Spiegel
Google is creating code to measure AGESA performance, which needs structure TP_Perf_STRUCT and associated definitions. In preparation to remove IDS headers, move the necessary definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHzKevin Chiu
Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warm reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28src/drivers/pc80/pc: Remove unneeded includeElyes HAOUAS
Change-Id: Ic238181d5c26ab8cf549137824a7c5e6c6d80ab1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-27drivers/intel/wifi: Make WIFI_SAR_CBFS user visibleFurquan Shaikh
This change makes WIFI_SAR_CBFS user selectable option so that it can be enabled/disabled from menuconfig along with the SAR filepath. BUG=b:112425861 Change-Id: Idf6feaefe68e7ebf6786c2c36e92a054fba4483c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-27vendorcode/amd/pi/00670F00: Transfer IDS_CALLOUT to AGESA.hRichard Spiegel
Currently, IDS_CALLOUT macros are only used in stoneyridge callout. In preparation to remove IDS headers, move the definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: Ia9717eb68fed2e568eaf169157c2837bb8232b7e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-27mb/google/poppy/variants/atlas: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:113101335 BRANCH=atlas TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU0: Package temperature above threshold' Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619 Reviewed-on: https://review.coreboot.org/28325 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/poppy/variants/nocturne: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:67459049 BRANCH=nocturne TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU3: Package temperature above threshold' Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458 Reviewed-on: https://review.coreboot.org/28324 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27vendorcode/amd/pi/00670F00/Include/Ids.h: Remove IDS_ERROR_TRAPRichard Spiegel
The macro IDS_ERROR_TRAP is only defined, and never used. Also, IDSOPT_ERROR_TRAP_ENABLED is defined FALSE, so the macro would translate to nothing. Remove the macro and IDSOPT_ERROR_TRAP_ENABLED. BUG=b:112885948 TEST=Build grunt Change-Id: I2c3ca4b0a4a1f96f245ba2f4902fd0051dda77ef Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove IdsErrorStopRichard Spiegel
Function IdsErrorStop() is only used within AmdLib.c function LibAmdMsrRead(), which in turn is only used once within PspBaseLib.c and three times inside AmdLib.c, all with well defined MSR addresses. IdsErrorStop() is used as a trap if MSR address is 0 or 0xFFFFFFFF, which clearly it's not. Therefore it can be safely removed from AmdLib.c. BUG=b:112885948 TEST=Build grunt Change-Id: I47ffcbd4fbae28b6d711a340f0ac3f3b007e8e4f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27mb/google/octopus/variants/baseboard: Update DPTF parametersSumeet Pawnikar
Update TSR1 trip point from 48C to 50C. Also, change power limit2 minimum value from 8W to 10W. These are the values as per recent thermal tuning. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28187 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27lib/nhlt: Use common function to set NHLT versionMarc Jones
Set NHLT version with get_acpi_revision(NHLT) to keep all table versions in sync. Change-Id: I4ea9d511142e4ea68e651e58c2c985e739c032d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28279 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/kahlee: Fix I2C bus 0 timing for GruntAkshu Agrawal
This commit fixes the values and thus fixes the issue of audio device not getting detected on random reboots. Change-Id: I34a4f62815d192005c3324d4f71b0aba377fe738 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/28280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-08-27mb/supermicro/h8qme_fam10: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: Ie3ee4acfd272991133f02a56df6e23aa6071d3e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27mb/kontron/986lcd-m: Use common pnp_{enter,exit} functionsElyes HAOUAS
Some unneeded includes are also removed. Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27intel: Use common HPET table revision functionMarc Jones
Use get_acpi_table_revision(HPET) to keep all table versions in sync. Change-Id: Idb5e8ccd49ec27f87a290f33c62df3c177645669 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27x86/acpi: Update MADT table versionMarc Jones
Update the MADT table version to sync with the FADT table version. All current coreboot FADT tables are set to ACPI_FADT_REV_ACPI_3_0 and the MADT should be set to match. This error was found by running FWTS: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27update all FADT version 3.0 to use the get tables functionMarc Jones
Most FADT report using ACPIv3 FADT table. Using the get revision function keeps the table versions in sync. Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27x86/acpi: Add ACPI table revision functionMarc Jones
Use a single function to set ACPI table versions. This allows us to keep revisions synced to the correct levels for coreboot. This is a partial fix for the bug: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28276 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27vendorcode/amd/cimx/sb*: Rename RSDP headerMarc Jones
Rename RSDP to RSDP_HEADER to match other AMD vendorcode and to not pollute the namespace. We will use RSDP in a future patch. Change-Id: I3b66135ae1732b86b5ebfcdc01a850a0d9d3eb50 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27siemens/mc_apl1: Disable PCI clock outputs on XIO bridgeMario Scheithauer
This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridge. Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-27mb/google/octopus: add Digitizer and Synaptics Touchpad for bobbaPan Sheng-Liang
add device "WCOM Digitizer" and "Synaptics Touchpad" for bobba BUG=none BRANCH=master TEST=emerge-octopus coreboot Change-Id: Ie0bf8ebab6d9cb9c8fe42a500efaa3d11ae359db Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-25mb/intel/coffeelake_rvp: Remove superfluous header fileArthur Heymans
TEST: same sha256sum with BUILD_TIMELESS=1. Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-08-25Revert "drivers/spi/spi_flash: don't allocate unbounded stack memory"Patrick Georgi
This reverts commit c5ee35ff861fe4447fd80119f645fba7bfd3a184. Reason for revert: breaks boards, uncertain if it _really_ works. Change-Id: I9ba2ba877b9a391306f89295c0c1d0e2d011c5ea Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28338 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jean Lucas <jean@4ray.co> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-24siemens/mc_apl1: Select DDR50 mode for eMMCMario Scheithauer
To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed to DDR50 mode. Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-24soc/intel/apollolake: Make eMMC max speed configurableMario Scheithauer
The eMMC maximum speed is set to HS400 mode per default. To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed. Change-Id: I6fa5eb56a0593e24269ef143645c506232879889 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28282 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-24soc/cn81xx: Add vboot supportPhilipp Deppenwiese
* Add VERSTAGE and VBOOT_WORK to memlayout. * Add hard and soft reset. * Add missing makefile and kconfig includes. Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-24soc/cavium/cn81xx: Don't directly manipulate devicetree dataPatrick Rudolph
As preparation to constify devicetree data, do it the right way. Change-Id: I5081de020bb73c56aa8bdf7bb17fe6b2913d0ffe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-24device_tree/fit: Constify data structuresPatrick Rudolph
* Add const quailifier to arguments and elements. * Add casts where necessary in cn81xx/soc. Tested on Cavium CN81xx EVB SFF. Change-Id: Id27966427fb97457fe883be32685d1397fb0781f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-23Kconfig, Makefile.inc: Remove all traces of ifdfakeAngel Pons
Since ifdfake has been deprecated in favor of better alternatives, there is no need to support it any further. Remove it from the build system. Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28233 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23mb/google/poppy/variants/nocturne: enable "Base Attached Switch" deviceDmitry Torokhov
This enables CBAS device on Nocturne to allow hid-google-whisker driver in kernel properly detect device configuration. Change-Id: I5905a2de208e94062f2768a9b7d22147f85c7f38 Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/28262 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23google/chromeec: Add support for "base attached switch" deviceDmitry Torokhov
On some detachables, the mere presence of attached base is not enough to determine whether the device is in tablet mode or not, so we introducing a new "switch" in EC, separate from "Tablet Mode" switch, to signal whether the base is attached or not. We also want the driver to be separate from cros_ec_keyb, so we create a new ACPI device, C(hrome)B(ase)A(ttached)S(witch), with HID GOOG000B, and guard it with EC_ENABLE_CBAS_DEVICE. Change-Id: Id73a12f04a1a48f7fbd9365c2a501afadf3878fa Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/28260 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboardMario Scheithauer
For the 1st redesign of mc_apl1 mainboard some adjustments are necessary: - The FPGA is now connected directly via a PCIe Root Port - Internal Apollo Lake UARTs are now used - Adjusting GPIO settings Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-23siemens/mc_apl1: Move board specific things to mc_apl1 variantMario Scheithauer
A FPGA is not necessarily available in further mc_apl1 variants. So we move the loading of the driver and the notify function to the mc_apl1 variant. Setting the CPU to Max Non-Turbo Ratio is also not absolutely necessary for further variants. Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-23mb/foxconn/d41s: Add mainboardArthur Heymans
This supports the Foxconn d41s, d42s, d51s, d52s. The following is tested (SeaBIOS 1.12 + Linux 4.9) and works: - COM1 - S3 resume (with SeaBIOS needs sercon disabled) - Native graphic init on VGA output - SATA - USB - Ethernet - PS2 keyboard The base for this mainboard port was the Intel D510MO port. Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28227 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23mb/google/octopus: Add null pointer checkJohn Zhao
src/mainboard/google/octopus/mainboard.c Function dev_find_slot may return NULL, check before its usage. Found-by: klockwork BRANCH=None TEST=Built & booted Yorp board. Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28235 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23drivers/spi/spi_flash: don't allocate unbounded stack memoryPatrick Georgi
This open-codes flash_cmd, but until the API is fixed for real, it uses xfer's existing scatter-gather ability to write command and data in one go. BUG=chromium:446201 TEST=emerge-coral coreboot succeeds Change-Id: Ic81b7c9f7e0f2647e59b81d61abd68d36051e578 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-23mb/google/octopus/var/meep: Update GPIO config for meepWisley Chen
The change updates GPIO configuration for meep. 1. Update touchscreen power enable GPIO in devicetree. 2. Provide default override tables for GPIO configuration. BUG=b:112955087 TEST=Boot on meep proto board with Intel (Jefferson Peak) wifi card. Change-Id: Idb4e7a510eef15c2e118058d5848080782f4f665 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/28252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-22nb/intel/*/gma.c: Skip NGI when VGA decode is not enabledArthur Heymans
Writes to VGA MEM and IO by NGI are invalid if the IGD is not decoding them. Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-22soc/intel/apollolake: Fix logical vs. bitwise operatorJohn Zhao
src/soc/intel/apollolake/chip.c Apply bitwise operator instead of logical one. Found-by: Coverity Scan BRANCH=None TEST=Built & booted Yorp board. Change-Id: I36746b04dec889f53c8d7eeb3b1d8118eff1de42 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22src/mainboard/*: Remove IFD_*_REGION values for ifdfakeAngel Pons
Since ifdfake has been deprecated in favor of better alternatives, such as flashrom IFD parsing. Therefore, there is no need to support ifdfake any further. Remove the IFD_*_REGION values on the few motherboards with them. Change-Id: Ie07116a7fb960c6ca832d802016f22c6677baac9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28232 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-22soc/amd/stoneyridge/smihandler.c: Report pending wake eventRichard Spiegel
There's a small window of opportunity when CPU is already in SMM but has not yet entered S3 for a wake event to happen, which would cause a failed S3 entry. Check for pending events at the very last moment possible, and if there are pending wake events report them. BUG=b:111100312 TEST=build and boot grunt. Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22drivers/elog/elog.c: Create extended eventRichard Spiegel
For debug reasons, sometimes you not only want to log an event, but also some extra information that would help debugging. Create an extended event reporting event type with a dword complement, and define extended events for failing to enter S3 due to pending wake event (one for pm1 and one for gpe0). BUG=b:111100312 TEST=Add a fake pending wake event, build and boot grunt, see the event in eventlog.txt. Change-Id: I3e8df0953db09197d6d8145b0fc1e583379deaa5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-22acpi: remove CBMEM_ID_ACPI_GNVS_PTR entryJoel Kitching
Since we can retrieve the address of ACPI GNVS directly from CBMEM_ID_ACPI_GNVS, there is no need to store and update a pointer separately. TEST=Compile and run on Eve Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea Reviewed-on: https://review.coreboot.org/28189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-22lib/fit_payload: Add coreboot tables support for FDT.Philipp Deppenwiese
Copy code of depthcharge boot/coreboot.c and adapt it. Tested on Cavium CN8100 EVB SFF, /sys/firmware/log is readable and prints the log. Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-22mb/google/octopus/variants/bobba: Apply new GPIO configs for bid >= 2Furquan Shaikh
This change updates the board id check for version >=2 to apply new GPIO configs. BUG=b:112618194 Change-Id: I3544c9596c465615818d2040682e554a64fc6b1a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28263 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-21nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.cPatrick Rudolph
There's nothing Sandy Bridge specific in this code. Make it available on all platforms to reduce code duplication. Tested on Lenovo T430: SMBIOS entry 17 is still valid. Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21security/tpm: Fix TPM 1.2 state machine issuesPhilipp Deppenwiese
* Fix ACPI resume path compilation for TPM ramstage driver * Move enabling of the TPM prior activation and remove reboot return status from TPM enable. More information can be found via the TCG specification v1.2 Tested=Elgon Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28085 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-21superio/ite/it8721f: Add SuperIO ACPI declarationsArthur Heymans
Change-Id: I074d57fa5b140b6946ae81beb210fefac48a66eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21superio/ite/it8721f: Add resourcesArthur Heymans
There is no public datasheet available for this SuperIO so the resources are guessed by looking at other ITE SuperIO's and the register dumps while running vendor firmware. The only board with this SuperIO in the tree is the asus m5a88-v. Most of the devicetree entries would have been invalid here so one should not worry too much about regressions. Tested with Foxconn d41s. Change-Id: I6715c68b3aa9aebf6e292975cbf64ce905b30e8b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21nb/intel/pineview: Use a common MMCONF_BASE_ADDRESSArthur Heymans
This should not be board specific. Change-Id: Ifa617e84af767f33a94f1ddfa7d4883c1a45198f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-21nb/intel/pineview: Use the correct address for the RCVEN strobeArthur Heymans
When doing the receive enable training, the final mapping of the ranks is already done, so we can be sure that that address 0x00000000 there will always be a rank. Change-Id: I7ac017a8816fc9a47cef0695826a1c32f699f6f8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21nb/intel/pineview: Use i2c block read to fetch SPDArthur Heymans
With this the time spend during the raminit decreases from ~480ms to ~126ms. Change-Id: Ic23f39f1017010c89795e626f6a6f918f8bda17a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21soc/intel/skylake: Remove unsupported sleepstates in ACPI tableLucas Chen
Some OS certification test (for example Windows) will fail if there are unsupported sleep states. Since these states are not really used today, we can remove them from ACPI table. BRANCH=eve BUG=b:72197653 TEST=certification system sleep test pass. Change-Id: I5f5122cac1bf61f7c580afb18cc66b5ff07286fb Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1065401 Commit-Queue: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://review.coreboot.org/28080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20vendorcode/amd/pi/00670F00/Lib: Remove unused functionsRichard Spiegel
The only code still used are LibAmdPciRead() and LibAmdPciWrite(). These functions are used by PspBaseLib. Remove all functions that are not used, directly or indirectly, by LibAmdPciRead() and LibAmdPciWrite(). BUG=b:112688270 TEST=Build grunt Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28194 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20vendorcode/amd/agesa/f15tn: add Richland RL-A1 to the equivalence tableMike Banon
This small change is required for the successful loading of microcode from F15TnMicrocodePatch0600110F_Enc.c for the Richland RL-A1 CPUs, such as A10-5750M found at coreboot-supported Lenovo G505S laptop. Richland RL-A1 and Trinity TN-A1 CPUs are using the same microcode, so the Richland RL-A1 IDs should be added to this equivalence table. Function `GetPatchEquivalentId()` in `src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c` goes through the equivalence table like below. for (i = 0; i < (EquivalencyEntries * 2); i += 2) { // check for equivalence if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) { *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1]; return (TRUE); } } Change-Id: I7a68f2fef74fb4c578c47645f727a9ed45526f69 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/28204 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: <awokd@danwin1210.me> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20eve: Add PL1 override to 7WLucas Chen
Change PL1 from 4.5W to 7W, based on thermal test results. BRANCH=eve BUG=b:73133864 TEST=Verify the MSR PL1 limitation is set to 7W. Change-Id: Ic3629f9c3b7eb6eef1a1b5a3051c9a11448bc9ad Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28078 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20soc/intel/skylake: Support PL1 override optionWei Shun Chang
In legacy mode, DPTF on some systems may rely on MMIO to control PL1 settings. However, MSR PL1 also contributes to the decision of max PL1 power; and in the current design, the lower value takes effect. In order to align MMIO and MSR settings, a tdp_pl1_override option is added to override the MSR PL1 limitation. BRANCH=eve BUG=b:73133864 TEST=1. Write PL1 override setting in devicetree.cb 2. Verify the MSR PL1 limitation is set correctly. Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20atlas: enable keyboard backlight supportCaveh Jalali
This adds support for controlling the keyboard backlight over ACPI. BUG=b:112619894 BRANCH=none TEST=verified keyboard backlight can be adjusted using keyboard shortcuts Change-Id: I25713f341e8b5a4e50903ac109bfa717f20969d8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28205 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20mb/google/poppy/variants/nocturne: enable eistMatt Delco
Enable Enhanced Intel SpeedStep (EIST) on nocturne. Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20mb/google/eve: enable eistMatt Delco
Enable Enhanced Intel SpeedStep (EIST) on eve. Change-Id: I49b18b817cda570f5c3c4d048c4e03329ac10b87 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/skylake: add CPPC supportMatt Delco
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC). Linux has a driver that enables features like speed shift without consulting ACPI. Other OSes instead rely on this information and need a _CPC present. Prior to this change performance in Win10 never exceeds 80% and MSR 0x770 is 0, while with this change (and enabling eist) higher speeds can be achieved and the MSR value is now 1. Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20cpu/intel/common: add function to init cppc_configMatt Delco
This change adds a method to init a cppc_config structure in a way that should ideally work across Intel processors that support EIST. Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20soc/intel/common/block: Move common uart function to block/uartSubrata Banik
This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20nocturne: Enable debouncing of SX9310 CLOSE / FAR IRQsEnrico Granata
This is meant to solve an issue where the proximity sensor may fluctuate between CLOSE / FAR in rapid succession upon the user removing their hand from the unit, before settling on the correct output. Using the hardware debouncing filter solves this issue and removes the spurious fluctuations. BRANCH=None BUG=None TEST=manual on Nocturne, observing events come in Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/28112 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20soc/intel/common/block: Add WHL 2-core SKUKrzysztof Sywula
There are two SKUs of Whiskey Lake W0, 2-core and 4-core. Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/28111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/apollolake: Force USB-C into host modeJohn Zhao
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures USB-C as device mode. Force USB-C into host mode. BUG=b:111623911 TEST=Verified that USB-C being host mode once USB OTG is set. Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20mb/google/octopus/variants/fleex: Increase weida touchscreen reset delayCrystal Lin
Weida touchscreen controller needs 130 ms delay after reset BUG=b:111102092 BRANCH=master TEST=Verify touchscreen on fleex works with this change Change-Id: Ia86c3acf3c0e09ca05cc1681113672b546f830a0 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-20drivers/pc80/rtc: do not warn if CMOS options are unavailableStefan Tauner
Callers should have a default ready and get noticed by the return value of get_option(). No need to scare log readers at this location. Change-Id: Ied373d8a02afdc8d1017c9f41d9004e3797dfbb3 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28215 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20nb/intel/raminit: Remove unused headersPatrick Rudolph
Change-Id: Ic6e7341b53bcabc415089ccfab121d3694ccb071 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-20nb/intel/sandybridge/raminit: Fix DIMM type mappingPatrick Rudolph
The DIMM type read from SPD needs to be converted to make sure SMBIOS fills in the correct formfactor. Tested on Lenovo T430: The Form Factor no longer reads as unknown. Change-Id: Ia0211fa133f4ba9d60dfbd5f0dd45a43df68c030 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20nb/intel/sandybridge: Fill in DIMM serial numberPatrick Rudolph
Fill in SMBIOS type 17 DIMM serial number, read from SPD. Fixes FWTS SMBIOS type 17 test. Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20intel/common/block: Fix issues found by klockworkJohn Zhao
src/soc/intel/common/block/cpu/mp_init.c Function init_cpus: Pointer dev checked for NULL may be dereferenced. src/soc/intel/common/block/graphics/graphics.c Function graphics_get_bar: Pointer dev returned from call may be NULL and will be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20mb/kontron/ktqm77: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: Ib5799cceacefa89385a7615ef1c4b4d06157044f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20ec/lenovo/pmh7: use read/write function in clear_bit/set_bitAlexander Couzens
Make the code simpler and improve readability. Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20src/drivers/usb/Kconfig: increase warning signs for BBB ownersStefan Tauner
The help text is already very clear but some users (first and foremost the author of this patch ;) are still selecting USBDEBUG_DONGLE_BEAGLEBONE when using a BeagleBone Black and waste hours on analyzing the debug output of EHCI debug driver. Change-Id: Ibf002db7d81ed44878f3ce0324170e4b99e780a5 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-19google/cyan: Fix ACPI resource scope for Melfas touchscreenMatt DeVillier
Fix scope of ResourceSource, which should match the scope of the device itself. Change-Id: I9d0ff0ecc2721ec55b1ed12dddb495cd55966daf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-19mb/lenovo/x1_carbon_gen1: add support for hynix memoryAlexander Couzens
All different memory configuration should be supported by now. Thanks to Igor Lee. Change-Id: Ib93c0e3cbdc29cbf6cff26292df4fbbb8208082f Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: Igor Lee <getrun@gmail.com> Reviewed-on: https://review.coreboot.org/27781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17arm64: Factor out common parts of romstage execution flowJulius Werner
The romstage main() entry point on arm64 boards is usually in mainboard code, but there are a handful of lines that are always needed in there and not really mainboard specific (or chipset specific). We keep arguing every once in a while that this isn't ideal, so rather than arguing any longer let's just fix it. This patch moves the main() function into arch code with callbacks that the platform can hook into. (This approach can probably be expanded onto other architectures, so when that happens this file should move into src/lib.) Tested on Cheza and Kevin. I think the approach is straight-forward enough that we can take this without testing every board. (Note that in a few cases, this delays some platform-specific calls until after console_init() and exception_init()... since these functions don't really take that long, especially if there is no serial console configured, I don't expect this to cause any issues.) Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17sandybridge/raminit_common.c: fix printram statementIru Cai
Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/28117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17soc/amd/common/block/pi/agesawarapper.c: Use find_image()Richard Spiegel
In preparation to removing AmdLib, replace function LibAmdLocateImage() with its ported version find_image(). BUG=b:112625809 TEST=Build and boot grunt. Change-Id: I75ddd55f7e3e7f2cd7914f97c99b62690ae70660 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28164 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17soc/amd/common/block: Port vendorcode's LibAmdLocateImageRichard Spiegel
In preparation to removing AmdLib, function LibAmdLocateImage() has to be ported to be used by agesawrapper. The most important aspect of this porting is that it has to obey coreboot format, specifically 8 character tab and 80 characters max. This required breaking the function in 2 (to solve indentation) and rename some variables to shorter names. One important aspect was breaking (AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset) into: image_ptr = (AMD_IMAGE_HEADER *) current_ptr; if (validate_image((void *)image_ptr->ModuleInfoOffset, and, within validate_image completed by: AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain; BUG=b:112625809 TEST=Build grunt, functionality tested in next commit. Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17google/grunt: Update TP/TS/H1 i2c timingsKevin Chiu
After adjustment on Careena EVT TP: 400.0 KHz TS: 396.8 KHz H1: 396.8 KHz BUG=b:112663934,b:112664258 BRANCH=master TEST=emerge-grunt coreboot measure by scope Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28119 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>