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2021-08-28mb/google/dedede/var/boten: Generate SPD ID for supported partstanley.wu
Add supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. The memory part being added is: MT53E512M32D1NP-046 WT:B BUG=b:194223174 BRANCH=dedede TEST=Build the boten board. Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya/var/anahera: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:197850509 TEST=build pass Change-Id: Ib7bdab1396138d728ae053c30656a9c80dddaff8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/dedede/var/driblee: Configure I2C ports and touchpadFrank Wu
Update the I2C ports and touchpad based on the schematic. BUG=b:195622489, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8778ad6564e526e029c46c36c78e38f764e3c6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56998 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/driblee: Configure USB port settingsFrank Wu
Update the USB port configuration based on driblee schematic. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 1 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: None USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:195622487, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Add two sensors for DPTF functionalitySumeet Pawnikar
Add two thermal sensors for fan and wwan for DPTF based thermal control. BRANCH=None BUG=b:181271666 TEST=None Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
2021-08-28mb/intel/adlrvp_m: Enable touchscreenBernardo Perez Priego
This will add ACPI information to enable WACOM touchscreen. TEST=Boot DUT and issue command: $ ls -al /sys/bus/i2c/devices WACOM PWB-D893 device should be listed and touchscreen should be functional. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-28mb/google/dedede/var/corori: Generate RAM ID and SPD fileIan Feng
Add the support RAM parts for Corori. Here is the ram part number list: DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR BUG=b:196744958 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure thermal sensor settingIan Feng
According to schematics, TSR2 thermal sensor is not present in corori. BUG=b:197281317 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Id69f9d6ace738ef1e792addd782d05c2d03d2b3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57110 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure I2C ports and touchpadIan Feng
1. Support Elan touchpad. 2. Follow schematic to disable I2C1, I2C2 and I2C3. BUG=b:197052531 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ideef57c275432e21f8580d4c5c937909b168d91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57031 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure audio settingIan Feng
Select the drivers for ALC5682 codec and MAX98360A spk amp BUG=b:197037090 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0659a05fbcc28702d922a23d74885ba65a4254f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57015 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure USB port settingsIan Feng
Follow schematic to modify USB port settings. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 0 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: Integrated Bluetooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:196998272 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure GPIO settingsIan Feng
Updated the GPIO pins based on the latest schematic. BUG=b:196867404 BRANCH=keeby TEST=FW_NAME=corori emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I683a7da4fcb2e4e0efdb3547b1de15796c6b55e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Create anahera variantWisley Chen
Create the anahera variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:197850509 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ANAHERA Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27mb/google/butterfly: Put braces around `else` branchAngel Pons
Ensure braces are consistent on all branches of a conditional statement, as per the coding style. Tested with BUILD_TIMELESS=1, Google Butterfly remains identical. Change-Id: I34f3b22486e0f0712bc248477acb43012b21c5ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-27mb/amd/majolica/Kconfig: add EFS SPI settingsFelix Held
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100 case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config for the EM100 emulator case that has limited SPI frequency support. Tested on Majolica by Martin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27broadwell: Drop weak `mainboard_fill_spd_data` definitionAngel Pons
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define this function accordingly. Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/broadwell: Move `mainboard_fill_spd_data`Angel Pons
Move the `mainboard_fill_spd_data` function out of romstage, in preparation to confine `pei_data` usage to as few files as possible. Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27Broadwell boards: Do not assign unused SPD addressesAngel Pons
The `pei_data` struct is already zero-initialised. Change-Id: If539cddc007f32a04389bc3b3b06c43cb5c86e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55804 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/auron: Refactor memory-down SPD handlingAngel Pons
Variants only need to provide the SPD index and whether said index corresponds to a dual-channel configuration, which can be achieved without using `pei_data`. Add two functions that return the values and use them in `spd.c` at mainboard level. Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-27mb/google/brya/variants/primus: Enable SaGv supportAriel Fang
This patch enables SaGv support for primus. BUG=b:196286180 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I00074e348dd6347602c18dcfd231a890153b4685 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27soc/intel/denverton_ns: Ensure CPU device has a valid linkFurquan Shaikh
This change calls `add_more_links()` in `denverton_init_cpus()` if `dev->link_list` is NULL. This condition can occur if mainboard does not add any APIC device in the device tree. Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/intel/adlrvp: Enable SaGv supportV Sowmya
BUG=b:187446498 TEST=Boot and verify memory trains at all the SaGv points through FSP debug logs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-27mb/google/cherry: Support audio codec RT1011Trevor Wu
Add GPIO "rt1011 reset" and i2c2 initialization for RT1011. Add CHERRY_USE_RT1011 and CHERRY_USE_RT1019 to Kconfig, so we can spearate code for the specific codec by config. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I18939a2a2caae0444ce17f4712764647975121ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/57157 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/var/driblee: Configure GPIO settingsFrank Wu
Updated the GPIO pins based on the latest schematic. BUG=b:191732473, b:195619827 BRANCH=keeby TEST=FW_NAME=driblee emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I20baeb6b13c8c0a70c7555aa8f7f5557768c0083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56996 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/amd/common/block/spi: Add SPI config to KconfigMartin Roth
Currently, The SPI speed/mode configuration is split between Kconfig and devicetree. We'd like to have everything in one place. Since we need the fast-read speed and the mode available in the Makefile to build the AMD EFS table, we currently need it in Kconfig. Move all of the settings to Kconfig and remove them from Devicetree in a later commit. BUG=b:195943311 TEST=boot majolica & guybrush, verify spi settings Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/variant/drawcia: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to drawcia for MT53E512M32D1NP-046 WT:B. This part is already in global_lp4x_mem_parts.json.txt, and use /util/spd_tool/lp4x/gen_part_id to assigns DRAM IDs. BUG=b:196951879 BRANCH=firmware-dedede-13606.B TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: Ic42e6357943ba651ffd92fb2974e9ea52fa19020 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56905 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/var/sasukette: Add FW_CONFIG probe for EXT_VRZhi Li
commit df520855 (soc/intel/jsl: Add disable_external_bypass_vr config) Add FW_CONFIG probe for don't stuffing ANPEC APW8738BQBI IC. BUG=b:190727416 BRANCH=dedede TEST=test for enter S0ix and resume normally by powerd_dbus_suspend Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I15ab30f14df9dc02157009091aa8398e2fa75188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56804 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/amd/common/fsp/fsp_validate: add runtime check for FSP-M binary sizeFelix Held
When modules are added to the FSP and they won't fit into the FSP binary any more, the size can be increased in the FSP build. Especially in the case of debug builds the increased size might not fit into the memory region it gets decompressed into which starts at FSP_M_ADDR and has a size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header function that ends up being called by the FSP driver in romstage to do some additional checks on the FSP binary's header that includes the version number and the image size. We can use the image size field to check if it fits into the reserved region. Since the FSP-M memory region is located after romstage loading it won't clobber the romstage code where we do the check. This runtime check is added in addition to the build-time check to also cover the case when the FSP binaries in CBFS get replaced with ones that don't fit into the reserved memory region after the coreboot build. BUG=b:186149011 TEST=Mandolin still boots fine with the patch applied. When as a test the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000 which is by far not enough for the decompressed FSP-M binary to fit into it prints the newly added error message on the console and then stops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26elog: Define constant for RW region nameRicardo Quesada
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the hardcoded "RW_ELOG" value. This constant will be used also by elogtool (see CL in the commit chain). BUG=b:172210863 Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56986 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26elog: move functionality to commonlib/bsdRicardo Quesada
This commit moves some drivers/elog/ functionality to commonlib/bsd since they will be called from util/cbfstool/. In particular: * elog_fill_timestamp(), elog_update_checksum(), elog_checksum_event() were moved to commonlib/bsd/elog * elog_fill_timestamp() receives the time parameters and updates the event based on the "time" arguments. The original elog_*() functions were written by Duncan Laurie (see CB:1311) and he gave permission to re-license the code to BSD. BUG=b:172210863 Change-Id: I67d5ad6e7c4d486b3d4ebb25be77998173cee5a9 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26mb/google/octopus: add CBI SKU RAM ID 5Sheng-Liang Pan
add CBI sku RAM ID 5 for 4GiB Capacity with dual channel and dual rank with 4gb dram density. BUG=b:178665760 BRANCH=Octopus TEST=build fw and flash to the dut with RAMID 5, dut can boot up successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I922a518cffc4dac71caec68e6f7a55c6c5717438 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56982 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26mb/google/dedede/var/bugzzy: Configure USB portsSeunghwan Kim
Override USB port configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image Change-Id: I4368946f4175f4f065a3483dc7ca6068c6de3123 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-26soc/intel/tigerlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ice4c727f2b75893cd012345a556fd21d9807dfaa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/intel/alderlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/intel/common/block: Add PAM locking functionTim Wawrzynczak
Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit instead of the FSP, therefore add a function in the common code to do this. Source: ADL & TGL FSP integration guides Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26mb/google/var/redrix: Correct the WWAN_PERST_L settingWisley Chen
WWAN_PERST_L (GPP_E0) is wrongly configured to NC in ramstage. So, remove it. BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: If8e96045a0d78a942f77d8d8e371ab75dff0c202 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-26mb/google/brya/variant/redrix: Correct MAX98390 AMP settingWisley Chen
4 MAX98390 Speaker Amps are connected to i2c0 and device addresses are 0x38/0x39/0x3a/0x3b BUG=b:191931762 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ie8f01e6a7e09e18f6d34f3ceb1db8e2e238197bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57114 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26drivers/intel/fsp2_0: rename soc_validate_fsp_versionFelix Held
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it can not only be used to check the version info in the FSP-M binary's header, but also to check every other field in the binary's header. This is a preparation for a follow-up patch that implements this function to check the FSP-M binary's size. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26soc/amd/common/fsp/Makefile: check if FSP-M is larger than FSP_M_SIZEFelix Held
The FSP-M binary needs to fit into the memory region that starts at FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time if the uncompressed FSP-M file is larger than the size of the region it will be copied into. BUG=b:186149011 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26device/mipi: Move to drivers/mipiJulius Werner
Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-26mb/google/guybrush: Create dewatt variantBhanu Prakash Maiya
Create the dewatt variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:196460993 BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_DEWATT Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I57860a7cad1bf202bd3ef3eed5f498fbf1d29af8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57108 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/roda/rv11/acpi: Use lower case format for hex valuesFelix Singer
Change-Id: I3bea9e1f9cc25a4476ddbaa8bd8e434609eb28f7 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25mb/roda/rv11/acpi: Use Printf ()Felix Singer
Change-Id: Iec6ec8bbf3cc5c9230ba6bcb0126ff6085f26464 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25soc/intel/cannonlake: Fix PCH-H IRQ constraintsAngel Pons
Cannon Point PCH-H does not implement the eMMC, I2C4 and I2C5 devices. Guard the IRQ constraints for these devices to prevent FSP assertions. Tested on Prodrive Hermes, debug FSP builds no longer fail to boot. Change-Id: I58674d1c3c5fe4535c022020674d48d6a5315bf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25mb/google/brya/variants/gimble: Correct I2C slave address and update gpio.cMark Hsieh
1. According to the Maxim's comment and schematic diagram of proto, Modify I2C slave address to 0x38, 0x3c. 2. According to the schematic diagram of proto, Change GPD11 to NC. BUG=b:191811888, b:1191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibf8adf2ed8dda9ae6da06e7e995bef9395cdee35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57059 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/google/dedede/var/galtic: modify touchscreen to native I2C protocolFrankChu
Touchscreen will be no function with R93-14092.19.0 image or be later. It just happened to work because elants_i2c driver would bind to the device first based on "ELAN0001" HID ID BUG=b:195994810 TEST= verify only update RW FW can fix touchscreen no function issue 1.Build test firmware 2.prepare DUT enviroment (R93 image + update RW to test firmware) 3.verify touchscreen function normally Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie9e0fe726854d0128ad1bb430544640dc8f034ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/57011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2021-08-25mb/google/dedede/var/sasukette: Update DPTF parametersZanxi Chen
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I06d8a543dbd77137cb97c4ea695a1f2b9f8ee76c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57116 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/goog/bry/var/redrix: Enable Genesys GL9755 settingWisley Chen
BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I45ecab8c036a7e75cc0c564867119c027175ed06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25soc/intel/tigerlake: Hook up ucode for TGL-HTim Crawford
Hook up microcode from 3rdparty repo for: - 06-8d-01 (CPUID signature: 0x806d1) Verified microcode blob was found in CBFS on system76/gaze16 (TGL-H). CBFS: Found 'cpu_microcode_blob.bin' @0x11700 size 0x18400 in mcache @0x76c2d0ac microcode: sig=0x806d1 pf=0x2 revision=0x2c Change-Id: Icf0d8bc700a73697f06503e9d1bb40ce26741cdf Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57067 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/google/brya/primus: modify HID to MX98357A to enable audio functionCasper Chang
Primus has MX98360A, which Linux kernel 5.10 currently does not support and, therefore, audio does not work. As the device is compatible with the MX98357A, use that until Linux’ SoF driver supports the new version (https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268). BUG=b:194749863 BRANCH=none TEST=build coreboot and audio function works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25mb/google/brya: Fix PL4 limitsTim Wawrzynczak
Commit e7f3e6a0558 added PL4 limits for brya0, but the units were mW, whereas the `tdp_pl4` field is expected to be in whole Watts, therefore divide all of the settings by 1000. BUG=b:197468828 TEST=boot brya0 to OS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6da6bae4eb8c83188d813828cdc4f7c1e20f1b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-24mb/google/brya/variants/kano: Init devicetree for kanoDavid Wu
Init basic override devicetree based on schematics BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I283517427612e24eabe2ce736d677253065c7859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya: Enable SaGv supportV Sowmya
This patch enabled the SaGv support for brya0 baseboard. BUG=b:187446498 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I2a71e159fa49f677660af8279f2b582a3916eee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for primusMalik_Hsu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for primus. BUG=b:195611000 BRANCH=None TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c60979a2d42f836e0f0261c42fcfc36c41e113a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/dedede/var/cret: Add new G2Touch touchscreenDtrain Hsu
Add G2Touch G7500 touchscreen into devicetree for cret. BUG=b:180547621 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I57638bf8a3eb4efcd819f5433fa54c22b7af3054 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-24mb/google/brya/var/felwinter: Generate RAM ID and SPD fileEric Lai
Add the support RAM parts for felwinter. Here is the ram part number list: DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) BUG=b:197308861 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I76febefc251b02a047819242e23c02dc50891c2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/broadwell: Move `pei_data` out of romstage.cAngel Pons
Prepare to confine all `pei_data` references in raminit.c and refcode.c so that mainboards don't need to know about its existence. Change-Id: I55793fa274f8100643855466b6cca486896fb2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/broadwell: Do early ME init a bit earlierAngel Pons
Do early ME init before adding the "start of raminit" timestamp. Change-Id: If8b27a9d4eb3b801e3e05dc2f2b95bf748985707 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55800 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/tigerlake: Add USB ACPI devices for PCH-HJeremy Soller
Change-Id: Ia1c1c3d172366ddcc8c194cb2e0b0c2fb2acf678 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add SPI_DMI_DESTINATION_ID for PCH-HJeremy Soller
Change-Id: I9a316b91b31166831f23eaf9e271a7d67ac4ccff Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Set UserBd to recommended default for PCH-HJeremy Soller
Change-Id: Ie8a28d8e03d7176df5409e6cb507a0a802ff026f Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56951 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-HJeremy Soller
Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add TGL-H PEG portsJeremy Soller
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCIe root ports for PCH-HJeremy Soller
Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H GPIO definitionsJeremy Soller
Add TGL-H GPIO definitions, based on existing TGL definitions and how CNP/CNP-H handles the split. Reference: - Intel doc 619207 - TigerLake FSP - linux/drivers/pinctrl/intel/pinctrl-tigerlake.c Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H PMC GPE group definitionsJeremy Soller
Reference: - TigerLake FSP Change-Id: I666eb710762f6b00d173ee1a473f1f5a612953a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add PCH-H chipset devicetreeJeremy Soller
Based on the base TGL devicetree, add one specific to TGL-H that adds the additional supported devices. Introduces a new Kconfig for selecting the PCH support. Reference: - Intel doc 615985 Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller
Convert the power limit defines to an enum and add TGL-H entries. Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel: Add TGL-H CPUIDJeremy Soller
Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56942 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"Furquan Shaikh
This reverts commit 68d8357dab55660058ad1ab8dca34fd03e0adbb5. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-24Revert "soc/intel/broadwell/pch: Drop device NVS remainders"Furquan Shaikh
This reverts commit 34bd6ba97917b0bc54bb1f1e106a56b5c03e19ac. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Not reverted: * ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's selection in broadwell is not required. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-23mb/google/hatch: Create moonbuggy variantRehan Ghori
Create the moonbuggy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=191356135 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_MOONBUGGY Signed-off-by: Rehan Ghori <rehang@google.com> Change-Id: Iaf545dcd5ff537afdf029f510553d16a1239763e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-23mb/google/dedede: add gooey variantstanley.wu
gooey is the same design as boten, and differs only in replacing Cr50 with discrete TPM. BUG=b:193366710, 197247706 TEST=FW_NAME=gooey emerge-keeby coreboot Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I2a54f872a7d5c0bee76a9e6e309613d9357b380b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-23include/bcd: move bcd code to commonlib/bsd/includeRicardo Quesada
Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/ Also, the license is changed from GPL to BSD. This is because it is needed from "utils" (see CL in the chain). For reference bin2bcd() & bcd2bin() are very simple functions. There are already BSD implementations, like these ones (just to name a few): https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67 http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c BUG=b:172210863 TEST=make (everything compiled Ok). Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-23mb/google/guybrush: Enable PCIe L1 SubstatesMatt Papageorge
This change enables L1.1 and L1.2 on all real Guybrush PCIe devices. BUG=b:188123142 TEST=Boot to ChromeOS and verify L1SS are functional by dumping the settings with "lspci -vv". Leave system on for 20 minutes and no hang. Also perform 20 reboots and suspend operations Cq-Depend: chrome-internal:4012927 Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-23mb/google/dedede/var/bugzzy: Configure GPIO settingsSeunghwan Kim
Override GPIO pad configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image and boot on bugzzy board Change-Id: I7c3580e7eb34efed0441ead243343d2d7875d50f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-23soc/mediatek/mt8195: Update clock square settingChun-Jie Chen
To reduce suspend power consumption, 1. Disable unused CLKSQ2. 2. Set CLKSQ_EN to sleep control for SPM 26M sleep control. No bus clock when enter 26m sleep control, and only control clock square by side band. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Ia9a1735d6f508ce35b9af2d67831a3474255198b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57043 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-23soc/mediatek/mt8195: add HDMI low power settingRex-BC Chen
Add HDMI low power setting to reduce power consumption. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ica91645789e5de3401131e7050d2b1ee06c535dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57042 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-22mb/google/brya/var/brya0: Align comments in overridetreePaul Menzel
Change-Id: Id3eb18cae2dd9a7b148bc9f3dcaf387f35dbd2fb Fixes: 312fb716 ("mb/google/brya: Add ALC1019_NAU88L25B support") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-22AGESA f15tn: Fix building IDS tracing supportAngel Pons
Also add a config file to ensure the code gets build-tested. Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-22AGESA f15tn: Hook up IDS options to KconfigAngel Pons
IDS (Integrated Debug Services) options are meant to be enabled when one wants to debug AGESA. Since they are compile-time options, using Kconfig is the logical choice. Currently, none of the options builds. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and Asus A88XM-E does not change. Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-08-22AGESA f15tn: Factor out common OptionsIds.hAngel Pons
Subsequent commits will add Kconfig options to configure IDS. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: I861762280b274566ce14969a30e2e0c98e120a69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`Angel Pons
The `ASSERT` macro is already defined in `src/include/assert.h`, and AGESA's definition is never used. On Asus A88XM-E, toggling the value of the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary when using reproducible builds. Attempting to use AGESA's definition of the `ASSERT` macro results in build errors: In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info': src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value] #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); Given that coreboot's definition of `ASSERT` is more useful, drop AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro. Also remove the `IdsAssert` function, as it is no longer used anywhere. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn boards: Sync IDS option valuesAngel Pons
In preparation to replace OptionsIds.h with Kconfig options, use the same settings on all AGESA f15tn boards. The only difference this makes is that the `IDS_LATE_RUN_AP_TASK` macro no longer expands to nothing. It is expected that the impact this difference makes is minimal. Note that the `IDSOPT_TRACING_ENABLED` option currently fails to build. Tested on asus/f2a85-m, still boots. Change-Id: Iedd4d1f255650012f3efd9a27718e18c1c904dc1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53982 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20qualcomm/sc7180: Switch to common MIPI panel libraryJulius Werner
This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20mb/google/brya: Add ALC1019_NAU88L25B supportEric Lai
Add ALC1019_NAU88L25B DB support. BUG=b:195891240 TEST=audio is functional when playing youtube. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9209c4cab00fc03b2a6107b5c32804786cd2e242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20soc/intel/adl: Update power limits for ADL-M SKUSumeet Pawnikar
Update SKU specific power limits for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: I40b9b3a508c549d940e1c2c9e8b4079695b694e6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20soc/intel/adl: Update PCI ID for ADL-M SKUSumeet Pawnikar
Update PCI ID for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: Ia2c5ce270bc421d8a41cc4bc6ce0b51987d2aaec Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20mb/google/zork: only enable RTD2141 when presentPeter Marheine
An MST hub is only present on some devices that are configured with a particular daughterboard indicated by EC fw_config, so add a fw_config probe that matches the USB daughterboard ID from CBI to only enable it on devices where present, using variant-specific daughterboard IDs. BUG=b:185862297 TEST=RTD2141 remains in ACPI tables on a berknip with Dali DB, and is not present on the same system if probe is changed to enable it for picasso DB. BRANCH=zork Change-Id: I4ada9b492ab221fa98350bf2faf27a23342f3a55 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-08-20soc/amd/common: Skip psp_verstage on S0i3 resumeMartin Roth
PSP_Verstage will take almost the entire time to run that is allotted to S0i3 resume. Since coreboot isn't running, the PSP needs to handle any security requirements. The long- term plan is that the PSP won't even load psp_verstage on S0i3 resume, but when it is loaded, this makes sure we exit immediately BUG=b:177064859 TEST=Verify that PSP_verstage doesn't run on S0i3 resume Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-08-20soc/intel/cannonlake: Unbreak some short linesNico Huber
Change-Id: I8c8b49d519b7c6a3d1e4946818b2fc5a1dd1d3e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56663 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19Revert "src/soc/intel/cannonlake: Update C-state latency control limits"Nico Huber
This reverts commit 66dbb0c5d67279722fcbcb547d9c6b61e606d50e. The numbers were meant for Cannon Lake, but the code was also meant to be used for all other platforms using the Cannon Point PCH. Now Cannon Lake support is even dropped, so we can cleanly revert to the recommended values for the other platforms. Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56662 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-19soc/intel/denverton_ns: Sanity check MMCONF_BASE_ADDRESSKyösti Mälkki
According to received feedback, FSP-T enables MMCONF at address 0xe0000000 with 256 busses. Sanity-check that Kconfig matches that. Add MMCONF_BUS_NUMBER such that MCFG in ACPI will be correct. Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-19mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-P RVPSubrata Banik
This patch enables eNEM flow for Alder Lake SoC hence drop INTEL_CAR_NEM Kconfig from ADL-P RVP. ALDERLAKE_CAR_ENHANCED_NEM Kconfig will select all relevant Kconfig required to enable eNEM for Alder Lake. Additionally, select INTEL_CAR_NEM Kconfig for ADL-M RVPs from Kconfig.name. BUG=b:168820083 TEST=Able to build and boot ADL-P RVP using eNEM mode. Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48345 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik
This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19mb/google/dedede/var/driblee: Generate RAM ID and SPD fileFrank Wu
Add the support RAM parts for Driblee. Here is the ram part number list: 1. Hynix H9HCNNNBKMMLXR-NEE 2. Micron MT53E512M32D2NP-046 WT:F 3. Samsung K4U6E3S4AA-MGCR 4. Micron MT53E512M32D1NP-046 WT:B BUG=b:195619346 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56924 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19mb/google/brya: set tcc_offset value to 10Sumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUGb=b:195706434 BRANCH=None TEST=Built for brya platform and verified the MSR value Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/alderlake: set default PL4 values for different SKUsSumeet Pawnikar
Set default PL4 values for various Alder Lake CPU SKUs as per bug#191906315 comment#10. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board. Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 16:03:55 +0000