summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2023-04-21drivers/ipmi: Replace <build.h> with <version.h>Kyösti Mälkki
To use generated build.h one should have had a pre-requisite in the Makefile. Reference coreboot_version from lib/version.c instead. Change-Id: I7f10acabf1838deb90fde8215a32718028096852 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21nb/amd/pi/00730F01/northbridge: use get_top_of_mem_[below,above]_4gbFelix Held
Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6332b051acf8d00ba6528360b18ea0d3c4dc30fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gbFelix Held
The top of memory below 4GB will always fit into 32 bits, so change the return type accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b463a17f2db3b7a99ff3572f318c9c22aac7431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21include/cpu/amd/mtrr: rename functions to get top of memory regionsFelix Held
Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and get_top_of_mem_above_4g to make it clearer what those functions return. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21soc/amd/phoenix: Update XHCI eventsJon Murphy
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI to allow for XHCI events to be logged. BUG=b:277273428 TEST=builds Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74280 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/myst: Enable AP <-> GSC communicationJon Murphy
Configure GSC I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for GSC device and enable the required config items. BUG=b:275959717 TEST=builds Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74111 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21aopen/dxplplusu: Drop ACPI C-states supportKyösti Mälkki
C0 clock throttling was disabled, no need to add _PTC. C2/C3 latency values were copy-paste from different CPUs. TBD: Check IO-trap Change-Id: Ia0e35e28f0df8b0f8fc58f70c7d792487ee4f7f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74439 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-04-21ACPI: Obsolete FADT duty_offset and duty_width fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _PTC package to define P_CNT IO address for clock throttling. The platforms touched here already emit empty _PTC to disable clock throttling. Change-Id: I0e84c8ccd2772c9b3d61f71b74324c8d28f4eefe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74438 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21soc/amd/phoenix/xhci: Correct counting of xhci_sci_sourcesFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iabba97e003d1a5140c98e3fc5a3496f66f8795c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-21mb/google/brya/var/marasov: Add _DSD object for wifiFrank Chu
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:278310435 BRANCH=firmware-brya-14505.B TEST=Verified that the _DSD object is still present in the SSDT. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5a69a47e67f6acaad5a5d1b67e437c5a41bebf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74499 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/dedede: Create boxy variantkevin3.yang
Create the boxy variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277529068 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BOXY Change-ID: Ief22eb000421c23abf6de3f99eb860bdae1e7919 Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-20soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM methodCliff Huang
srcclk_pin is 0-based and '0' is a valid clock source number. If srcclk_pin is set to -1, then the clock will not be disabled in D3. Therefore, clock source gating method should not be generated. BUG=b:271003060 BRANCH=firmware-brya-14505.B TEST=Boot to OS and check that rtd3 ACPI entries are generated as expected. For those PCI devices with RTD3 driver whose srcclk_pin to 0, the RTD3 entries should not be missing due to check error. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73889 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-20soc/intel/meteorlake: Send CSE EOP Async CMD earlySubrata Banik
This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample which causes idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/rex sku to ChromeOS and observed ~100ms of boot time savings (across warm and cold reset scenarios) Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-20mb/google/myst: Add eSPI configurationJon Murphy
Add eSPI configuration for myst. Ensure the additional windows are used and remove unnecessary addresses from the range used on skyrim. BUG=b:275953893 TEST=builds Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPRFelix Held
Parts of this file were still a copy of the file from the Mendocino SoC, so update the file to match the PPR #57019 Rev 3.03 and the chipset devicetree of the Phoenix SoC. Phoenix has 4 GFX/GPP PCIe bridges/ports, the numbering scheme of the GPP PCIe bridges/ports was changed so that the numbers match the device and function numbers, and there are new device functions for the IPU and the USB4 controller and router devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74565 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/amd/phoenix/devicetree: drop i2s_ac97 deviceFelix Held
In both PPR #57019 Rev 3.03 and PPR #57396 Rev 3.04, the i2s_ac97 function on bus C isn't mentioned any more and the microarchitecture specification document for this SoC also doesn't mention it, so remove it from the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibd115953bdd60e1dfcc79797b0c2158e5d861636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74564 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_regFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e067f6fb2bab66d9b2f6965636845dfd8b7cacd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-20soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is currently unused. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I08930ef84438140a13df74900570b126088bd1cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74478 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/alderlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is currently unused. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2590e8dec0a308e0dc3d467cb3dd2bb97e877492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74477 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep stateSean Rhodes
Use D3COLD_SUPPORT Kconfig option to set the maximum support sleep state. Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it is not, it will break S3 exit. When D3COLD_SUPPORT is not enabled, return `3` (D3Hot). This fixed S3 exit on both TGL and ADL. Tested on StarBook Mk V and Mk VI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I578d4933b6144aec79fe0b2eb168338ef82c0b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74406 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-20soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20device: Move D3COLD_SUPPORT symbolSean Rhodes
Move D3COLD_SUPPORT to device, so it can be used by multiple SOCs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie92736458ab95374c51346107665dc0fd1e653a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74404 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20mb/amd/birman: Enable PCIe RTD3 supportFred Reitberger
Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-20mb/amd/birman: Update DXIO descriptors per schematicFred Reitberger
Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B v0.7 Update devicetree to reference the updated DXIO descriptors. TEST=boot birman and note the devices show up in the logs correctly Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/69705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-20soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOSSubrata Banik
The Intel FSP used on ChromeOS platform has dropped the `CpuFeaturesPei.ffs` module to opt for coreboot running this additional feature programming on BSP and APs. TEST=Able to build and boot google/rex without any boot regression. Please refer to the boot time and SPI flash savings after dropping the FSP feature programming: Boot time savings=10ms SPI Flash size savings=34KB Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Reviewed-on: https://review.coreboot.org/c/coreboot/+/74168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-19mb/amd/birman/ec.c: Update EC configurationFred Reitberger
Update the EC GPIO values for Birman, per schematic # 105-D67000-00B Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec Reviewed-on: https://review.coreboot.org/c/coreboot/+/73971 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19mb/google/myst: Add initial fch irq routingJon Murphy
Add initial fch irq routing table for Myst. BUG=b:275946702 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMAKarthikeyan Ramasubramanian
CBFS library performs memory mapped access of the files during loading, verification and de-compression. Even with MTRRs configured correctly, first few file access through memory map are taking longer times to load. Update the SPI DMA driver to load the files into CBFS cache, so that they can be verified and de-compressed with less overhead. This saves ~60 ms in boot time. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe ~60 ms improvement with the boot time. Performing additional test to confirm there are no regressions. Before: ======= 970:loading FSP-M 15:starting LZMA decompress (ignore for x86) 760,906 (60,035) 16:finished LZMA decompress (ignore for x86) 798,787 (37,881) 8:starting to load ramstage 17:starting LZ4 decompress (ignore for x86) 1,050,093 (13,790) 18:finished LZ4 decompress (ignore for x86) 1,054,086 (3,993) 971:loading FSP-S 17:starting LZ4 decompress (ignore for x86) 1,067,778 (3,313) 18:finished LZ4 decompress (ignore for x86) 1,068,022 (244) 90:starting to load payload 17:starting LZ4 decompress (ignore for x86) 1,302,155 (11,285) 18:finished LZ4 decompress (ignore for x86) 1,303,938 (1,783) After: ====== 970:loading FSP-M 15:starting LZMA decompress (ignore for x86) 709,542 (12,178) 16:finished LZMA decompress (ignore for x86) 739,379 (29,837) 8:starting to load ramstage 17:starting LZ4 decompress (ignore for x86) 1,001,316 (12,368) 18:finished LZ4 decompress (ignore for x86) 1,001,971 (655) 971:loading FSP-S 17:starting LZ4 decompress (ignore for x86) 1,016,514 (3,031) 18:finished LZ4 decompress (ignore for x86) 1,016,722 (207) 90:starting to load payload 17:starting LZ4 decompress (ignore for x86) 1,244,602 (10,313) 18:finished LZ4 decompress (ignore for x86) 1,244,831 (228) Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-04-19mb/google/skyrim: Fix eMMC reset GPIOJon Murphy
On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6). Update the port_descriptors to link the correct reset GPIO. Data is from the skyrim variant schematics and go/skyrim-gpios. BUG=b:278759559 TEST=reboot: 5 iterations suspend_stress_test: 10 iterations Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74512 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-19mb/google/brya/var/crota: select SOC_INTEL_RAPTORLAKETerry Chen
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as crota is using a converged firmware image. BUG=b:267249674 BRANCH=firmware-brya-14505.B TEST="FW_NAME=crota emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage" Cq-Depend: chromium:4430832 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I448c58f93fddc44904c1f5ef3f8939618eff536f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-19mb/google/kukui: Add sdram configs for RAM code 0x33 and 0x34Sheng-Liang Pan
Add sdram configs: - RAM code 0x33: sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB SPD for K4UBE3D4AB-MGCL 4GB - RAM code 0x34: sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB for H54G68CYRBX248 8GB BUG=b:278644249 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If5b484b5324ba39dbb220f12bdb8344ecb5c4da5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73469 Reviewed-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-19mb/google/brya/var/constitution: Generate SPD ID for supported partsMorris Hsu
Add supported memory part in mem_parts_used.txt, then generate. K4UBE3D4AB-MGCL BUG=b:267539938 TEST=run part_id_gen to generate SPD id Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74497 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-18mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0Anand Vaikar
The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF), hence update the correct bridge number in the device tree. TEST: Builds and boots, the device enumerates. [DEBUG] PCI: 00:02.4 [1022/14ee] enabled [DEBUG] PCI: 01:00.0 [144d/a80a] enabled Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-18src/cpu/power9: move part of scom.h to scom.cSergii Dmytruk
Reset function, constants and include are not used outside of scom.c and not going to be. Change-Id: Iff4e98ae52c7099954f0c20fcb639eb87af15534 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-04-18mb/google/brya/var/omnigul: Adjust I2Cs CLK to be around 400 kHzJamie Chen
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for audio, TPM, touchscreen, and touchpad. Tuning i2c frequency for omnigul I2C0 - Audio CLK : 293.7khz I2C1 - TPM CLK : 388.8khz I2C3 - Touch Screen CLK : 294.8khz I2C5 - Touch Pad CLK : 389.2khz BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, and measure i2c clock. Change-Id: I7c4fdf0e003318a69b870b487a60accefbc0ffed Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-17Makefiles: Drop redundant VARIANT_DIR definitionsKyösti Mälkki
Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-17mb/google/dedede/var/boten: Generate SPD ID for supported memory partkevin3.yang
Add boten supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL BUG=b:278138388 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-17mb/google/rex: Enable all DDI lanesAnil Kumar
This patch enables all DDI ports on Rex board to support display port tunneling and dual display on TBT dock. BUG=b:273901499 TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74413 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-17sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED definesKyösti Mälkki
Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-17cpu,soc/intel: Separate single SSDT CPU entryKyösti Mälkki
Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-17mb/google/brya/variants/hades: Update GPIO configsTarun Tuli
Update GPIO configs based on latest schematics (revision aabe36) Move GPP_D4->GPP_A13 (BT_DISABLE_L) Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD) Move GPP_A13->GPP_A20 (GSC_PCH_INT_ODL) BUG=b:269371363 TEST=builds Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-17mb/google/nissa/var/craask: Add GTCH7503 and split TS by SSFCTyler Wang
Add G2 touchscreen GTCH7503 for craaskino. Use SSFC to separate touchscreen settings. Bit 38-41 for TS_SOURCE: (1) TS_UNPROVISIONED --> 0 (2) TS_GTCH7503 --> 1 BUG=b:277979947 TEST=(1) emerge-nissa coreboot (2) Test on craaskino with G2 touchscreen (3) Test on craaskino with elan touchscreen Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I636f21be39f26a617653e134129a11479e801ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-16mb/google/rex: Create screebo variantSimon Zhou
Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-16soc/intel/jasperlake: Hook up GMA ACPI brightness controlsMatt DeVillier
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on google/magpie. Backlight controls work on Windows 10 and Linux 6.1. Change-Id: Iaa9872cd590c3b1298667cc80354ed3efd91c6c8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-15soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.cSubrata Banik
The patch moves API that gets the CSE FW partition information into CSE Lite specific file aka cse_lite.c because the consumer of this API is the cse_lite specific ChromeOS devices hence, it's meaningful to move the cse lite specific implementation inside cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74382 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/tigerlake: Enable early caching of RAMTOP regionLean Sheng Tan
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/alderlake: Enable early caching of RAMTOP regionLean Sheng Tan
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot Starlab ADL laptop to OS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73736 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-15soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi
This patch adds CPU ID for B0 stepping (aka ES2). DOC=#723567 TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log. Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/baytrail: Make acpi_madt_irq_overrides() staticKyösti Mälkki
Change-Id: Id362e023358054df2c4511fd108c313da868306d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74325 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPICKyösti Mälkki
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. For asus/p2b, this adds MADT LAPIC entries, even though platform has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates the MADT, including an entry for LAPIC address. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-14ec/acpi/ec: replace misleading "recv_ec_data_timeout" console outputFelix Held
In the non-timeout case in recv_ec_data_timeout, a message like this one will get printed at BIOS_SPEW log level: "recv_ec_data_timeout: 0x00". The "timeout" part of the function name corresponds to what the function does, but the message will only be printed when not running into the timeout which is a bit misleading and might suggest a problem when there is none. To avoid this possible confusion, don't use the function name in the printk, but use "Data from EC:" instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I521f67517f64fc64e24853d96730c3f9459f1ccc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74381 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-14cpu,soc/intel: Sync ACPI CPU object implementationsKyösti Mälkki
Take variable names from soc/intel and adjust counter to start from zero. Change-Id: I14e1120e74e1bd92acd782a53104fabfb266c3b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14cpu,soc/intel: Use acpigen_write_processor_device()Elyes Haouas
Use acpigen_write_processor_device() instead of deprecated acpigen_write_processor(). Change-Id: I1448e0a8845b3a1beee0a3ed744358944faf66d8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72488 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_configLean Sheng Tan
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB that was caused by the API change in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. This patch removes the broken API function and also adds package_id log print same as previous commit mentioned above. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74436 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-14vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS caseFelix Held
When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be selected. This causes vc/google/chromeec/acpi/chromeos.asl to be included in the DSDT and chromeos_acpi_gpio_generate to be called when generating the coreboot SSDT. When a mainboard also uses DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0 and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only checked if the GPIO table was non-NULL, which caused the function to exit early and not generate the OIPG package which causes the kernel to complain about referencing the non-existing OIPG package. To avoid this, only exit in the GPIO table pointer being NULL case if the number of GPIOs is non-0. TEST=Error about missing OIPG ACPI object in dmesg disappears on birman. Before: [ 0.241339] chromeos_acpi: registering CHSW 0 [ 0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330) [ 0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531) [ 0.241933] chromeos_acpi: failed to retrieve GPIO (5) [ 0.242011] chromeos_acpi: registering VBNV 0 [ 0.242113] chromeos_acpi: registering VBNV 1 [ 0.242284] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.242462] chromeos_acpi: installed With the patch applied: [ 0.242580] chromeos_acpi: registering CHSW 0 [ 0.242714] chromeos_acpi: registering VBNV 0 [ 0.242817] chromeos_acpi: registering VBNV 1 [ 0.242990] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.243249] chromeos_acpi: installed Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74375 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)Subrata Banik
This patch avoids cannonlake base config to select eNEM for CAR by default. Rather allow other SoC config to choose the applicable CAR mode between eNEM and NEM. CML and WHL select eNEM whereas CFL decided to use NEM for CAR setup. Here is some background about why CFL SoC platform decided to choose NEM over eNEM: It was found that some coffeelake CPUs like Intel i3 9100E fail to enter CAR mode because some MSR used by NEM enhanced are lacking. According to the Intel SDM CPUID.EAX=07h.ECX=0 reg EBX[12 or 15] should indicate the presence of IA32_PAR_ASSOC and CPUID.EAX=10h.ECX[1 or 2] reg ECX[2] should indicate IA32_L3_QOS_CFG and IA32_L2_QOS_CFG respectively but even on a Intel coffeelake CPU that works with the NEM_ENHANCED these CPUID bits are all 0 so there is no way of knowing whether NEM_ENHANCED will work at runtime. Instead just always use regular NEM. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14mb/google/corsola: Add detachable Starmie as variantRuihai Zhou
The 'Starmie' is a mt8186 detachable reference design that will share most of Corsola design. For AP firmware, there will be a few changes, mostly in display (MIPI interface and w/o bridge), so we create it as a variant in Corsola. BUG=b:275470328 BRANCH=corsola TEST=./util/abuild/abuild -t google/corsola -b starmie -a Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14soc/mediatek: Add assert for regulator VRF12Cong Yang
Add assert for MT6366_VRF12, define a constant macro for 1200000. BUG=none TEST=build board starmie with mt8186. Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74394 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14mb/google/corsola: Add support for VIO18 in regulator.cCong Yang
Add regulator VIO18 support to supply power for STA_HIMAX83102_J02 panel. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: Ie1dd9226b0c4f05f9c9ce6633b7384aa5eb4c978 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74342 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14soc/mediatek: Add support for regulator VIO18Cong Yang
To provide power to MIPI panel STA_HIMAX83102_J02, add support for regulator VIO18. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74341 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
2023-04-14soc/intel/xeon_sp: Don't sort struct device cpus for numaArthur Heymans
Currently the xeon_sp code reassigns struct devices apic_id so that srat entries can be added in a certain order. This is not a good idea as it breaks thread local storage which contains a pointer to its struct device cpu. This moves the sorting of the lapic_ids to the srat table generation and adds the numa node id in each core init entry. Now it is done in parallel too as a bonus. Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14soc/intel/meteorlake: Replace assert with error messageKapil Porwal
Avoid asserts related to CNVi UPDs which are not boot critical. Instead, add error messages which are more helpful in identifying the issue. BUG=none TEST=Boot to the OS on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74370 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-14drivers/efi: Fix linker error when SMM phase uses option APIBenjamin Doron
For security reasons, removing the efivars implementation of the option API was considered. However, this use-case is not the "None" option-backend (CONFIG_OPTION_BACKEND_NONE), so the SMM phase also does not use the no-op in option.h. This causes linker errors when the option API is called. For example, src/soc/intel/common/block/pmc/pmclib.c and src/console/init.c use `get_uint_option`. Minimising code in SMM can be implemented as a follow-up. Change-Id: Ief3b52965d8fde141c12266a716f254dd45559d5 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-14cpu/intel/speedstep: Refactor P-state coordinationKyösti Mälkki
Change-Id: I12462f271821d3d8fe3324d84a65c2341729591e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14intel/i82371eb,speedstep: Use dev_count_cpu()Kyösti Mälkki
Change-Id: I8582d401c72ad44137f117315c5c6869654c3e99 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/intel/common: Fix acpigen use for processor DeviceKyösti Mälkki
Change-Id: Ib4e21732ac31076a1a97a774e03c8466d17c5f29 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14acpi/acpi.c: Follow spec more closely for MADTArthur Heymans
Secondary threads need to be added after the primary threads. Change-Id: I3a98560760b662a7ba7efb46f5f7882fb0f7bb1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-14mb/google/dedede/var/kracko: Add G2touch touchscreen supportRobert Chen
Add G2touch touchscreen support for kracko. BOE NV116WHM-T04 V8.0 with G7500 touch panel sensor IC BUG=b:277852921 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot & test on DUT Change-Id: Ic065d5dc2900c6ccfee09031f7a80cefc391f5dd Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74307 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14mb/google/hades: move PCIEXP_SUPPORT_RESIZABLE_BARS to commonEric Lai
All the variant will use the same dGPU, so make PCIEXP_SUPPORT_RESIZABLE_BARS common. BUG=b:277974986 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: If8618f2da3133c6b52427375c55a69d7014c4881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74371 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-14soc/amd: Clarify ACPI _PRT entry generationKyösti Mälkki
The reference to a constant FCH IOAPIC interrupt count used with GNB IOAPIC was a bit obscure. Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-13AMD binaryPI: Use madt_ioapic_from_hw()Kyösti Mälkki
Read IOAPIC ID and number of interrupts from programmed registers. Change-Id: Ic8ba395bc220fdb691118719f7b32dd7400931f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-13AMD binaryPI: Declare IOAPIC IDsKyösti Mälkki
There is no longer a relation between MAX_CPUS and IOAPIC IDs, start the cleanup with new declarations. Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-13soc/intel/cmd/block: Implement an API to get firmware partition detailsDinesh Gehlot
This patch retrieves details of a specified firmware partition table. The information retrieved includes the current firmware version and other information about the firmware partition. The patch communicates with the ME using the HECI command to acquire this information. BUG=b:273661726 Test=Verified the changes for ISH partition on nissa board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-13mb/google/myst: Disable keyboard reset pinJon Murphy
The keyboard reset is not being used on this board, so disable the functionality. BUG=b:277294460 TEST=None Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74285 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/brya/acpi: Add support for GPS_REQUESTDXSTATETarun Tuli
Implement the GPS_REQUESTDXSTATE function which forces the current D notifier state to re-report. TEST=verified that notifications are forced out when invoked using acpiexec BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I6dab9b793fe1d0b1c875eddbe6ae324d2894efe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: Add support for forcing notifications in DNOT funcTarun Tuli
Currently the DNOT function first checks to see if the current DNOT value has already been reported. Add support to allow forcing regardless if it had been sent already. TEST=confirmed that when enabled, all events notify. When disabled, only events on value change are notified. BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I7a93cca6a8f922574dd46b46572b230755db9aa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: Pass GPS_FUNC_SUPPORT as 8 byte bufferTarun Tuli
Currently the value was being truncated to 4 bytes. Change so that the full 8 byte value is passed. TEST=verified function returns expected value using acpiexec BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Icfc775de680e328a2b240595223d7098fee3dc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: LTOB - Add support for a 8 byte integer to bufferTarun Tuli
This function adds support to convert a integer into a 8 byte buffer TEST=verified returned buffer is as expected using acpiexec BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I89eb50f1452657c26b97eb5609ed956fa8ee8117 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: Correct _DSM GPS function for revision checkTarun Tuli
The logic was not equals, rather than the intended greater than or equal to for checking the minimum GPS revision. TEST=version check passes as expected now BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I66bf1fc32295e1b9e9c41c661ea8e395a1592a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13soc/intel/meteorlake: Hook up UPD CnviWifiCoreKapil Porwal
Hook the newly created/exposed CnviWifiCore UPD up as a chip driver. Enable this option by default to maintain the existing behavior. BUG=b:270985197 TEST=Verified by enabling/disabling the UPD on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/74306 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13soc/intel/common: Update cpu_apic_info_type structSridhar Siricilla
The patch updates total cpu count variable and total P-core count in cpu_apic_info_type structure to `unsigned short int` to address more cores. TEST=Verify the build on Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I46239cc7ad9870e7134955af56b9f6625be2b002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-13mb/google/dedede: Create taranza variantDavid Wu
Create the taranza variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277664211 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_TARANZA Change-Id: Id64e48ff2acd6e827fe586a00376183930ddc7e1 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74295 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750HzBill XIE
Its EDID string is "LTN121AT07L02". The vendor sets BLC_PWM_CTL to 0x31313131. This frequency seems working well on the x200 with this panel, which is said to be LED. Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74182 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-13cpu/x86/mp_init.c: Set topology on BSPArthur Heymans
The BSP might have non-zero lapicid so set the topology accordingly, without assuming it is 0. This fixes a cpu exception on at least Intel Meteorlake. This was caused by FSP CPU PPI being giving incorrect information about the BSP topology. This problem was introduced by 8b8400a "drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer" which sets the PPI struct based on struct device. TESTED on google/rex Change-Id: I3fae5efa86d8efc474c129b48bdfa1d1e2306acf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74374 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13soc/intel/xeon_sp: Fix very small total memory when CXL is enabledJohnny Lin
Processor attached memory should not use reserved_ram_from_to and treat the calculation of gi_mem_size size as 64MB. By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Before the fix running command 'free -g -h' under Linux shows the total memory is only 1.4Gi, after the fix it's showing the expected total memory size 15Gi. Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. On OCP Crater Lake with CXL memory attached, CXL memory can be recognized in NUMA node 1: numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 .. 59 node 0 size: 95854 MB node 0 free: 93860 MB node 1 cpus: node 1 size: 63488 MB node 1 free: 63488 MB node distances: node 0 1 0: 10 14 1: 14 10 Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-13mb/google/nissa/var/yaviks: Update GPIOs to support yavillaShon Wang
Yavilla is a variant of yaviks which is almost identical to yaviks, so is reusing the yaviks coreboot variant. so update the GPIO tables to handle these based on fw_config. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I831b199055c931e7a4a393eeb9e75e83c8ae3c3a Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74264 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavillaTony Huang
Select hdmi vbt bin files based on MB_HDMI field of FW_CONFIG. BUG=b:277148122, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74262 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/nissa/var/yaviks: Update devicetree based on FW_CONFIG for yavillaTony Huang
Yavilla will leverage yaviks FW build. It has one additional USB Type-A0 port, support stylus and support WWAN. Here update devicetree based on FW_CONFIG for yavilla's design. -Enable USB2 port3 and USB3 port1 for USB2/3 Type-A0 -Enable USB2 port5 and USB3 port3 for WWAN -Enable pen garage -Enable rear mipi cam -Enable Synaptics touchpad BUG=b:277148122, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-13soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tomFelix Held
Use the common acpi_fill_root_complex_tom function instead of the SoC- level northbridge_fill_ssdt_generator function that does basically the same. TEST=Resulting coreboot SSDT remains unchanged on Careena. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0f100e0766ce0f826daceba7dbec1fb88492938 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-13mb/google/myst: Add initial I2C configurationJon Murphy
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:275939564 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I44668295fb6ed03992df9d9fc075792e181d1a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74108 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/myst: Enable elogJon Murphy
Enable ELOG for Myst. BUG=b:275938975 TEST=builds Change-Id: I214e2dbaa3bc40c3f4ca68c8ee4b1398446d7090 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74282 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Add ACPI configuration for USB portsJon Murphy
The USB port configuration was derived from the PPR and schematics. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras (World/User facing) 1 Bluetooth transceiver 1 WWAN BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Enable XHCI controllersJon Murphy
Enable the XHCI controllers in the devicetree for myst project. BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Enable internal graphicsJon Murphy
Enable internal graphics on the phoenix soc for myst projects. BUG=b:275900162 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74104 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/amd/birman/port_descriptors_*: use DDI_DP_W_TYPEC type for DDI 2..4Felix Held
DDI 2..4 are the display outputs multiplexed onto the 3 USB type C ports as DisplayPort alternate function, so use the DDI_DP_W_TYPEC connector type for those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I659d62bfb426e3e47214203490c34e9c200beee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74299 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12mainboard/google/skyrim: Fix MP2 FW namingMarshall Dawson
Update the blob type for TypeId0x25_Mp2Fw_MDN_AD03.sbin to subprogram 0. Delete the extra MP2FW line. BUG=b:246770914 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I5418b1ed59e1916b971d2eece9f6a2fd0e51b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-12Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"Michael Niewöhner
This reverts commit 655f7362e13ca49e3e13a822c916c7dc52573d74. Reason for revert: Apparently, the change was not properly reviewed. It not only contains conflicting name and description of the D3COLD Kconfig, but also creates a conflict between existing devicetree and Kconfig options for D3Cold/S3/S0ix. Change-Id: I56ce8f59f8548fc58bc2b3b07c1314e2eed7061c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 16:14:25 +0000