summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2006-08-04final rename orgy. sorry for the inconvenience. This should fix it againStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04ouch. it's 8_2_371. I'll fix it. This commit breaks compilationStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04rename southbridge i440bx to its actual name i8371ebStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03Changelog:Indrek Kruusa
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03slightly changed C.D. Hailfinger's precompressed rom stream patchStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-02Allow setting of serial port speed in EPIA-M config file.Jonathan McDowell
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-02Add newer Via Nehemiah stepping levels.Jonathan McDowell
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-02Geode LX: this patch adds configuration/status/self-test MSR definitionsIndrek Kruusa
for L2 cache and fixes wrong P2D defines. This also patch adds L2 cache initialization for Geode LX CPU. Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-30- Fix some copy bugs and thinkos in the i440bx SMbusRichard Smith
read code. SBbus reads to RAM now work. Yah! - Rename the register constants to something I can look at more easily. - Make the logic flow match the flow from V1 assembly - #if 0 out other SMbus functions that are still broken. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-29- fixup Bitworks/IMS to use private copy of SMbus debug routinesRichard Smith
Re-enable the SPD dump routine in this Bitworks/IMS code and make it work like the Asus/p2b. This avoids having to hack the sdram/generic_dump_spd.c for a single mem controller. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-29- Add support _framework_ for the Asus p2b. Richard Smith
- New superIO winbond/w83977tf - Add single memory controller SBbus debug routine into a file private to the i440bx This adds support the start of support for an Asus p2b mainboard. Current limitations are the same as for the Bitworks IMS board. Reads from the SMbus don't work. Moving dump_spd_registers() into its own private copy solves the problem of having to go hack on the version that included in src/sdram to only do one memory controller. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-28This patch adds support for the AMD LX cpu. Ron Minnich
There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-27"Hey Ron - Attached is a simple patch that enables the upper banks on the Ronald G. Minnich
UART. If the upper banks are enabled, then the Linux 8250 driver knows how to set baud speeds greater then 115200. This was prompted by David Woodhouse. Jordan" git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-24add framework for i440bx chipsetRichard Smith
add support for NSC pc87351 SuperIO add Bitworks/IMS manboard config This is a very basic framework for the i440bx chipset and the Bitworks IMS board that uses it. Most things are structure only. Known issues: - SMbus reads to the RAM SPD come back all zero. - dump_spd_registers() is commented out since it breaks with the default setting of generic_dump_spd.c where it wants 2 memory controllers. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-21restore the old code for enabling flash. The new amd code did not work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-21These changes incorporate steve goodrich'es fixes, and one bug that isRonald G. Minnich
disabled. cs5536: add new entires for SB control etc. cs5536.c: chip_enabled function moved to chip_init, so it only gets run once. IRQ setup improved gx2def.h: new defines added vr.h: new file, with new def's for virtual register control. mainboard config.lb: new entries added for nb and sb control. chipsetinit.c: new controls added -- I forget all the details :-) grphinit.c: new function added northbridge.c: new IRQ control added. FlashChipSetup added, controlled by chip info setupflash struct member. Currently, if enabled, this hangs OLPC in linux PCI scan. chip.h: new struct members added for unwanted device enable, flash setup git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-19this code is for writing the mp table, so only execute it when Stefan Reinauer
we actually have one. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-19move mptable to 960k to 1MStefan Reinauer
https://openbios.org/roundup/linuxbios/issue55 This patch is a little bit enhanced, it keeps the ppc table consistent, which Yinghai's original patch did not. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-19closing issue 44: rename ram clocks in cmos.layoutStefan Reinauer
https://openbios.org/roundup/linuxbios/issue44 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-18fixing aruma build as suggested by mail ;-)Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-18sorry for the inconvenience. this is a test commit.Stefan Reinauer
breaking a build is intentional. It will be fixed in a bit. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-11fix handling of mkelfImage'd binariesStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-27fix interrupt for f5 (ehci)Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-27changes per steve goodrich.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-24fix typo on duplicate line.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-23fix compilation of s2892.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-23match settings per steve goodrich.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-22set up interrupt values for the southbridge, and add a function toRonald G. Minnich
manage them. Make pci_level_irq global. Add value settings for OLPC rev_a board. Comment out no-longer-needed code in olpc mainboard.c -- it is replaced by the settings in Config.lb, and the support in cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-20Fixes from AMD. Tested to build on rumba and olpc, and builds. Ronald G. Minnich
Tested to booting linux on olpc, and boots. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-18delete two empty filesStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-18* delete two empty filesStefan Reinauer
* commit SMM lock code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-18fix idiiot typo I did not catch.Ronald G. Minnich
add support for conditional enable of uarta interrupt. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-18add irq mapper support for OLPC and other boards that need this mappingRonald G. Minnich
done for the gx2 north. tested on OLPC. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-14add k8 processor name handling as required by the k8 revision guide.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-14remove erroneous cache disable.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-12ron forget an svn add.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-12Get rid of #if 01 and debug prints that are compiled out. Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-10changes from AMD for making OLPC video work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-08further development of OLPC. Set vsm size to 35k. add PCI IRQ for USB. Ronald G. Minnich
Set linuxbios size to 28k. Drop debug level to 8. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-26fix two mainboards that have been broken by someone who does not use abuild.shStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-25add DK8HTX support. Ronald G. Minnich
VSAs now required to be nrv2 compressed git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-25fix broadcom/blast, tyan/s2735, tyan/s2891, tyan/s2895 broken by r2307Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18co processor support with s2891Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18init the ECC for BSP and AP at the same time. So reduce init cpus timeYinghai Lu
from 2.1x to 1.1x or from 4x(SERIAL_CPU_INIT) to 1.1x git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18add option to decide to use onboard vga or addon card.Yinghai Lu
CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18cleanup some of the compressed rom stream ugliness -- more to do!Ronald G. Minnich
olpc and rumba can now boot linux out of flash. vsa was resized to 64K. olpc and rumba now used compressed payload -- thanks stefan! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-16Commit for IDE NAND FLASHRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-15OLPC now builds and works just fine.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-12correct it, finally.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-12memory size in cf07Ronald G. Minnich
goodrich pll code disable havedmi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-06Use a real variable to configure rom base for vsa ...Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-05This is to enable COM1 early.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-05reorder early startup so that it might work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04mods for early printing on OLPCRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04fix the treeStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04don't wait core0 started twiceYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04core range and set_init_ram_accessYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04rm unused fileYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04merge zrom to rom_stream and print olen ilenYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-03oops! Slap me on the head for this one. Quick fix for ward untilStefan Reinauer
YhLu's suggestions are all there.. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-03more changes; rumba enet works fine now.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02enable compressed payload per defaultStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02add automatic payload compression method to LinuxBIOSStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02Fall back to pre-broken settings and setup for GX2. Ronald G. Minnich
We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-29typoStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27remove more codeLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27code cleanup, comments addedLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27more code removal and removal of incorrect register settings.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27removing redundant and unneeded calls to functions.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27we don't need msr_initRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-26some todo and comment for ron.Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-25set irq options.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-25builds and should do the right things for sb for interrupt routing.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-25to give ollie a look.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-25fix the msr.lo for olpc 0x20000019Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-24hex values with 0x prefixStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-23Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device()Richard Smith
Default is 255. This allows mainboard configs for working across various groups of boards that differ a device that may not loaded. If you search for a device that is not loaded and max buses is 255 then there can be up to a 8 second delay to search the entire PCI space. Board configs that know thier max bus can limit this search space. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-23fix so that olpc uarts come up enabled.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-21Lower debug progress messages in vt8623 init to debug level rather than error.Jonathan McDowell
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20more 5536 -> 5536 conversionLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20change to 5536Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20change to 5536Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20remove dup filesLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20add cs5536Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20boot to kernelLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20added cs5536Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20add cs5536 directoryLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20add cs5536 directoryLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-19resolve conflictLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18fix adjustment for sizeramRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18add back in missing lineRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18set up timingRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18add ram resourcesRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18added the olpc target and supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-13add SystemPreInit() and supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-13minor modificationLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-11this was in my queue since 2005/10/26Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-11small fixes to get Ward Vandewege's Tyan board booting.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10added chipsetinit function, many defines. addec call to chipsetinit to Ronald G. Minnich
northbridge.c builds fine on lippert git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10add cpureginit to romcc code.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 05:47:54 +0000