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2024-08-30mb/qemu-q35/smihandler.c: add support for SMIs on QEMUKrystian Hebel
qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating Intel chipset. In addition, even though it implements SMI_STS register, QEMU never sets any bits in it. As there is little emulated hardware that can be generating SMI, assume that all SMIs come from APM. This source is used e.g. to disable ACPI (which wasn't working until now on QEMU) and SMMSTORE. Tested by invoking SMMSTORE commands from the payload with SMM logging. Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82558 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30soc/mediatek/mt8196: Enable VBOOT_DEFINE_WIDEVINE_COUNTERSYu-Ping Wu
To support Widevine DRM, enable VBOOT_DEFINE_WIDEVINE_COUNTERS. BUG=b:357976379 TEST=emerge-rauru coreboot BRANCH=none Change-Id: I3760c30b175338165f8e11b59c7cfa830070a19e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-30nb/intel/sandybridge: Fix uninitialised variableArthur Heymans
GCC with LTO caught this. Change-Id: I9f78b9973729bdedb40bd63b8989e94c9c498814 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-30arch/x86/car.ld: Fix overlapping regionsArthur Heymans
The fspm_rc_heap is already accounted for inside .car.data. Some linkers like LLD do not like overlapping regions so remove this. Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84048 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-30soc/intel/apl: Fix building with clang & LTOArthur Heymans
LTO does not like that assert on a constant, so use the more appropriate static assertion. Change-Id: I52094ec825fcec56a9b9fb6b9abc58644c2bf9cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-30soc/intel/pmclib.c: Work around compiler bug -Werror=stringop-overreadArthur Heymans
On xeon-sp this is a zero length array. With GCC LTO this triggers the stringop-overread warning. To work around this change the signature of the function from an array to a pointer. Change-Id: Ieee6e9bddc4e738eb560dd0e69dc3087ac9f5da6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-30soc/intel/meteorlake: Configure DDR5 Physical channel width to 64Arthur Heymans
A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5 Physical channel width to 64" Building with GCC LTO cought this buffer overflow when assigning SPD addresses to a buffer. Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-30ext_stage_cache: Make sure variables are initializedArthur Heymans
GCC LTO incorrectly warns about this it seems. This also exits gracefully from stage-cache code if no smm region is found. Change-Id: Ib1851295646258e97c489dc7402b9df3fcf092c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30soc/cavium: Fix non matching typesArthur Heymans
There is no struct device *dev equivalent of this function. Clang LTO warns about mismatching types. Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-29soc/intel/xeon_sp: Add PCIe root port driverShuo Liu
The driver sets ACPI names for PCIe root ports and its subordinate devices, and fill SSDT for them accordingly. SPR PCIe root port devices are initially supported. TEST=Build and boot on intel/archercity CRB Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-08-29soc/intel/raptorlake: Use updated microcode from blobs repoFelix Singer
This updated microcode fixes the recent voltage issues on the Raptor Lake S platform. Intel provided this specific microcode just as an attachment [1]. Thus, we've uploaded it to our own blobs repository, which is why the path is changed. Microcode signature: sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129 [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/81 Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84132 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29cbmem.h: Change return type of cbmem_get_regionArthur Heymans
The underlying IMD function already returns an integer which indicates success or failure. This removes the need to have initialized variables that need to be checked for NULL later. In some cases this actually adds the appropriate check for returned values. Dying is appropriate if cbmem is not found as it is essential to the bootflow. Change-Id: Ib3e09a75380faf9f533601368993261f042422ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-29lib/rmodules: Add support for LTOArthur Heymans
Change-Id: I9cdda036f330486370e8c4120be5b6a0fd982e99 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84038 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29cpu/x86/smm: Don't do partial linkingArthur Heymans
For LTO we want to link everything in one go. Change-Id: If2c186eb87072e0b80c7e8998b2a0d9bdfddf740 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84037 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29cpu/x86/64bit: Specify linker to be used for cbfs PTArthur Heymans
When clang supports linking bare metal targets it defaults to LLD for linking which linking those raw data structures used to generate CBFS page tables does not fare well. Change-Id: I66fb374a456ea752a97a41426c5a98e6747f3a92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-29mb/google/rauru: Reset USB hub in bootblockYidi Lin
We have to reset the USB hub as early as possible. Otherwise the USB3 hub may not be usable in the payload. This design has been introduced since Cherry. TEST=build pass. BUG=b:317009620 Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29mb/google/rauru: Setup USB host in ramstageMingjin Ge
Add usb host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com> Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-29soc/mediatek/mt8196: Add USB host supportMingjin Ge
Add USB host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com> Change-Id: Ia4efcddac9bf5e04e688648a5c22384075a0b026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-29mb/google/brya/var/nova: Configure scaler I2C GPIOsKenneth Chan
According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL). BUG=b:358439747 TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C. Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-29soc/intel/alderlake: Add Vccin Aux Imon Iccmax settingSimon Yang
According to RDC#646929 Power Map, there are two expected values of VccInAuxImonIccImax and the value has to align with HW design. But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A), hence, provide a config for projects modification. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Modify the register and add a printk to output a debug message to observe whether the value is changing as expected. Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-08-28mb/google/brox/var/lotso: Remove STORAGE_UNKNOWN fw_config optionKarthikeyan Ramasubramanian
With `probe unprovisioned` fw_config rule, there is no need to define an explicit STORAGE_UNKNOWN option. Hence remove it. BUG=None TEST=Build Lotso FW image. Change-Id: Ia170a6e006cb51e95fbaf3efe1106ca907165eca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84094 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28mb/google/brox: Disable Thunderbolt deviceKarthikeyan Ramasubramanian
This feature is not required in Brox devices. Hence disable the concerned device. BUG=None TEST=Build Brox firmware and boot to OS. Ensure that the concerned device is disabled in the OS. Change-Id: I355852c780c552e6f9b2c28508f53580f392c1b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84093 Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
2024-08-28mb/qemu-i440fx/rom_media: Use MEM_REGION_DEV_INIT() for boot_devNico Huber
`boot_dev` can be const, and we can use MEM_REGION_DEV_INIT() as all the values are known at compile time. Change-Id: Icd3757ba4b5e8bfbee9e9c9d18bf0ee71520a8ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84089 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28mb/google/nissa/var/anraggar: Force audio mute to avoid screen flickSimon Yang
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG:b=357764688 BRANCH=firmware-nissa-15217.B TEST:Verfied on Anraggar and cannot reproduce the issue Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-28mb/google/nissa/var/nivviks: Prevent camera LED blinking during bootSowmya V
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. TEST=Build and boot nivviks. Monitor the camera LED blinking during boot. Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-28soc/intel/adl: Prevent unconditional legacy COM ports initializationSubrata Banik
This patch eliminates the LPC_IOE_COMA_EN and LPC_IOE_COMB_EN IO enables from the io_enables variable in the pch_early_iorange_init() function because lpc_io_setup_comm_a_b() is intended to activate legacy COM ports like COM-A (0x3F8 - 0x3FF) and COM_B (0x2F8 - 0x2FF). These COM ports are being activated unconditionally, which is undesirable for the Intel Alder Lake platform and causes traffic over the IO bus. As a result, this code is being removed and platforms that select DRIVERS_UART_8250IO can activate legacy COM ports. BUG=b:354066052 TEST=Able to boot google/redrix to the operating system and confirm that there was no traffic over legacy COMs while being monitored using the eSPI analyzer. Change-Id: I7a6e38bd151f823d37c07ee89a800489122cc209 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84080 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-28soc/intel/alderlake: Remove SOC_INTEL_GFX_MBUS_JOIN configSubrata Banik
This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option. Support for fast modeset joining has been added to the mainline i915 kernel driver (https://patchwork.freedesktop.org/series/130480/), making this coreboot-specific workaround unnecessary. BUG=b:291885733 TEST=Successful build and boot of google/marasov with single and dual displays, no redundant boot splash. Change-Id: I53c08a0e7a40b24db7cc910c5b9adc2376a9bb17 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-28tree: Use boolean for "eist_enable"Elyes Haouas
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-08-27soc/amd/stoneyridge/smihandler: add PSP SMI handlerFelix Held
Now that the PSP SMI handler for flash access is also implemented for the PSP generation 1, the PSP SMI handler can be added to the Stoneyridge code too. The actual PSP SMI handler code will only be added to the build when SOC_AMD_COMMON_BLOCK_PSP_SMI is selected which isn't the default case, so this patch doesn't change the current behavior unless that option is also selected. This SMI handler mainly added for completeness since the PSP firmware blobs released for Stoneyridge are probably lacking the corresponding PSP-side code to send the PSP SMI to the host. At least if I remember correctly the PSP bootloader release for Stoneyridge has the ability to load the secure OS removed and since the secure OS is the runtime component, some part of that is probably what's sending those SMIs to the host. If there are some other PSP bootloader builds that support loading the secure OS, this patch might still be useful for those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78944e2de86bc1e8e277d22a7a8da517622f49a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84077 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27soc/amd/common/psp: move PSP SMI SPI access function prototypesFelix Held
Now that we have the local psp_smi_flash.h header, move the psp_smi_spi_* function prototypes there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12cbbabf6a960836fe0c5dc1424c08550cb66a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84068 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-27soc/amd/common/psp: consistently use uint[8,16,32,64]_t data typesFelix Held
Use the uint[8,16,32,64]_t data types everywhere instead of a mixture of uint[8,16,32,64]_t and u[8,16,32,64] data types for consistency. Suggested-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I36151ecf94619afaf690dbb73834fcff3c51fdac Reviewed-on: https://review.coreboot.org/c/coreboot/+/84067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp: add helper functions to retrieve capability bitsFelix Held
Add helper functions to send the PSP commands to query the fTPM and PSP capability bits as well as the HSTI state. All SoCs using any PSP generation support the MBOX_BIOS_CMD_PSP_FTPM_QUERY command and some generation 1 and all generation 2 PSP SoCs support the MBOX_BIOS_CMD_HSTI_QUERY command, so implement those two in the common psp.c. Only PSP generation 2 supports the MBOX_BIOS_CMD_PSP_CAPS_QUERY command, so implement that one in psp_gen2.c. This code is ported and modified from github.com/teslamotors/coreboot/tree/tesla-4.12-amd Document #54267 revision 1.06 was used as reference for the 1st PSP generation and document #55758 revision 2.04 was used for the 2nd PSP generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e17f994fb332690828c55742262da793e297d99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_def: rename MBOX_BIOS_CMD_PSP_QUERYFelix Held
Rename MBOX_BIOS_CMD_PSP_QUERY to MBOX_BIOS_CMD_PSP_FTPM_QUERY to bring it a bit more in line with document #55758 revision 2.04 and to avoid confusion when another command is added in a follow-up patch. In document #54267 revision 1.06 this command is called MBOX_BIOS_CMD_PSP_QUERY and in document #55758 revision 2.04 it's called MBOX_BIOS_CMD_FTPM_QUERY, so just name it MBOX_BIOS_CMD_PSP_FTPM_QUERY in coreboot which should be the least confusing name for it that still somewhat aligns with the documentation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id085b34363d39528bd125dfb77596d3ed13b6fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84065 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_smi_flash: implement generation 1 supportFelix Held
Implement the request buffer access functions for the PSP generation 1 case. In this case, only the SMI_TARGET_NVRAM is supported, so always return this target NV ID and always return true in the validity checks which in the PSP generation 2 case check if the target NV ID is valid. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e141f846e930bab6972a281745c0180ac52c291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84064 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-08-27soc/amd/common/psp/psp_smi_flash: introduce common data structuresFelix Held
The request buffer data structures differ between the PSP generation 1 and 2 in the way that the generation 2 added the 64 bit target NV ID field right at the beginning of the request buffer data structures. In order to make the data structure definitions common, remove the target_nv_id struct element via the preprocessor in case the SOC_AMD_COMMON_BLOCK_PSP_GEN2 option isn't selected. Since the request buffer data structures are now common for both generations, also remove the 'v2' from the struct names. Document #54267 revision 1.06 was used as reference for the 1st PSP generation and document #55758 revision 2.04 was used for the 2nd PSP generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe0bd2d8e6a5c39cc67a49e7bb3a51ce0900a39a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_smi_flash: factor out generation-specific codeFelix Held
Factor out the code to access the request buffer into PSP generation specific file. This is a preparation for adding PSP SMI flash access support for the PSP generation 1 which has a slightly different request buffer layout. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e18f7ea53592d9fd413ad56e8d137cfc13ad5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27soc/amd/common/psp/psp_def: rework command buffer documentationFelix Held
The existing comment on the mbox_default_buffer struct was outdated and didn't reflect the current state, so rework it to keep it a bit more generic and also add the document number for the newer generations of CPUs. To better document which commands use non-default buffers, add the names of the commands using the non-default buffers to those buffer struct definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I510d953217240243392e8a415358524257bd28b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-08-27arch/arm: Fix building with LTOArthur Heymans
With LTO clang cannot find the aliased symbols. Change-Id: I3d89c093cee2636e648987a06afb0d325b1d96ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-27mainboard/google/rex: Remove HAVE_ACPI_RESUME for Intel Meteor LakeSubrata Banik
This patch removes the HAVE_ACPI_RESUME config option from the Google Rex mainboard configuration. The Intel Meteor Lake SoC does not support S3 (ACPI sleep state) entry/exit, and attempting S3 validation could lead to abnormal platform behavior. This change ensures that `_S3` is not listed as a valid wake source in the DSDT (Differentiated System Description Table) after booting to the OS. BUG=b:351025543 TEST=Booted google/rex successfully and verified that the `_S3` name variable is not present in the DSDT. Change-Id: I730ade628eea84c60ba003a0c871e729b0ee0a9f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84081 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-27mb/dell: Add Latitude E6230 (Ivy Bridge)Nicholas Chin
This was adapted from CB:22693 from Iru Cai, which was based on autoport. I do not physically have this system. Someone with physical access to an E6230 running version A11 of the vendor firmware sent me the VBT after running the command `intelvbttool --inlegacy --outvbt data.vbt`. This new version of the port has not yet been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Original-Change-Id: I8cdc01e902e670310628809416290045c2102340 Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82153 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/dell: Add Latitude E6330 (Ivy Bridge)Nicholas Chin
Mainboard is QAL70/LA-7741P. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A21 of the vendor firmware. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I827826e9ff8a9a534c50250458b399104478e06c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/dell: Add Latitude E6220 (Sandy Bridge)Nicholas Chin
Mainboard is codenamed Vida. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. The VBT was obtained using intelvbttool while running version A14 (latest available version) of the vendor firmware. Tested and found to boot as part of a libreboot build based on upstream coreboot commit b7341da191 with additional patches, though these do not appear to affect SNB/IVB. The base E6430 patch was tested against coreboot main. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82131 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/dell: Add Latitude E6320 (Sandy Bridge)Nicholas Chin
Mainboard is PAL70/LA-6611P. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A22 of the vendor firmware. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82130 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27drivers/intel/opregion.c: Also set vbt_size if size is 0Arthur Heymans
Make sure size vbt_size is initialized. GCC LTO warns about this. Change-Id: I4fcc6c02f898640e9b40d769e1165a4a0fb0fdf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84041 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-08-27mb/dell: Add Latitude E5420 (Sandy Bridge)Nicholas Chin
Mainboard is Krug 14". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A02 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I0283653156083768e1fd451bcf539b4e028589f4 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/dell: Add Latitude E6520 (Sandy Bridge)Nicholas Chin
Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-27mb/hp/snb_ivb_desktops: Add 8200 USDT variantRiku Viitanen
Based on autoport. data.vbt extracted from a running system using "intelvbttool --inlegacy" Like with 8200 SFF, OEM firmware write-protects itself, but not the IFD, GBE or ME regions when FDO jumper is applied. Therefore, ME can be shrunken with me_cleaner and BIOS region moved there. Tested: - Internal flashing from the latest endor BIOS (v2.33) - Sandy Bridge Pentium G630 CPU - RAM: 8+0, 8+4, 8+8 1866MHz DDR3 - SeaBIOS 1.16.2, metest86+ v6, coreinfo, nvramcui & tint payloads - libgfxinit txtmode & corebootfb - VGA, DisplayPort (DVI monitor through an adapter) - Gigabit Ethernet - All front and back USB ports - Booting Void Linux - Rebooting - Mini-PCIe WLAN (PCIe) - Both SATA ports: 2.5" & DVD - PS/2 keyboard and mouse - Fan control - TPM settings in SeaBIOS Untested: - Second Mini-PCIe slot (or is it mSATA): connector not present on my unit - MXM graphics Not working: S3: it sleeps for a few seconds and wakes up on its own Change-Id: I1cba7a5e664758eba7ea2ab8a55658b307d1d173 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79583 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-27mb/hp: Move compaq_8200_elite_sff_pc into snb_ivb_desktops variantsRiku Viitanen
Tested to still boot, SeaBIOS -> Void Linux Change-Id: I03d57c7e76ccdfccd58b2a6deab4dee87b02503a Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79545 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-26mb/dell: Add Latitude E5520 (Sandy Bridge)Nicholas Chin
Mainboard is Krug 15". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A14 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26mb/dell: Add Latitude E6420 (Sandy Bridge)Nicholas Chin
Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82126 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-26mb/dell: Add Latitude E5530 (Ivy Bridge)Nicholas Chin
Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A21 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26mb/dell: Add Latitude E6530 (Ivy Bridge)Nicholas Chin
Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the vbios obtained using intel_bios_dumper while running version A22 of the vendor firmware, which I then processed using `intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt. This was originally tested and found to be working as a standalone board port in Libreboot, though this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26ec/dell/mec5035: Replace defines with enumsNicholas Chin
Instead of using defines for command IDs and argument values, use enums to provide more type safety. This also has the effect of moving the command IDs to a more central location instead of defines spread out throughout the header. Change-Id: I788531e8b70e79541213853f177326d217235ef2 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-26nb/intel/haswell: Move SPD addresses to devicetreeKeith Hui
Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy. Patch also covers recently added Z97 boards using Broadwell MRC. Also update util/autoport to match. abuild passes for all affected boards. autoport builds, but otherwise untested. Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-26vc/intel/fsp: Update ADL N FSP headers from v5021.00 to v5132.00KunYi Chen
Update generated FSP headers for ADL-N to MR5(5132_00) Change-Id: I96fccbb92866fbc18c57187628612fda655cd7a7 Signed-off-by: KunYi Chen <kunyi.chen@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-08-26mb/*/*/early_init.c: Remove unused included southbridgeElyes Haouas
Change-Id: Ia3fda208f5cb2e0d8a1e4da2c4392bc0f326d1ed Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84076 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-25Revert "mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT"Seunghwan Kim
This reverts commit aa6865291a7ddfae4c67fcfc55ebd0c13a376807. Reason for revert: We applied this patch for touchpad stuttering issue for XOl, but the same touchpad problem was reported. So we would revert this change and apply kernel patch (crrev/c/5808335) to avoid the touchpad issue. Change-Id: I78139932e76dbd4128fb325dd70b7dcff3bcc81c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-24soc/mediatek/mt8196: Add I2C driver supportHao Han
Add I2C controller driver. TEST=build pass BUG=317009620 Change-Id: I617ad8a43ce8b492b1a0e5dc06c1f0ffe7d92b5e Signed-off-by: ot_hao.han@mediatek.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/83927 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-24soc/mediatek/mt8196: Initialize watchdogJarried Lin
Add watchdog support for MT8196. TEST=build pass and WDT uart log BUG=b:317009620 Change-Id: I9d5e71aa27d469855c2bd65abc5309d69a018750 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-24soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMAJarried Lin
- Turn off L2C SRAM and reconfigure as L2 cache: Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. - Configure DMA buffer in DRAM: Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass, register(disable_l2c) read ok BUG=b:317009620 Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83925 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-24soc/mediatek: Refactor MMU operation for L2C SRAM and DMAJarried Lin
Refactor mmu operation by - moving mtk_soc_disable_l2c_sram to l2c_ops.c - keeping mtk_soc_after_dram in mmu_cmops.c Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24mb/google/rauru: Initialize flash controller in bootblockJarried Lin
Initialize SPI NOR Flash Controller (SNFC) in the bootblock. TEST=read nor flash data successfully. BUG=b:317009620 Change-Id: I88960ce7a50f67ea6f402884b714cb205836a6d8 Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83924 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24soc/mediatek/mt8196: Add NOR-Flash supportJarried Lin
Add NOR-Flash drivers for flash read/write. TEST=read nor flash data successfully. BUG=b:317009620 Change-Id: Id0a19f0520020f16c4cf9d62da4228a5b0371b91 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83923 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24soc/mediatek: Move SNFC pad_func into MediaTek common directoryJarried Lin
To reduce duplicate pad_func of MediaTek SoCs, move the pad_fun to a common directory. TEST=Build pass BUG=b:317009620 Change-Id: I145233ef887a38251e8fc129b8357f236c5f7a2b Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-24mb/google/skyrim: Combine the function port_descriptors for variantsZheng Bao
Remove the weak function. Combine all the getting descriptors together. BUG=b:279144932 TEST=Build Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83646 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-24mb/lenovo/thinkcentre_m710s: Drop PCH UPDs from PEG deviceNicholas Sudsgaard
Change-Id: Ic0e0864b99c5078e5b84b9183262b3c47ffcb329 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-24soc/mediatek: Require MCU and DRAM blobs to existYu-Ping Wu
When the config of MCU firmware blob such as CONFIG_SPM_FIRMWARE is non-empty, we should always expect the file to exist. Similarly, since the device is unlikely to boot without the DRAM blob (assuming MRC_CACHE doesn't contain valid memory training data), dram.elf should always exist as well. Therefore, remove the check for the existence of the blobs. Build would fail if any of the blobs is missing. Change-Id: I755e7c5a70b34b0c3d3915ab339c65263688aad7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84053 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-24Add initial experimental LTO supportArthur Heymans
This will not succeed in compiling on all target and compiler combinations but at least gets the ball rolling. The change is not invasive. Some notes: - GCC has issues with LTO on ARM - Clang uses LLD automatically on some arch - Clang with LTO fails on x86 as it forwards the linking to GCC for some reason - SMM building succeeds but the binary is empty Change-Id: Ieb9204777fd349542744a8946e2207731c37969c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-24mb/google/nissa/var/nivviks: enable WIFI_SARDavid Wu
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG for WIFI_CATEGORY to choose the right wifi_sar hex file. Below is the file mapping: wifi_sar_0.hex = wifi6 wifi_sar_1.hex = wifi7 BUG=b:345596420 TEST=emerge-nissa coreboot chromeos-bootimage Cq-Depend: chrome-internal:7607427 Change-Id: If8339a2a1d32d3e885ef87ea2ec2847f107f1fbd Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84051 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23mb/google/dedede/var/awasuki: Modify DPTF parametersWei Hualin
Modify DPTF parameters from thermal team. 1. Add TCHG. 2. Modify the charging limit. BUG=b:360066326 TEST=Modify Thermal according to design requirements Change-Id: Ia7050b552656a70da0c992e4f54b02ccb6a7c114 Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83929 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar
2024-08-23soc/mediatek/mt8196: Add GPIO driverJarried Lin
Add GPIO driver for other modules to control GPIO pins. TEST=build pass BUG=b:317009620 Change-Id: I6d1e6ef17660308c8de908697ffba6b5f17ff9ae Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83922 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23soc/mediatek/common: Move GPIO definition to the common directoryJarried Lin
To reduce duplicate gpio_base.h in each SoC folder, move gpio_base.h to mediatek/common folder. TEST=Build pass BUG=b:317009620 Change-Id: I815df8a3083cf04b821165ec834ca98ee71a0c78 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-23soc/mediatek/common: Print error if GPIO raw_id is not in the rangeJarried Lin
TEST=build pass BUG=317009620 Change-Id: I5dffdb9f3e4e7e0d49209e6012893cd246948ee8 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83987 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-23mb/google/nissa/var/riven: Set VccIn Aux Imon IccMax to 25ADavid Wu
Iccmax of VccIn_Aux is 25A with MBVR design. BUG=b:348258637 TEST=Local build successfully and boot to OS normally. Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-08-23mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-upRoger Wang
EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table. BUG=b:358472598 TEST=Build and verified test result by EE team Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83904 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23arch/arm: Add a few ARM targets as supported by CLANGArthur Heymans
Some targets cannot be supported by clang as clang generates slightly larger binaries which the hardware won't accept. This is usually the case with CONFIG_CHROMEOS. Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69747 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23mb/google/nissa/var/nivviks: Correct USB port for PCIE WLAN bluetoothDavid Wu
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN bluetooth companion device. BUG=b:345596420 TEST=Build and test on nivviks, check BRDS is shown in SSDT. Change-Id: I0908ff500434401bf89a5313427cf304f32cf929 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-08-23mb/google/nissa/var/riven: Correct USB port for PCIE WLAN bluetoothDavid Wu
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN bluetooth companion device. BUG=b:345596420 TEST=Build and test on revin, check BRDS is shown in SSDT. Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-23region: Turn region_end() into an inclusive region_last()Nico Huber
The current region_end() implementation is susceptible to overflow if the region is at the end of the addressable space. A common case with the memory-mapped flash of x86 directly below the 32-bit limit. Note: This patch also changes console output to inclusive limits. IMO, to the better. Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-22Makefile.mk: Add a common link_stage function and use itArthur Heymans
A few differences with the original link targets: - 'libs' is now supported on all arch even though only x86 uses it - compiler_rt is included on arch that previously did not (arm). This however has no impact as there compiler_rt is not defined for those arch in xcompile - LIBGCC_FILE_NAME_bootblock is not included, but this was not defined anywhere so this is a noop Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83574 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-22arch/x86: Move oformat definition into the linker fileArthur Heymans
This removes the boilerplate --oformat out of the makefile.mk Change-Id: Ib78934fff4a31c4375da2038efca5027b813b07b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83999 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-22mb/google/brox/var/jubilant: Enable devices on unprovisioned fw_configRen Kuo
Add the condition of unprovisioned fw_config to enable all storages and devices. It's for first boot on all storags and preliminary test in factory when fw_config is unprovisioned. BUG=None TEST=Build jubilant firmware and boot to OS on storages when fw_config is unprovisioned and ensure all devices are enable. Change-Id: Ia14632744c34548e2c201dfc58d82515cdd02df0 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84002 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-22mb/google/brox: Enable storage devices on unprovisioned fw_configKarthikeyan Ramasubramanian
Storage devices are very critical to boot to OS. When probe list is defined for storage devices, all of them get disabled when fw_config is unprovisioned - a typical situation in the factory. Fix this by configuring the storage devices in device/override tree to probe and enable them when fw_config is unprovisioned. BUG=None TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned. Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83984 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-22util/sconfig: Probe device when fw_config is unprovisionedKarthikeyan Ramasubramanian
When fw_config is unprovisioned (eg. in the factory), devices that do not have any probe list are enabled by default and those that have probe list are disabled. On mainboards that support multiple types of boot critical devices (eg. storage) through probing fw_config, all of them are disabled when fw_config is unprovisioned. Hence the devices do not boot to OS. Add sconfig fw_config rule `probe unprovisioned` to enable such devices when fw_config is unprovisioned. BUG=None TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned. Change-Id: I178f821e077912776d654971924d67203a7c43df Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83983 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-08-22mb/google/nissa/var/teliks: Adjust usb2 pin of wlanzengqinghong
Since the voltage value measured by the USB2 pin of the wlan is 500mv, it does not meet the design requirements. Adjusting the port length can reduce the voltage to 450mv, which meets the expected settings. BUG=b:361037189 TEST=1. The voltage measurements are as expected. 2. The Bluetooth and WiFi functions of the wlan module are verified to be normal. Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508 Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-08-22mb/google/volteer/var/drobit: Set UART GPIOs in bootblockMatt DeVillier
Enables early serial console for debugging. TEST=build/boot drobit, verify console output available starting in bootblock on CPU UART (/dev/ttyUSB1) vs ramstage. Change-Id: If94eb8caca3469143433fef06b972050f886be6a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdrCliff Huang
These field defines are SOC-specific. The AUX bias virtual wire field positons are shifted in PTL. In MTL SOC and older: 7:0 GROUP_ID Group ID in PCH GPIO 10:8 BIT_NUM Data bit Position in PCH GPIO 23:16 VW_INDEX VW Index in PCH GPIO In PTL SOC: 15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 BIT_NUM Data bit Position in PCH GPIO 31:24 VW_INDEX VW Index in PCH GPIO BUG=361048817 TEST=boot to OS and use iotools to read AUX Bias Ctrl register to verify the group ID, bit number, and vw index. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-22mb/lenovo/thinkcentre_m710s: Disable DRIVER_LENOVO_SERIALSNicholas Sudsgaard
This mainboard does not have AT24RF08C (Asset Identification EEPROM) and will show "*INVALID*" in the SMBIOS table. Change-Id: If6f948bc4c63c7afdc8b31e1945d3c3beb99883f Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22mb/lenovo/thinkcentre_m710s: Add USB port descriptionsNicholas Sudsgaard
Change-Id: Icc5546a8073c03ce77480b634b367d10d1ad0111 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83992 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22mb/lenovo/thinkcentre_m710s: Add SMBIOS data for PCIe slotsNicholas Sudsgaard
Change-Id: Iaa761108acbf275820ecbec9837b81bc5d64613e Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83991 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22mb/google/dedede: enable Intel CrashLogJędrzej Ciupis
Enable Intel CrashLog diagnostic feature by default on all Google Dedede variants. BUG=b:354834461 TEST=Built for Google Dedede and verifed that CrashLog is enabled by default. Change-Id: Ib0487bd6a5bfdad2a80fd0787e009e48f4527d38 Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-22soc/intel/jasperlake: Add CrashLog implementation for Intel JSLJędrzej Ciupis
Extend support for CrashLog to Intel Jasperlake based platforms. This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7, originally reviewed on https://review.coreboot.org/c/coreboot/+/49943. BUG=b:354834461 TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms and can generate a BERT table, if enabled. Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-22arch/x86/include: Define feature check macros for MCE and MCAShuo Liu
Define feature check macros for MCE (machine check exception) and MCA (machine check architecture). Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-22soc/intel/alderlake: Refactor eSOL for late CSE sync text messageSubrata Banik
This patch extends the eSOL implementation on Alder Lake to render text messages during late CSE sync (from ramstage). Currently, the eSOL is limited to the early boot phase (until romstage) and only displays FSP-M memory training warnings or messages during early CSE sync (at romstage). Platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage, cannot display any eSOL messages, resulting in a brief black screen during CSE firmware updates. This patch implements the following logic to scale eSOL for late CSE sync (at ramstage) without recompiling eSOL code for ramstage: 1. During boot, check if the MRC cache is available. This indicates the need for memory/DRAM training and triggers an eSOL message. 2. For CSE lite SKUs (applicable to CrOS), leverage the `is_cse_fw_update_required` API to check if the current CSE RW firmware version differs from the CBFS metadata file version. If so, trigger an eSOL message indicating a CSE sync is required. 3. If either condition #1 and/or #2 is true, the AP firmware renders an eSOL text message using LibGfxInit for the Alder Lake platform. BUG=b:359814797 TEST=eSOL text messages are displayed during CSE sync and FSP updates. tirwen-rev3 ~ # elogtool list 0 | ... | Log area cleared | 4088 1 | ... | Early Sign of Life | MRC Early SOL Screen Shown 1 | ... | Early Sign of Life | CSE Sync Early SOL Screen Shown 2 | ... | System boot | 197 3 | ... | Memory Cache Update | Normal | Success 4 | ... | System boot | 198 5 | ... | Firmware Splash Screen | Enabled Change-Id: I1c7d4475ed5cf6888df1beebab0641ee4203b497 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83975 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-08-22soc/intel/alderlake: Preserve eSOL for late CSE syncSubrata Banik
This patch prevents the eSOL screen from being wiped out on Alder Lake platforms that use late CSE sync (from ramstage). This allows the eSOL text message to remain visible until ramstage. Currently, the eSOL only functions during the early boot phase (until romstage), so platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage, cannot display any eSOL messages to the user. A future patch will ensure the eSOL remains relevant for CSE sync in ramstage, but this patch is necessary to avoid tearing down the IGD text mode when exiting romstage. BUG=b:359814797 TEST=eSOL text mode is not torn down when exiting romstage. Change-Id: I81548b4057ab95ce3da0dbc69703977baf0581f1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-21soc/intel/ptl: Dump SoC QDF from report_cpu_info in bootblockJamie Ryu
This enables SOC_QDF_DYNAMIC_READ_PMC and adds pmc_dump_soc_qdf_info to report_cpu_info to dump QDF information from bootblock. Change-Id: Iaf6f46cd9be831dde345c3b3728cd66145746d68 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
2024-08-21soc/intel/cmn/pmc: Add pmc_ipc to bootblockJamie Ryu
This adds pmc_ipc to bootblock if SOC_INTEL_COMMON_BLOCK_PMC is enabled. The good place to report SoC QDF can be report_cpu_info in bootblock. QDF read is done by PMC IPC Command, so this adds pmc_ipc to bootblock to enable calling pmc_dump_soc_qdf_info. Change-Id: Id0391eae48fc53cd652acd09e6380ca6802eaf88 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-21mb/google/byra/var/kinox: Add/update VBT filesMatt DeVillier
Kinox has two VBT options, selected via fw_config. Add the second option to CBFS, and update the original file. Extracted from Google_Kinox.14505.704.0.bin. TEST=build/boot kinix, verify firmware display init successful and payload menu visible. Verify correct VBT selected via cbmem log. Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83996 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21mb/hp: Move compaq_elite_8300_usdt into snb_ivb_desktops variantsRiku Viitanen
Tested to still boot, SeaBIOS -> Void Linux Change-Id: Idc61e5d17f4c71fc50cf87c60a5063fc893c1d8c Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79544 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common/block/cpu: Round up the number of waysJeremy Compostella
`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As a result, when the `div' instruction is called to compute the needed number of ways, there could be a remainder. When there is, one extra way should be added to cover `CONFIG_DCACHE_RAM_SIZE'. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83982 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 21:52:12 +0000