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2024-08-23soc/mediatek/mt8196: Add GPIO driverJarried Lin
Add GPIO driver for other modules to control GPIO pins. TEST=build pass BUG=b:317009620 Change-Id: I6d1e6ef17660308c8de908697ffba6b5f17ff9ae Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83922 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23soc/mediatek/common: Move GPIO definition to the common directoryJarried Lin
To reduce duplicate gpio_base.h in each SoC folder, move gpio_base.h to mediatek/common folder. TEST=Build pass BUG=b:317009620 Change-Id: I815df8a3083cf04b821165ec834ca98ee71a0c78 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-23soc/mediatek/common: Print error if GPIO raw_id is not in the rangeJarried Lin
TEST=build pass BUG=317009620 Change-Id: I5dffdb9f3e4e7e0d49209e6012893cd246948ee8 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83987 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-23mb/google/nissa/var/riven: Set VccIn Aux Imon IccMax to 25ADavid Wu
Iccmax of VccIn_Aux is 25A with MBVR design. BUG=b:348258637 TEST=Local build successfully and boot to OS normally. Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-08-23mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-upRoger Wang
EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table. BUG=b:358472598 TEST=Build and verified test result by EE team Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83904 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23arch/arm: Add a few ARM targets as supported by CLANGArthur Heymans
Some targets cannot be supported by clang as clang generates slightly larger binaries which the hardware won't accept. This is usually the case with CONFIG_CHROMEOS. Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69747 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23mb/google/nissa/var/nivviks: Correct USB port for PCIE WLAN bluetoothDavid Wu
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN bluetooth companion device. BUG=b:345596420 TEST=Build and test on nivviks, check BRDS is shown in SSDT. Change-Id: I0908ff500434401bf89a5313427cf304f32cf929 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-08-23mb/google/nissa/var/riven: Correct USB port for PCIE WLAN bluetoothDavid Wu
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN bluetooth companion device. BUG=b:345596420 TEST=Build and test on revin, check BRDS is shown in SSDT. Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-23region: Turn region_end() into an inclusive region_last()Nico Huber
The current region_end() implementation is susceptible to overflow if the region is at the end of the addressable space. A common case with the memory-mapped flash of x86 directly below the 32-bit limit. Note: This patch also changes console output to inclusive limits. IMO, to the better. Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-22Makefile.mk: Add a common link_stage function and use itArthur Heymans
A few differences with the original link targets: - 'libs' is now supported on all arch even though only x86 uses it - compiler_rt is included on arch that previously did not (arm). This however has no impact as there compiler_rt is not defined for those arch in xcompile - LIBGCC_FILE_NAME_bootblock is not included, but this was not defined anywhere so this is a noop Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83574 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-22arch/x86: Move oformat definition into the linker fileArthur Heymans
This removes the boilerplate --oformat out of the makefile.mk Change-Id: Ib78934fff4a31c4375da2038efca5027b813b07b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83999 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-22mb/google/brox/var/jubilant: Enable devices on unprovisioned fw_configRen Kuo
Add the condition of unprovisioned fw_config to enable all storages and devices. It's for first boot on all storags and preliminary test in factory when fw_config is unprovisioned. BUG=None TEST=Build jubilant firmware and boot to OS on storages when fw_config is unprovisioned and ensure all devices are enable. Change-Id: Ia14632744c34548e2c201dfc58d82515cdd02df0 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84002 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-22mb/google/brox: Enable storage devices on unprovisioned fw_configKarthikeyan Ramasubramanian
Storage devices are very critical to boot to OS. When probe list is defined for storage devices, all of them get disabled when fw_config is unprovisioned - a typical situation in the factory. Fix this by configuring the storage devices in device/override tree to probe and enable them when fw_config is unprovisioned. BUG=None TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned. Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83984 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-22util/sconfig: Probe device when fw_config is unprovisionedKarthikeyan Ramasubramanian
When fw_config is unprovisioned (eg. in the factory), devices that do not have any probe list are enabled by default and those that have probe list are disabled. On mainboards that support multiple types of boot critical devices (eg. storage) through probing fw_config, all of them are disabled when fw_config is unprovisioned. Hence the devices do not boot to OS. Add sconfig fw_config rule `probe unprovisioned` to enable such devices when fw_config is unprovisioned. BUG=None TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned. Change-Id: I178f821e077912776d654971924d67203a7c43df Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83983 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-08-22mb/google/nissa/var/teliks: Adjust usb2 pin of wlanzengqinghong
Since the voltage value measured by the USB2 pin of the wlan is 500mv, it does not meet the design requirements. Adjusting the port length can reduce the voltage to 450mv, which meets the expected settings. BUG=b:361037189 TEST=1. The voltage measurements are as expected. 2. The Bluetooth and WiFi functions of the wlan module are verified to be normal. Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508 Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-08-22mb/google/volteer/var/drobit: Set UART GPIOs in bootblockMatt DeVillier
Enables early serial console for debugging. TEST=build/boot drobit, verify console output available starting in bootblock on CPU UART (/dev/ttyUSB1) vs ramstage. Change-Id: If94eb8caca3469143433fef06b972050f886be6a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdrCliff Huang
These field defines are SOC-specific. The AUX bias virtual wire field positons are shifted in PTL. In MTL SOC and older: 7:0 GROUP_ID Group ID in PCH GPIO 10:8 BIT_NUM Data bit Position in PCH GPIO 23:16 VW_INDEX VW Index in PCH GPIO In PTL SOC: 15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 BIT_NUM Data bit Position in PCH GPIO 31:24 VW_INDEX VW Index in PCH GPIO BUG=361048817 TEST=boot to OS and use iotools to read AUX Bias Ctrl register to verify the group ID, bit number, and vw index. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-22mb/lenovo/thinkcentre_m710s: Disable DRIVER_LENOVO_SERIALSNicholas Sudsgaard
This mainboard does not have AT24RF08C (Asset Identification EEPROM) and will show "*INVALID*" in the SMBIOS table. Change-Id: If6f948bc4c63c7afdc8b31e1945d3c3beb99883f Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22mb/lenovo/thinkcentre_m710s: Add USB port descriptionsNicholas Sudsgaard
Change-Id: Icc5546a8073c03ce77480b634b367d10d1ad0111 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83992 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22mb/lenovo/thinkcentre_m710s: Add SMBIOS data for PCIe slotsNicholas Sudsgaard
Change-Id: Iaa761108acbf275820ecbec9837b81bc5d64613e Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83991 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-22mb/google/dedede: enable Intel CrashLogJędrzej Ciupis
Enable Intel CrashLog diagnostic feature by default on all Google Dedede variants. BUG=b:354834461 TEST=Built for Google Dedede and verifed that CrashLog is enabled by default. Change-Id: Ib0487bd6a5bfdad2a80fd0787e009e48f4527d38 Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-22soc/intel/jasperlake: Add CrashLog implementation for Intel JSLJędrzej Ciupis
Extend support for CrashLog to Intel Jasperlake based platforms. This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7, originally reviewed on https://review.coreboot.org/c/coreboot/+/49943. BUG=b:354834461 TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms and can generate a BERT table, if enabled. Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-22arch/x86/include: Define feature check macros for MCE and MCAShuo Liu
Define feature check macros for MCE (machine check exception) and MCA (machine check architecture). Change-Id: I014c25ced1dbe21f35486f8305b1de7669e932d0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-22soc/intel/alderlake: Refactor eSOL for late CSE sync text messageSubrata Banik
This patch extends the eSOL implementation on Alder Lake to render text messages during late CSE sync (from ramstage). Currently, the eSOL is limited to the early boot phase (until romstage) and only displays FSP-M memory training warnings or messages during early CSE sync (at romstage). Platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage, cannot display any eSOL messages, resulting in a brief black screen during CSE firmware updates. This patch implements the following logic to scale eSOL for late CSE sync (at ramstage) without recompiling eSOL code for ramstage: 1. During boot, check if the MRC cache is available. This indicates the need for memory/DRAM training and triggers an eSOL message. 2. For CSE lite SKUs (applicable to CrOS), leverage the `is_cse_fw_update_required` API to check if the current CSE RW firmware version differs from the CBFS metadata file version. If so, trigger an eSOL message indicating a CSE sync is required. 3. If either condition #1 and/or #2 is true, the AP firmware renders an eSOL text message using LibGfxInit for the Alder Lake platform. BUG=b:359814797 TEST=eSOL text messages are displayed during CSE sync and FSP updates. tirwen-rev3 ~ # elogtool list 0 | ... | Log area cleared | 4088 1 | ... | Early Sign of Life | MRC Early SOL Screen Shown 1 | ... | Early Sign of Life | CSE Sync Early SOL Screen Shown 2 | ... | System boot | 197 3 | ... | Memory Cache Update | Normal | Success 4 | ... | System boot | 198 5 | ... | Firmware Splash Screen | Enabled Change-Id: I1c7d4475ed5cf6888df1beebab0641ee4203b497 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83975 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-08-22soc/intel/alderlake: Preserve eSOL for late CSE syncSubrata Banik
This patch prevents the eSOL screen from being wiped out on Alder Lake platforms that use late CSE sync (from ramstage). This allows the eSOL text message to remain visible until ramstage. Currently, the eSOL only functions during the early boot phase (until romstage), so platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage, cannot display any eSOL messages to the user. A future patch will ensure the eSOL remains relevant for CSE sync in ramstage, but this patch is necessary to avoid tearing down the IGD text mode when exiting romstage. BUG=b:359814797 TEST=eSOL text mode is not torn down when exiting romstage. Change-Id: I81548b4057ab95ce3da0dbc69703977baf0581f1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-21soc/intel/ptl: Dump SoC QDF from report_cpu_info in bootblockJamie Ryu
This enables SOC_QDF_DYNAMIC_READ_PMC and adds pmc_dump_soc_qdf_info to report_cpu_info to dump QDF information from bootblock. Change-Id: Iaf6f46cd9be831dde345c3b3728cd66145746d68 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
2024-08-21soc/intel/cmn/pmc: Add pmc_ipc to bootblockJamie Ryu
This adds pmc_ipc to bootblock if SOC_INTEL_COMMON_BLOCK_PMC is enabled. The good place to report SoC QDF can be report_cpu_info in bootblock. QDF read is done by PMC IPC Command, so this adds pmc_ipc to bootblock to enable calling pmc_dump_soc_qdf_info. Change-Id: Id0391eae48fc53cd652acd09e6380ca6802eaf88 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-21mb/google/byra/var/kinox: Add/update VBT filesMatt DeVillier
Kinox has two VBT options, selected via fw_config. Add the second option to CBFS, and update the original file. Extracted from Google_Kinox.14505.704.0.bin. TEST=build/boot kinix, verify firmware display init successful and payload menu visible. Verify correct VBT selected via cbmem log. Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83996 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21mb/hp: Move compaq_elite_8300_usdt into snb_ivb_desktops variantsRiku Viitanen
Tested to still boot, SeaBIOS -> Void Linux Change-Id: Idc61e5d17f4c71fc50cf87c60a5063fc893c1d8c Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79544 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common/block/cpu: Round up the number of waysJeremy Compostella
`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As a result, when the `div' instruction is called to compute the needed number of ways, there could be a remainder. When there is, one extra way should be added to cover `CONFIG_DCACHE_RAM_SIZE'. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83982 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common/block/cpu: Fix ways count computation regressionJeremy Compostella
Commit 16ab9bdcd578612bb3822373547f939eb90afd82 ("soc/intel/common: Calculate and configure SF Mask 2") breaks the computation of the number of ways and as result, all the derived masks. It results in MSR such as `IA32_L3_MASK_1' to be improperly programmed yielding unpredictable NEM issues such as hangs. Indeed, this commit has introduced a backup of 0x1 into %edx before comparing the requested cache-as-RAM size against the way size. When the requested cache-as-RAM is larger, it reaches the second part of the algorithm which computes the necessary number of ways to fit the requested cache-as-RAM. This algorithm uses the `div' instruction. Per specification, the div instruction divides the 64 bits combination of %edx and %eax register. Since 0x1 got backed up in %edx and assuming a `CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000 by the way size instead of 0x200000 which result in a necessary number of ways of 4098 for a way size of 0x100000. This commit clears the %edx register before calling the `div' instruction. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83948 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/common: fix CrashLog size in legacy modeJędrzej Ciupis
Intel's PMC CrashLog size in legacy mode is expressed in DWORDs and therefore needs to be explicitly recalculated to bytes. BUG=None TEST=Built and checked the size in logs Change-Id: I2678d537439c24fbd10aa3ceffee63c9a849d28b Signed-off-by: Jędrzej Ciupis <jciupis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-08-21mb/goog/brox: unlock gpio wake sourcesNick Vaccaro
The power off code in depthcharge disables all GPEs prior to power off. The problem is that for gpio wake sources that are locked, this power off code cannot successfully clear any pending interrupt from that source. This can result in the device incorrectly waking back up after it's been powered off from the firmware dev screen. BUG=b:360380950, b:359692570 BRANCH=None TEST=verify brox DUT is able to power down and stay powered down when selecting the "Power off" button in the firmware dev screen. Change-Id: I5cd36640677996209beb8fe29f522ff8e07ebf00 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-21mb/goog/rex: unlock gpio wake sourcesNick Vaccaro
The power off code in depthcharge disables all GPEs prior to power off. The problem is that for gpio wake sources that are locked, this power off code cannot successfully clear any pending interrupt from that source. This can result in the device incorrectly waking back up after it's been powered off from the firmware dev screen. BUG=b:360380950, b:359692570 BRANCH=None TEST=verify rex DUT is able to power down and stay powered down when selecting the "Power off" button in the firmware dev screen. Change-Id: I3fdc02a82d197fd2b075e0a66c578149cef3a69f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-21mb/goog/brya: unlock gpio wake sourcesNick Vaccaro
The power off code in depthcharge disables all GPEs prior to power off. The problem is that for gpio wake sources that are locked, this power off code cannot successfully clear any pending interrupt from that source. This can result in the device incorrectly waking back up after it's been powered off from the firmware dev screen. BUG=b:360380950, b:359692570 BRANCH=firmware-brya-14505.B TEST=verify brask, nissa, or brya DUT is able to power down and stay powered down when selecting the "Power off" button in the firmware dev screen. Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-21soc/intel/pantherlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch replaces the SoC-specific config option `SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT` with the generic `SOC_INTEL_COMMON_DEBUG_CONSENT`. TEST=Able to build and boot google/fatcat without any functional impact while debugging. Change-Id: I36bbe14d02654ed9dbda21df0d9a6a6769b87754 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch replaces the SoC-specific config option `SOC_INTEL_METEORLAKE_DEBUG_CONSENT` with the generic `SOC_INTEL_COMMON_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/rex0 without any functional impact while debugging. Change-Id: I657d20a38e15eee333a4e45c0c600736148173d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83961 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/alderlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch replaces the SoC-specific config option `SOC_INTEL_ALDERLAKE_DEBUG_CONSENT` with the generic `SOC_INTEL_COMMON_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/redrix without any functional impact while debugging. Change-Id: I9a9c81b72d707f5ed2e1a53c139ee22be0e30068 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-21soc/intel/tigerlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_TIGERLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/volteer without any functional impact while debugging. Change-Id: I3e96b20e7e8b3ce3c2e4884abd315a5cc55fe71d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-21soc/intel/jasperlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_JASPERLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/dedede without any functional impact while debugging. Change-Id: I3e7abaf5fb3a0d5528041af5ce767a15fc738870 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83960 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/elkhartlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot intel/elkhartlake_crb without any functional impact while debugging. Change-Id: Idb8db7230c432792e742218d41d891c529b2114f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83959 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21soc/intel/cannonlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch drops the SoC-specific config option `SOC_INTEL_CANNONLAKE_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/hatch without any functional impact while debugging. Change-Id: Ifad11652b5fa6ff14f713f55a721cdbbfbfde471 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83958 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21mb/acer/g43t-am3: Remove duplicated filesFelix Singer
With commit 26b1a5f62b ("mb/acer/g43t-am3: Rework mainboard for variant mechanism"), the files related to the G43T-AM3 mainboard were supposed to be moved into its own variant directory. However, it seems it was forgotten to delete the old ones and thus remove the duplicates. Change-Id: I450fab074621d21e80216e4667eaf2510b0e14ad Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83985 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-20ec/starlabs/merlin: Remove cezanne-desktop variantSean Rhodes
This board now uses merlin so it can be removed. Change-Id: I6036695ccf80b0a7d6e6463d26e5b32aa6cb9d57 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-20ec/starlabs/merlin: Remove ITE mirror functionalitySean Rhodes
Remove the ITE mirror functionality; all devices will mirror automatically when they exit G3, and this is good enough. Change-Id: I9b82e1b1386b4607dfe7da9b25ba432ec0303cf8 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83629 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-20superio/ite/it8728f: Support setting power state after power failureVladimir Serbinenko
This properly supports power_on_after_fail setting on affected mainboards. Tested on GA-H61M-S2PV Change-Id: I3dcc4f032bc5f629fb916c4122beb8dc096bab20 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-20soc/intel/meteorlake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-20arch/riscv: Remove ram probingMaximilian Brune
Previously RAM probing was necessary for our QEMU-RISCV target in order to find the available amount of memory. Now we get the memory from the devicetree propagated by QEMU, so there is no reason to keep it anymore. Tested: Start QEMU-RISCV and cause an exception to make sure the trap handler still works. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83873 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-20soc/intel/cmn/basecode/debug: Add SOC_INTEL_COMMON_DEBUG_CONSENT configSubrata Banik
This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT, to control the debug interface on Intel SoCs. This eliminates the need for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT. Default values are provided for various debug types: - 0: Disabled - 1: Enabled (DCI OOB + [DbC]) - 2: Enabled (DCI OOB) - 3: Enabled (USB3 DbC) - 4: Enabled (XDP/MIPI60) - 5: Enabled (USB2 DbC) - 6: Enabled (2-wire DCI OOB) - 7: Manual Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value using SoC config override methods. TEST=Able to build google/rex. Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-20soc/intel/elkhartlake: Select SOC_INTEL_COMMON_BASECODESubrata Banik
This patch selects the SOC_INTEL_COMMON_BASECODE option for Elkhart Lake so that future patches can incorporate the common code debug feature with it. TEST=Able to build the EHL platform. Change-Id: I71d95352fe627a7f1912f802aa971ad1ebbbead7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-20mb/google/ovis/var/deku: Set TCC_offset to 12Tony Huang
Adjust settings as recommended by thermal team. Set tcc_offset value to 12 in devicetree. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I0ae97bb0b2dbb2fe8f35221522506ec1f7da47f6 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83971 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-20mb/google/nissa/var/riven: Set PCIE WLAN bluetooth companion deviceSubrata Banik
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:345596420 TEST=Build and test on revin, check BRDS is shown in SSDT. Change-Id: I87cfbdd0b8a97d84a96af373855219c60f39f173 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-20mb/google/nissa/var/nivviks: Set PCIE WLAN bluetooth companion deviceSubrata Banik
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:345596420 TEST=Build and test on nivviks, check BRDS is shown in SSDT. Change-Id: Ib654f22033c68edbc602f14537aaa2151800598d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83943 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-20drivers/soundwire: Support Realtek ALC722 codecAnil Kumar
This patch adds SoundWire driver to support ALC722 audio codec. The existing ALC711 codec driver is refactored to include support for ALC722 device based on config flag. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc711 register "desc" = ""Headset Codec"" device generic 0.1 on end end reference datasheet: Realtek ALC722-CG ver. 0.56 TEST=This driver was tested on Intel RVP with on board ALC722 codec by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Test soundcard binding works and devices are detected and check for audio playback using speaker output. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-19drivers/efi: add optional ESRT-friendly coreboot table tagSergii Dmytruk
EFI System Resource Table (ESRT) is an informational structure that reports basic details about current system or device firmware. This is chiefly used to perform firmware updates. New CONFIG_DRIVERS_EFI_FW_INFO is off by default, enabling it adds DRIVERS_EFI_FW_{GUID,VERSION,LSV} to be used to specify firmware version/update information. Existing forms of versions wouldn't be sufficient because there is no universal way of converting string versions to 32-bit unsigned integers and there are no GUIDs or lowest supported versions. Change-Id: Ic1b768d7bed43edf7ca8e41552087734054de033 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83421 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: coreboot org <coreboot.org@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19mb/google/brox/jubilant: Update fw_configMorris Hsu
Change STORAGE_UNPROVISIONED to STORAGE_UNKNOWN depend on depthcharge setting. BUG=None TEST=emerge-brox coreboot Set STORAGE_UNKNOWN on jubilant, check that NVMe and UFS can boot. Change-Id: I4cfd7322c2940862dfbae46e85522715cd7534c1 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83935 Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2024-08-19mb/google/dedede/var/awasuki: Adjust I2C frequency to less than 400 KHzWei Hualin
Before: I2C2 - 431KHz I2C4 - 413KHz After: I2C2 - 364KHz I2C4 - 370KHz BUG=b:351968527 TEST=Rate of the actual measured machine is pass. Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83906 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-08-19mb/google/brya/var/nova: Set up soundbar-related GPIOsKenneth Chan
Set up soundbar-related GPIOs for updating. BUG=b:358435383 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I517da8de90487533e49e46649c5acf4ccfcc5160 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83936 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19commonlib/bsd: Optimize strnlen()Julius Werner
This patch changes the strnlen() implementation to fix a small issue where we would dereference once more byte than intended when not finding a NUL-byte within the specified amount of characters. It also changes the implementation to rely on a pre-calculated end pointer rather than a running counter, since this seems to lead to slightly better assembly (one less instruction in the inner loop) on most architectures. Change-Id: Ic36768fd3a26e2b64143904e78cd0b52ba66898d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-19mb/google/nissa/var/sundance: Adjust WWAN GPIO sequenceRoger Wang
This patch removes WWAN configuration from the bootblock. It appears that setting it up in the bootblock may not be necessary. Configure in bootblock,the seq will be triggered at the same time. The customer would like us to leave some buffer for EN to RST. BUG=b:357764679 TEST=Build and verified test result by EE team Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83792 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19lib/jpeg: avoid calling malloc and freeNigel Tao
Since commit 1d029b40c9de ("lib/jpeg: Replace decoder with Wuffs' implementation"), a relatively large heap allocation is needed to decode many JPEGs for use as work area. The prior decoder did not need this, but also had many limitations in the JPEGs it could decode, was not as memory-safe and quickly crashed under fuzzing. This commit keeps using Wuffs' JPEG decoder, but it no longer requires any heap allocation (and thus configuring the heap size depending on how big a bootsplash image you want to support). Change-Id: Ie4c52520cbce498539517c4898ff765365a6beba Signed-off-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-08-19vc/wuffs: upgrade to Wuffs 0.4.0-alpha.8Nigel Tao
We were previously at Wuffs 0.4.0-alpha.2. The C file was copied from https://github.com/google/wuffs-mirror-release-c and its hash matches https://github.com/google/wuffs-mirror-release-c/blob/90e4d81a6a8b7b601e8e568da32a105d7f7705e5/sync.txt#L9-L10 $ sha256sum src/vendorcode/wuffs/wuffs-v0.4.c 6c22caff4af929112601379a73f72461bc4719a5215366bcc90d599cbc442bb6 src/vendorcode/wuffs/wuffs-v0.4.c Change-Id: Ie90d989384e0db2b23d7d1b3d9a57920ac8a95a2 Signed-off-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83894 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-18mb/acer/g43t-am3: Add Acer Q45T-AM as a variantJulia Kittlinger
This adds a new board as a variant of the Acer G43T-AM3 with the following prominent changes: * Intel Q45 northbridge (GMCH) instead of a G43 * 4 MiB of flash instead of 2 MiB * Two serial ports (one external, one internal) * A parallel port connector (internal) * An FDD connector * DVI-D instead of HDMI * No Firewire The port was done based on logs and info received via private email. It was only tested on the Acer G43T-AM3 so far, which still builds and works. Change-Id: Ic2654ca4b198bfea409992be14e89702cf67ea50 Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-18mb/acer/g43t-am3: Rework mainboard for variant mechanismMichael Büchler
In preparation for CB:83968, rework the configuration files and move files specific to G43T-AM3 to its own variant directory. Change-Id: I425852f4bdacf7cb6688a5fb845ac3001373262e Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57764 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-17mb/google/brya: Reset XHCI controller while preparing for S5Subrata Banik
This patch calls `xhci_host_reset()` function to perform XHCI controller reset. Currently, the PMC IPC times out while sending the USB-C (0xA7) command during poweron from S5 (S5->S4->S3->S0). On Brya variants, poweron from S5 state results in PMC error while sending PMC IPC (0xA7) to USB-C active ports, log here: localhost ~ # cbmem -c | grep ERROR [ERROR]  PMC IPC timeout after 1000 ms [ERROR]  PMC IPC command 0x200a7 failed [ERROR]  pmc_send_ipc_cmd failed [ERROR]  Failed to setup port:0 to initial state [ERROR]  PMC IPC timeout after 1000 ms [ERROR]  PMC IPC command 0x200a7 failed [ERROR]  pmc_send_ipc_cmd failed [ERROR]  Failed to setup port:1 to initial state [ERROR]  PMC IPC timeout after 1000 ms [ERROR]  PMC IPC command 0x20a0 failed This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0). During poweron the state of USB ports are not the same between S5 and G3 and it appears that the active USB port still is in U3 (suspend) while PMC tries to send the IPC command, which results in a timeout. This patch utilises the S5 SMI handler to reset the XHCI controller using `xhci_host_reset()` prior entering into the S5, it helps to restore the port state to active hence, no PMC timeout is seen with this code change. Supporting Doc=Intel expected to release a TA (Technical Advisory) document to acknowledge this observation and supported W/A for ADL generation platforms. Till that time, keeping this W/A as part of the google/brya specific mainboard alone. Note: other ADL-SoC based mainboards might need to apply the similar W/A. BUG=b:227289581 TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7) during resume from S5. Total Time: 1,045,855 localhost ~ # cbmem -c | grep ERROR No PMC timeout error is observed with this CL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-16mb/qemu-aarch64: Fix include path for device_tree.hNico Huber
Recently merged commit 8cc1d79ed0c3 (mainboard/qemu-aarch64: Get top of memory from device-tree blob) missed a rebase and hence needs the include path updated. Tested `make qemu` for qemu-aarch64. Change-Id: Id669eeaabbc1710bb7e408659f2d79f682427919 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-16mainboard/qemu-aarch64: Get top of memory from device-tree blobAlper Nebi Yasak
Trying to probe RAM space to figure out top of memory causes an exception on AArch64 virtual machines with recent versions of QEMU, but we temporarily enable exception handlers for that and use it to help detect if a RAM address is usable or not. However, QEMU docs recommend reading device information from the device-tree blob it provides us at the start of RAM. A previous commit adds a library function to parse device-tree blob that QEMU provides us. Use it to determine top of memory in AArch64 QEMU virtual machines, but still fall back to the RAM probing approach as a last-ditch effort. Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80364 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-16soc/intel/ptl: Do initial Panther Lake SoC commit till romstageSaurabh Mishra
List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-15mb/google/brox/jubilant: Disable devcies and GPIOs by fw_configMorris Hsu
1.Set unused device's GPIOs to NC based on fw_config. 2.Disable config for nvme, ufs and CNVi based on fw_config. 3.Add fw_config STORAGE_UNKNOWN to enable all storages for the first boot in factory. BUG=None TEST=emerge-brox coreboot chromeos-bootiamge check fw_config messages in ap log verify devices on/off by fw_config on jubilant Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-08-15mb/goog/brya: Don't lock GPP_F15 (FPMCU_INT_L)Nick Vaccaro
Locking GPP_F15 causes DUTs with fingerprint sensor to not be able to correctly power down and stay powered down. This pin does not need to be locked. BUG=b:359692570, b:356750516 BRANCH=firmware-brya-14505.B TEST=`FW_NAME=gimble emerge-brya coreboot chromeos-bootimage`, flash and boot gimble into developer mode, then reboot into dev screen and select the "Power off" button and verify gimble powers off and does not power itself back up. Change-Id: I1c73035b02021b0d1268cd46dcd0841621556ad5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83932 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-15mb/google/dedede/var/awasuki: Enable HECI 1Weimin Wu
The AP console log contains "HECI: No CSE device" and the system cannot be entered. BUG=b:359474142 TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki The "HECI: No CSE device" message for AP log disappered Change-Id: I488056dc8bca2174dd96c28793e3202b7aae890c Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83905 Reviewed-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-08-15Revert "mb/starlabs/starbook/adl: Update the VBT"Sean Rhodes
This reverts commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8. Reason for revert: The latest release of FSP will not boot without a display being connected using this VBT. The original VBT does not have this issue, nor is the original issue that commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8 fixed. Revert it to restore booting when there is no display. Change-Id: I05f9037cd68b8b29e69156e2372a544985f4442e Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-15include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaroundFelix Held
Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since it was defined as unsigned long in AGESA.h, a workaround was needed in cpu/amd/mtrr.h to not have the build fail due to a non-identical redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround without reaming the defines isn't trivially possible, since the stoneyridge romstage.c still ends up including both definitions which can't be easily worked around. Now all non-vendorcode coreboot code uses TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and TOP_MEM2 to avoid this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-15soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possibleFelix Held
Replace 'is_domain0(dev_get_domain(dev))' with 'is_dev_on_domain0(dev)' which is a helper function that does exactly the same, but slightly simplifies the call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b0c52a9176288039e6414a09c3fe0662db79e4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-08-15commonlib/bsd/string: Fix pointer overflow for strnlen()Yu-Ping Wu
When `maxlen` is large (such as SIZE_MAX), the `end` pointer will overflow, causing strnlen() to incorrectly return 0. To not make the implementation over-complicated, fix the problem by using a counter. BUG=b:359951393 TEST=make unit-tests -j BRANCH=none Change-Id: Ic9d983b11391f5e05c2bceb262682aced5206f94 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83914 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2024-08-15soc/intel/alderlake: Correct ISH partition availability checkSubrata Banik
The previous implementation incorrectly assumed that the presence of a UFS device implied the availability of the ISH partition. This is not always true, especially on Alder Lake platforms where ISH may be enabled by default even without UFS. This patch fixes the issue by directly checking for the presence of the ISH device to determine if the ISH partition is available. BUG=b:359440547 TEST=1. Able to dump the ISH version with UFS device: ``` tirwen-rev3 ~ # cbmem -c -1 | grep ISH [DEBUG] ISH version: 5.4.2.7780 ``` 2. Able to dump the ISH version with eMMC device: ``` trulo-rev1 ~ # cbmem -c | grep ISH [DEBUG] ISH version: 5.4.2.7780 ``` Change-Id: I411e36606c0697f91050af40e0636f7c64810e95 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-14mb/google/octopus/var/phaser: Update VBTMatt DeVillier
Extracted from coreboot-Google_Phaser.11297.296.0.bin. Fixes display init on newer LASER14 boards. TEST=build/boot google/phaser, observe display init successful. Change-Id: Icb48edb4e74f147e3458f845d921a15a2d1906da Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83897 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-14soc/intel/adl,mtl/romstage/fsp_params: fix clock request warningFelix Held
If a root port doesn't use a clock request pin, we shouldn't check if this pin number, which defaults to 0 when not set, is already used. This fixes the following spurious warning that was previously printed for each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set and didn't set 'clk_req' to some unused clock request pin number: Found overlapped clkreq assignment on clk req 0 Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC which I'm currently porting coreboot to. Also changing this for Meteor Lake, since they have the same implementation in their romstage fsp_params.c file Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-14mb/google/nissa/var/riven: Disable external fivrDavid Wu
In next phase, riven will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:359062365 TEST=build, boot to OS, suspend/resume work normally. Change-Id: Id5f538b2eda7820a922b8d9ee14b2bae7df3726c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-14mb/google/brox: Remove Mainboard Prepare to Sleep(MPTS) ACPI methodKarthikeyan Ramasubramanian
Brox does not have PCIe WWAN or discrete GPU. Hence no need to power them off during suspend. Hence also remove the MPTS ACPI method. BUG=None TEST=Build Brox firmware and boot to OS. Change-Id: Ia239c3f038ce31934efb0a391350fa0f786e3fcd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83788 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-14commonlib/bsd: Add strcat() and strncat() functionsYu-Ping Wu
An upcoming vboot feature [1] will need strcat() to be defined in string.h. Therefore, add strcat() and strncat() to commonlib/bsd. Remove those functions from libpayload. [1] https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_reference/+/5650810 Change-Id: If02fce0eafb4f6fa01d8bab17d87a32360f4ac83 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-14commonlib/bsd: Add strlen() and strnlen() functionsYu-Ping Wu
Add strlen() and strnlen() to commonlib/bsd by rewriting them from scratch, and remove the same functions from coreboot and libpayload. Note that in the existing libpayload implementation, these functions return 0 for NULL strings. Given that POSIX doesn't require the NULL check and that other major libc implementations (e.g. glibc [1]) don't seem to do that, the new functions also don't perform the NULL check. [1] https://github.com/bminor/glibc/blob/master/sysdeps/i386/strlen.c Change-Id: I1203ec9affabe493bd14b46662d212b08240cced Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83830 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-13mb/google/brox: Do not override GPIO PMKarthikeyan Ramasubramanian
Brox uses Ti50 which always supports long interrupt pulse. Hence no need to override GPIO PM. BUG=None TEST=Build Brox firmware and boot to OS. Perform suspend/resume for 25 cycles. Change-Id: I6a138c1953714bc29570db587594cab8f315a4ec Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83856 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13soc/intel/mtl: enable FSP uGOP config in MTL for eSOLJayvik Desai
This patch updates the platform-specific Meteor Lake early sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP uGOP driver as an underlying technology for rendering eSOL screen. This patch does not change the binary or the system behaviour. BUG=b:352651132 TEST=Able to build google/rex and checked the config in output. Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83769 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13soc/intel/adl: update libgfx config to a generic eSOL configJayvik Desai
This patch updates the early libgfx init config (MAINBOARD_HAS_EARLY_LIBGFXINIT) used for Alder Lake SoC with a generic CrOS/ChromeOS early sign of life config (CHROMEOS_ENABLE_ESOL) This patch does not change the binary or the system behaviour and is only meant to bind the early GFX initialization with a generic eSOL config. BUG=b:352651132 TEST=Able to build google/tivviks and checked the config in output Change-Id: Ibc1b9190ac0e4d25f3c5517d74c9b519bc3bb349 Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83841 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13vc/google/chromeos: Enable eSOL config with libgfx and uGOPJayvik Desai
This patch introduces a new early sign-of-life config option when libgfx or uGOP is enabled for early graphics initialization. BUG=b:352651132 TEST=Able to build google/rex and google/tivviks Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950 Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83705 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13mb/google/brya/var/nova: Enable TCSS XHCI settingPranava Y N
This patch enables the TCSS XHCI in the devicetree to solve the genesys hub enumeration issue. BUG=b:348332200 TEST=Able to build google/nova and ensure lsusb can list genesys hub device. Change-Id: Ic8e25756a2975e884434c4c7e3d587f4c1f0ed0b Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83845 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13commonlib/include: Include <stdint.h> to fix 'SIZE_MAX' undeclared errorSubrata Banik
This change includes the <stdint.h> header file to resolve the compilation error "'SIZE_MAX' undeclared". This issue was introduced by commit hash af0d4bce65df277b56e495892dff1c712ed76ddd (region: Introduce region_create() functions). TEST=Able to build google/rex. Change-Id: I0dbd839e3573d5c74375911903c8f9d6a66bbf28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83886 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13mb/google/nissa/var/pujjoga: Modify GPP_C1 settingLeo Chou
Confirm with EE, the GPP_C1 don't need PU 20K. So modify GPP_C1 setting to remove PU 20k Schematic version: 500E_GEN4S_ADL_N_MB_0418 BUG=b:358162951 TEST=Build and boot on pujjoga. Change-Id: I7ad16cd29ab467d3eac74dab40522c577d91c747 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83818 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-13mb/google/nissa/var/pujjoga: Modify P sensor settingLeo Chou
1. The P sensor need follow WWAN FW_CONFIG to enable/disable 2. Modify GPP_H19 setting to PAD_CFG_GPI_APIC to fix PLT test fail Schematic version: 500E_GEN4S_ADL_N_MB_0418 BUG=b:357998089 TEST=1. Boot to OS and verify the P sensor devices is set based on fw_config. 2. Confirm that the PLT test can pass successfully. Change-Id: Ic3610180c8cf99eba9367e26bfc3666410af19f7 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13mb/google/nissa/var/riven: Add elan touchscreen supportDavid Wu
This change adds the necessary configuration for the elan touchscreen (ELAN9004) device, connected to I2C bus 16. It includes settings for: * HID descriptor * Device description * IRQ configuration * Detection * Reset, stop and enable GPIOs with their respective delays * Power resource handling * HID descriptor register offset BUG=b:348125053 b:348126380 TEST=emerge-nissa coreboot boot with elan TS, make sure elan TS is functional. Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83876 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13mb/asus/p8z77-m: Light DRAM_LED during early bootKeith Hui
Turn on DRAM_LED on the mainboard in early bootblock, and turn it off in ramstage. Primarily an indication if boot fails during raminit, modeled after vendor firmware. This LED is controlled by GPIO07 on the super I/O. Boot tested on hardware. Change-Id: I549b51375d1ef056d5fc01871bfe62d60b8a01cb Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-08-12drivers/intel/fsp2: Add config for FSP uGOP eSOLJayvik Desai
This patch introduces a new configuration option, FSP_UGOP_EARLY_SIGN_OF_LIFE, to the FSP driver. This enables uGOP support using FSP-M for the early sign-of-life feature in SOC. BUG=NA TEST=Able to build google/rex and checked the config in output. Change-Id: Ic0426ff7974a141ae9188b0098677b4cc97aee36 Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-11tree: Use boolean for pch_hda_sdi_enable[]Elyes Haouas
Change-Id: I27568d1205216f697b48ffb09ce5208505718978 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83863 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11soc/intel/xeon_sp/gnr: Remove VPD from GNR KconfigGang Chen
Remove the unused config VPD from GNR Kconfig. Change-Id: I3fc45ba05df5fc23e326081d6ce9e53b2046464c Signed-off-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82975 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-08-11soc/intel/ptl: Do initial Panther Lake SoC commit till bootblockSaurabh Mishra
List of changes: 1. Add required Pather Lake SoC programming till bootblock. 2. Include only required headers into include/soc. 3. Include PTL related DID, BDF. 4. Includes additional minimal code required to compile the PTL SoC and google/fatcat mainbaord. 5. Ref: Processor EDS documents vol0.51 #815002 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11mb/google/brox/jubilant: update overridetree for dptf settingsMorris Hsu
Update dptf settings for EVT. BUG=None TEST=emerge-brox coreboot chromeos-bootiamge Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842 Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11mb/google/brox/jubilant: update overridetreeMorris Hsu
Update touchpad settings. BUG=b:342867386 TEST=ensure touchpad is working. Change-Id: Ibf62470b7fd921065201894a63d7e2a83dad53ce Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2024-08-11mb/google/nissa/var/teliks: Configure TPM IRQ for telikszengqinghong
Add TPM TIS ACPI interrupt configuration, set teliks's `TPM_TIS_ACPI_INTERRUPT` to 13. BUG=b:352263941 TEST=emerge-nissa coreboot Change-Id: Iaed51e0bb8abac0ed0b35bfcf12e95fd34f92242 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83832 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-11mb/google/nissa/var/teliks: Add DP AUX BIAS connectzengqinghong
Because one side is not displayed when using type-c projection, the configuration of DP AUX BIAS to SOC direct connection is added. BUG=b:352263941 TEST=DP function of MB and DB workable Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 09:03:45 +0000